Abstract: The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area.

Abstract: Embodiments include writing a first data value to a validation variable through a fixed programming interface, where the validation variable includes multiple fields that correspond to multiple fields within a persistent variable. Contents of the validation variable are subsequently read through the fixed programming interface. When the validation variable contents include one or more differences from the first data value, one or more errors are identified.

Abstract: An integrated circuit card includes a central processing unit, a memory and an abnormal condition detector. The memory stores data to be processed by the central processing unit. The abnormal condition detector detects whether at least one operating condition of the integrated circuit card is within one of a suspend region or a reset region. The abnormal condition detector controls an operation of the central processing unit in accordance with the detection.

Abstract: A testing apparatus for semiconductor device comprises test controllers 10-1, 10-2, . . . , 10-N, variable clock generators 24-1, 24-2, . . . , 24-N which are provided respectively associated with the test controllers 10-1, 10-2, . . . , 10-N and which output variable clock signals having certain phase relationships with the control signals outputted from the associated test controllers 10-1, 10-2, . . . , 10-N, test pin groups 12-1, 12-2, . . . , 12-N which synchronize with the variable clock signals and test devices under test based on the control signals, an N×N switch matrix 16 which supplies the control signal from the test controller 10-i of the test controllers 10-1, 10-2, . . . , 10-N to the test pin group 12-j assigned to the test controller 10-i, and an N×N switch matrix 18 which supplies to the test pin group 12-j the variable clock signal from the variable clock generator 24-i of the variable clock generators 24-1, 24-2, . . . , 24-N, which is associated with the test controller 10-i.

Abstract: A latent error detector may be configured to reveal latent errors within a plurality of components within a computer system. The latent error detector may be configured to access configuration data specifying one or more types of components and one or more modules for each type of component. The one or more modules for each type of component may be configured to initiate a component-specific operation to reveal a latent error within the one or more components of the one or more types of components. A framework may be configured to call the one or more modules for each type of component. The framework may be configured as a main software module to access the one or more modules.

Abstract: Provided is a method for restarting a computing platform to a state in which applications run in less time than an initial start, including powering on a computing platform having a plurality of devices; identifying one or more of the devices which are not critical to running applications; storing information about the non-critical devices; restarting the computing platform; retrieving the information about the non-critical devices; disabling the non-critical devices; performing at least one of testing and initialization of at least one device of the plurality of devices that are critical to running the applications before the restart is completed; offloading at least one of testing and initialization of at least one of the non-critical devices; enabling devices which are not non-critical; and enabling the non-critical devices after the restart is completed.

Abstract: An image forming apparatus including: a registration section which registers information on a diagnostic mode, where an operation mode to diagnose inside the image forming apparatus based on error information is assumed to be the diagnostic mode; an error detecting section which detects an error in the apparatus and outputs error information; and a control section which, when the error detecting section outputs error information, receives the information on the diagnostic mode corresponding to the error information from the registration section, and executes problem solution and recovery of the apparatus.

Abstract: The testing of components of processing environments is facilitated by minimizing the resources needed for testing. The requirements for storage and/or storage components, in one embodiment, is minimized by reducing the amount of data to be stored in storage associated with the component being tested, and/or simulating a larger pool of storage than is actually provided. To accomplish these tasks, a filter is used, which may be placed in different locations along a data path from the component to storage.

Abstract: A redundant array of independent disks (RAID) system comprises N storage arrays. Each of the N storage arrays comprise a target processing module and 1 to M hard disk drives, where M and N are integers greater than 1. A data processing module assigns a first data storage request for a first data block to one of the target processing modules for processing of error checking and correcting (ECC) data for the first data block. The one of the target processing modules sends a first portion of the first data block and ECC data associated with the first data block to another of the target processing modules.

Abstract: A method, an apparatus, and a computer program are provided for generating an error detection state and correction of code patterns. Generally, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment is difficult. A circuit, however, can be employed that periodically detects the functionality of the dI/dt circuit to indicate success or failure. When errors are detected, the circuit allows for erroneous codes to be replaced with accurate ones. Using this circuit, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment can be more easily achieved.

Abstract: A system for initiating a connection to a wireless network using a wireless modem, where the system maintains the connection to the wireless network when the wireless modem becomes idle. The system determines that there is a problem using the wireless modem by monitoring the status of the wireless modem. In response to a determination that there is a problem using the wireless modem, the system automatically cycles power to the wireless modem and again initiates a connection to the wireless network using the wireless modem. The system may be implemented by an apparatus having a power control device with a power outlet coupled to a wireless modem. The control device controls power to the power outlet according to received power control commands that are based on the status of the wireless modem.

Abstract: A computer peripheral connecting interface system configuration debugging method and system is proposed, which is designed for use in conjunction with a computer platform that is equipped with a particular type of peripheral connecting interface, such as a PCI (Peripheral Component Interconnect) interface, for automatically finding errors in the PCI system configurations of a group of peripheral devices connected to the PCI peripheral connecting interface, and if errors are found, capable of automatically generating an electronic error report. This fully-automatic debugging capability can help software engineers to more conveniently and efficiently correct the errors in the PCI system configurations on a computer platform.

Abstract: One preferred embodiment of the present invention provides a system and method for checking the performance of sub-systems in an inter-messaging network of voice mail systems. This preferred embodiment includes a network diagnostic device that connects to the inter-messaging network and requests a test data file to be retrieved from all the voice mail sub-systems in the inter-messaging network. The requests for the test data file are generated without user interaction. Accordingly, the performance of the inter-messaging network in its entirety, as represented by the results of the request attempts, is assessed according to a defined level of performance, such as a preferred time limit. Other systems and methods are also provided.

Abstract: While executing a command that accesses a sector on a disk-shaped recording medium placed in a data recording device, an address of a sector where it is difficult to read data is recorded in a memory. After that, a determination is made as to whether or not the data recording device is executing a command. If it is judged that the data recording device is not executing a command, the address of the sector is read from the memory, and then a bad sector is searched for by detecting whether or not it is difficult to read data from each of surrounding sectors adjacent to the sector, the address of which has been read.

Abstract: A fault tolerant graphics controller that generates error codes for graphics commands and checks the error codes before the graphics controller executes the command. The error code generator may be configured to detect and correct errors or to just detect errors. If an error is detected or an uncorrectable error occurs, the host computing system can be informed or interrupted, the erroneous command can be flushed from the graphics controller or the commands before and after the possibly erroneous command can be stored to help determine the erroneous command. Error codes can be generated on a block basis and stored in the frame buffer, thereby having minimal impact on system performance.

Abstract: The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area.

Abstract: A method, system, and data processing system for dynamic detection of problem components in a hot-plug processing system and automatic removal of the problem component via hot-removal methods without disrupting processing of the overall system. A data processing system that provides a non-disruptive, hot-plug functionality is designed with a additional logic for initiating and/or completing a sequence of factory level tests on hot-pluggable components to determine if the component if functioning properly. When a component is not functioning properly, the OS re-allocates the workload of the component to other component so the system, and when the OS completes the re-allocation, the service element initiates the hot removal of the component so that the component is logically and electrically separated from the system.

Abstract: A method and apparatus and for detecting faults in components of a continuous process such as a steam generator. A model of the process is developed using a modeling technique such as advanced pattern recognition and the model is used to generate predicted values for a predetermined number of the operating parameters of the process. Statistical process control methods are used to determine if the difference between the predicted and actual measured values for one or more of the parameters exceeds a configured statistical limit. A rule set is used to indicate an actual or probable fault in a component of the continuous process.

Abstract: A processing system comprising: i) processor core; ii) a memory; iii) N peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the N peripheral devices that transfers bus request packets between the processor core, the memory, and the N peripheral devices. The communication bus comprises debug circuitry for capturing bus transaction data associated with a bus transaction between a first of the peripheral devices and a second of the peripheral devices and transferring the captured bus transaction data to an external test device.

Abstract: A safety device for a stored-program control includes a controller which exchanges data with a stored-program control and, via a bus controller and a bus system, with the peripheral to be controlled. A memory is provided, in which safety-relevant data of the stored-program control is stored, which is accessible to the controller.

Abstract: A method and system for a reject management protocol within a back-end IC manufacturing process. In one method embodiment, the present invention implements a tracking process for a die-strip. The present invention also maintains an electronic die-strip map database, and utilizes the tracking process to update the electronic die-strip map database as the die-strip moves in an in-line fashion from one sub-station to another within the manufacturing process. Information used to update the database can originate from one or more automated visual camera systems used for quality assurance. In so doing, the present invention categorizes the die on the die-strip based on information maintained by the electronic die-strip map database. This information can be used for die sorting and for die rejection. In one embodiment, an identifying code is placed on each die strip that can automatically identify the die-strip using the automated camera systems.

Abstract: When a remote service terminal is to be connected, the present invention executes the following procedure. The lobby terminal selects a clerk terminal which can correspond to a consulting detail and the selected clerk terminal is connected to the lobby terminal and carries out a remote consultation. When the lobby terminal selects an unattended agent server, the lobby terminal retrieves the past reply corresponding to the consulting detail of the user and displays it at the lobby terminal. When the clerk terminal corresponding to the consulting detail becomes connectable while the unattended agent server is corresponding to the user of the lobby terminal, the unattended agent server takes over the consulting detail to the clerk terminal. When there is no clerk terminal to be changed when the consultation is over, the unattended agent server sends the inquiry data which is to be replied to the user asynchronously to the clerk terminal by a communication means separately.

Abstract: Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.

Abstract: An element for carrying out and documenting a program or test sequence allows specific functions to be carried out. The element has at least one control input to which an external control signal can be supplied, and a variable can be varied in the element as a function of the external control signal. The process of carrying out a particular function can be varied by the element in such a manner that, when the variable has a specific value (“0”) and the external control signal is at a first signal level, the variable assumes a value (not equal to “0”) which differs from the specific value; and when the variable is at that specific value and an external control signal which is at the first signal level is once again applied, the variable remains at that specific value.

Abstract: To provide a system for monitoring data transmitted between parts of an electronic machine. The system includes a mirror memory circuit that is subjected to writing and reading of data in the same manner as a memory circuit based on first data to be supplied from a memory controller to a memory circuit, and a signal sampling circuit that stores in a sampling memory circuit the first data as well as second data read out of the mirror memory circuit. The sampling memory circuit stores exact copies of the first data supplied from the memory controller to the memory circuit and exact copies of the second data supplied from the memory circuit to the memory controller. Therefore, it is possible to monitor the data transmitted between the memory controller and the memory circuit.

Abstract: A method and system for managing uncorrectable data error (UE) conditions as the UE passes through a plurality of devices in a central electronic complex (CEC) is disclosed. The method and system comprises detecting a UE-RE by at least one device in the CEC; and providing an attention signal by at least one device to a diagnostic system to indicate the UE-RE condition. The method and system further includes analyzing the UE-RE attention signal by the diagnostic system to produce an error log with a list of failing parts and a record of the log. A method and system in accordance with the present invention provides a new fault isolation methodology and algorithm, which extends the current capability of a service processor runtime diagnostic code (PRD). The method and system in accordance with the present invention allows for correct error isolation and for surfacing of appropriate service action messages on a processing system that has successfully recovered from an uncorrectable data error (UE) condition.

Abstract: Methods, systems, and computer program products that automatically generate and track undo information so that the developer of a user interface object need not be responsible for generating and tracking undo information. Change notifications for changes to an object within a visual user interface designer are processed. Data representing an initial state of the object prior to the changes and data representing a subsequent state of the object after the changes is persisted. From the persisted data, an undo unit is prepared for undoing the changes to the object. The undo unit may comprise a transaction of multiple changes made to the object. Each undo unit may identify corresponding routines for undoing and redoing the actions included within the undo unit. An undo unit may be stored until an undo/redo notification is received, and then used to undo/redo the changes represented by the undo unit.

Abstract: A method and system for managing uncorrectable data error conditions from an I/O subsystem as the UE passes through a plurality of devices in a central electronic complex (CEC) is disclosed. The method and system comprises detecting a I/O UE by at least one device in the CEC; and providing an SUE-RE (Special Uncorrectable Data Error-Recoverable Error) attention signal by at least one device to a diagnostic system that indicates the I/O UE condition. The method and system further includes analyzing the SUE-RE attention signal by the diagnostic system to produce an error log with a list of failing parts and a record of the log. A method and system in accordance with the present invention provides a new fault isolation methodology and algorithm, which extends the current capability of a service processor runtime diagnostic code (PRD). The method allows for the accurate determination of an error source and provides appropriate service action if and when the system fails to recover from the UE condition.

Abstract: An integrated apparatus and method for testing a very large scale integration (VLSI) device is implemented. An interface between automatic test equipment (ATE) and a device under test (DUT) includes a switch and associated control logic that mediates data transfer between high speed buses coupled to the DUT. Additionally, traffic may be switched to a port connected to a bus coupled to the ATE. This bus need not operate at the full speed of the I/O buses of the DUT. The switch also couples to a static random access memory (SRAM) data cache array which may be used for delayed echo of data between ports. Additionally a logic analyzer in the interface may be used in conjunction with the switch and cache to selectively capture data transferred between the DUT and ATE. The configuration of the switch is programmable depending on the testing performed on the DUT.

Abstract: An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.

Abstract: A method and mechanism operating within the Application layer of the architectural model for maintaining high availability in a two node computer network. A backup connection is created wherein a second network card is added to each node of a two node network and a crossover cable is coupled between them. Each backup network card is configured with dummy parameters and taken down upon startup. A failover mechanism operating within the Application layer monitors the original, primary network connection. Upon detecting a failure of the primary connection, the failover mechanism halts monitoring of the primary connection, configures the backup network interface with the parameters of the primary network interface, and brings up the backup interface.

Abstract: A programmable unit having an OCDS module and a method for using an external debugger to debug the programmable unit equipped with the OCDS module are described. The programmable unit is distinguished in that it has a reset management device by use of which it is possible to determine whether the OCDS module should or should not also be reset when the programmable unit is reset. Therefore, the debugging is not interfered with or interrupted by the programmable unit being reset before or during the debugging process.

Abstract: Disclosed is a diagnostic method for a logic used in a vehicle in which a sequence of a plurality of logic operations is predetermined, the method comprising the steps of assigning an ID to each logic operation; comparing an ID of a logic operation that should be performed (“correct logic operation”) with an ID of a logic operation to be performed (“present logic operation”) before the present logic operation is performed; and determining that an error has not occurred in the case where the correct logic operation corresponds to the present logic operation, and determining that an error has occurred in the case where the correct logic operation does not coincide with the present logic operation.

Abstract: An on-chip debugging system emulator is disclosed. The on-chip debugging system emulator includes an on-chip debugging host processor. The on-chip debugging system emulator also includes an on-chip debugging emulator processor configured to emulate the on-chip debugging functions of a silicon chip. The on-chip debugging system emulator includes a hardware interface between the on-chip debugging host processor and the on-chip debugging emulator processor.

Abstract: A method for performing a load flow test among a number of IEEE 1394 controllers is provided. The IEEE 1394 controllers are disposed on a number of interface cards individually while the interface cards are placed in a host or several hosts. The method includes the following steps: The interface cards are first initialized. Then, the master interface card starts to perform the load flow test. After that, the status of every interface cards is checked for confirming whether an error occurs or not. If the error occurs, debugging is performed. If not, the slave interface cards checks the result of the load flow test. The invention can fully control the buffer and monitor the memory since the test method is not performed under the driver structure in Windows Operating System. It is therefore convenient to test in a load flow environment by using this method.

Abstract: In a computer comprising a plurality of plug-in cards and peripheral plug-in cards interconnected through a bus, plug-in places of the bus are designed as system plug-in places and peripheral plug-in places. A clock line is routed along respective clock jack contacts at the plug-in places and comprises an associated clock plug-in contact on a plug-in card. A universal plug-in card (14) comprises a control plug-in contact (24) which is capable of being connected with a control plug-in jack (22) of the bus (12) and activates a clock output signal of the plug-in card (14) which may be supplied to the bus (12) via the clock plug-in contact (C_LK0). The card (14) is capable of working in a peripheral mode in which a clock plug-in contact (C_LK0) acts as a clock input.

Abstract: In a computer system which allows simultaneous operation of multiple processes, a software watchdog process operates to monitor a primary process through operating system calls. If the response to an operating system call shows that the primary process is not operating or is over utilizing CPU time, then the primary process is restarted. The software watchdog process may also check and correct configuration and data files before restarting the primary process. Alternatively, rather than using operating system calls, the software watchdog process and primary process may communication through a loop back TCP/IP address for monitoring purposes.

Abstract: Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.

Abstract: In a method for preferably assigning, to a client, setting information necessary for connection to an external network, an address assignment processing section of a server which is a coordinator server at that point assigns an IP address and GW address and returns the assigned information to the client in response to an address assignment request from the client. The address assignment processing sections of servers which will become, through a server circulation process, the coordinator server respectively at subsequent points in time also function similarly. The client connects to the Internet via one of the gateways by referring to the GW address designated in the response from the server. A server which recognized that a failure has occurred in another server changes the GW address assigned to the client in order to switch the communication route for the client to access the Internet.

Abstract: Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.

Abstract: A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested.

Abstract: A method and system for providing diagnostic services for a computer system is provided. The diagnostic application presents to the user of the computer system a graphical representation of a computer system (202). The user is able to click on graphical components of the graphical representation. The diagnostic application performs diagnostic services on the particular component clicked on by the user. The diagnostic application may determine if the most recent version of the appropriate software driver is installed in the computer system. The diagnostic application may perform diagnostic tests on the clicked component. The diagnostic application may also permit the user to access online diagnostic services to permit the user to access the most recent version of the applicable software driver, communicate with a diagnostic support specialist, or receive additional diagnostic tools from a location remote from the computer system.

Abstract: In a distributed computer program, active software probes in the form of small functions built into an application are invoked by another application. When invoked, an active probe provides a positive response if the service being requested is available from the probed package. If the service is not available, the probe will fail alerting the software package installer that there is a problem. The active probes thus perform a functionality check for the software package, not a check merely based on the package's release number. Because the probe is active, it is capable of checking for subtending capabilities that the calling application may not realize are necessary for this service. This ensures full coverage of the test while hiding some implementation details from the calling application.

Abstract: A PCI debugging device, method and system. The PCI interface includes a request signal, a grant signal and a target ready signal. The system has a debugging mode such that current grant signal will be retained as long as the request signal remains activated. Using a decoding comparator circuit, the debugging device decodes an instantaneous command signal from the PCI interface and compares with a user-defined wait-to-debug command signal so that an identical command signal for activating the request signal can be generated. Due to the continuous activation by the request signal on the PCI interface, the system halts to display system data via a display circuit so that debugging is facilitated.

Abstract: A communication monitoring system is comprised of a semiconductor device manufacturing apparatus connected with a network, a host computer connected with the network, and a monitoring unit connected with the network. The semiconductor device manufacturing apparatus and the host computer carry out a sequence of communications through the network about a process of the semiconductor device manufacturing apparatus. The monitoring unit takes therein a first set of packets of the first sequence of communications and a second set of packets of the second sequence of communications through the network between the semiconductor device manufacturing apparatus and the host computer, and determines whether the communication between of the semiconductor device manufacturing apparatus and the host computer is normal or defective, based on the packets of the first and second sets.

Abstract: To provide a system for monitoring data transmitted between parts of an electronic machine. The system includes a mirror memory circuit that is subjected to writing and reading of data in the same manner as a memory circuit based on first data to be supplied from a memory controller to a memory circuit, and a signal sampling circuit that stores in a sampling memory circuit the first data as well as second data read out of the mirror memory circuit. The sampling memory circuit stores exact copies of the first data supplied from the memory controller to the memory circuit and exact copies of the second data supplied from the memory circuit to the memory controller. Therefore, it is possible to monitor the data transmitted between the memory controller and the memory circuit.

Abstract: A PC interval timer test method used in a personal computer to test the abnormality of the interval timer of a PC (personal computer) by: calculating the difference between the periodic interrupt frequency of the PC's CMOS Real Time Clock (R.T.C.) and the interval timer interrupt frequency within the same time period, and then judging the result by comparing the value of the difference thus obtained with the set maximum allowable value of error of the CMOS R.T.C.'s periodic interrupt frequency. The maximum frequency of the CMOS R.T.C. can be as high as 8192 Hz, so that the test error can be as minor as below 1/8192.

Abstract: A device and method for a peripheral adapter of a dual SCSI bus enclosure is described. An adapter can operate alone or in pairs to provide different modes of operation, including simplex, duplex, and cluster. When used in pairs, two adapters interconnect internally to the enclosure through internal cross-coupling bus repeaters that can be selectively enabled or disabled. The adapters are hot-swappable and have the ability to automatically self configure. In the cluster mode, the adapter supports failover capability from a master adapter to a redundant adapter.

Abstract: A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are provided. The method and apparatus are particularly applicable to computer systems with memory circuits, such as SLDRAMs, that have programmable response times. A response time monitoring circuit in the form of a phase detector includes a plurality of flip-flops with the data inputs commonly connected to receive a response ready signal from a component, such as a memory circuit, in response to a command to perform a task. Each clock input of the flip-flop is connected to a clock signal at a different phase of a response period. The outputs of the flip-flops determine the phase at which the response ready signal was generated by the component.

Abstract: A method for testing n data pins of a parallel communication port. It includes the main steps of: (a) selecting an address to access a memory unit; (b) selecting a data pin to be tested and a testing data, wherein the testing data is a binary code consisting of (n—1) of first binary digits at data pins other than the data pin being selected and a second binary digit at the data pin being selected, the first binary digit being different from the second binary digit; (c) writing the testing data into the memory unit through all the data pins; (d) reading a stored data from the memory unit also through all the data pins; and (e) comparing the testing data with the stored data to diagnose the data pins, then storing the result into computer memory.