Abstract: Disclosed is a non-mounted storage test device based on FPGA, which comprises a processor unit for performing enumeration and configuration for device, creating a scenario for test and performing test; a device driver unit for managing storage device; a data engine unit for generating pattern data for test and performing test; a system memory interface unit for receiving data for test and storing test result; a monitoring unit for monitoring packet; a DMA driver/address translation unit for performing DMA operation and transmitting Memory Read Request to Root Complex; a message input/output unit for transmitting to the data engine unit and the device driver unit; a switch unit for constituting DUT unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data for test and record generated between tasks.

Abstract: Approaches for a packet format for error reporting in a content addressable memory (CAM) device are disclosed. The CAM device may comprise a CAM array that includes a plurality of rows, each row including a plurality of CAM cells coupled to a match line, and an error notification circuit capable of forming a packet that indicates whether the CAM device is experiencing an error condition. If an error condition was experienced by the CAM device, the response packet may also indicate the type(s) of error that was encountered. Advantageously, information about any error condition experienced by the CAM device may be quickly ascertained by a host device in which the CAM device is incorporated.

Abstract: A data storage device includes a memory and a controller coupled to the non-volatile memory. The controller is coupled to a communication interface that is configured to enable communication with a host device. The controller is configured to send a signal via a first connection of the communication interface and to send a corresponding clock signal via a second connection of the communication interface. The signal is compliant with a communication protocol that specifies that the first connection of the communication interface carries the signal while the second connection of the communication interface carries the clock signal. The first connection is testable to measure the signal to generate data indicating transitions of the signal. The data excludes measurements of the clock signal. The data is analyzable to detect an indication defined by the communication protocol and to determine an estimated bit sequence of the signal.

Abstract: A disk control apparatus includes a processor, and a memory coupled to the processor in which executes a process as follows. The process includes diagnosing whether or not a failure has occurred on each of a plurality of disk apparatuses, determining, when the failure has occurred, whether or not the failure is a pre-defined failure, and excluding from diagnosis targets, when the failure is the pre-defined failure, a disk apparatus group included in a RAID together with a failed disk apparatus that is determined to have the pre-defined failure in the plurality of disk apparatuses.

Abstract: According to one embodiment, a memory system includes a first memory, a second memory, and a control unit. The first memory includes a volatile first register retaining a first operation parameter. The control unit performs a first operation of retaining the first operation parameter in the second memory. Then, the control unit turns OFF the first memory while retaining the first operation parameter in the second memory when an operation mode is switched from a first mode to a power saving second mode. Then, the control unit performs a second operation of turning on the first memory, and transferring the first operation parameter retained in the second memory to the first register when the operation mode is switched from the second mode to the first mode.

Abstract: In a method for testing a storage system, each disk of a storage system is numbered, and a disk of a number is selected as a root node of a binary tree. A probability that the nodes of each level of the binary tree is completely added into the binary tree is computed according to a predefined algorithm, and the nodes of each level of the binary tree are added into the binary tree according to the computed probability. And each disk is tested when the disk is added into the binary tree as the node of the binary tree.

Abstract: A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to fetch an instruction from the processing module and determines whether the instruction is currently stored in the main memory. When the instruction is not currently stored in the main memory, the memory controller determines whether the instruction is stored in a distributed storage network (DSN) memory as one or more sets of encoded instruction slices; and, when it is, the memory controller addresses the DSN memory to retrieve the one or more sets of encoded instruction slices. When at least a threshold number of encoded instruction slices are retrieved for each of the one or more sets of encoded instruction slices, the one or more sets of encoded instruction slices are decoded using a dispersed storage error coding function to reconstruct the instruction, which is provided to the processing module.

Abstract: A method and system for testing a memory is provided in the present invention. The method includes the following steps. Each of at least one address bit to be tested of the memory is set to a fixed value. Current test data is written into memory unit(s) of the memory which the set address bit(s) correspond(s) to. Current read back data is read from the memory unit(s) which the set address bit(s) correspond(s) to. The current test data is compared with the current read back data. It is judged whether there is any signal integrity problem in unset address bit(s) of the memory according to the comparison result of the current test data and the current read back data, in order to determine fault address bit(s). The method and system for testing a memory provided by the present invention may determine fault address bit(s) of the memory simply and quickly.

Abstract: In a testing device, a method for implementing distributed pin mapping. The method includes receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges, implementing accesses to the pin map memories locally at each of the plurality of bridges, and using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.

Abstract: A method or apparatus detects a memory corruption of at least one portion of memory during run-time and corrects the memory corruption of the at least one portion of memory by replacing the at least one portion of memory with a backup of the at least one portion of memory. In this way, memory corruption can be corrected in a timely fashion while minimizing security risks.

Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

Abstract: A CPU changes the operating mode to a test mode in which the CPU does not terminate a program being executed even if an MMU outputs a CPU exception notification, outputs an address signal for causing the MMU to output a CPU exception notification to the MMU in the test mode, and detects whether or not a CPU exception notification is input after the address signal is output to the MMU. This allows inspection as to whether or not a fault that prevents detection of an illegal access has occurred in the MMU while executing another program.

Abstract: This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations.

Abstract: A method includes a DSN access token module retrieving one or more sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with the computing device and/or the DSN access token module decoding the one or more sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function. The method continues with the computing device and/or the DSN access token module generating a plurality of sets of data access requests in accordance with the DS error coding function. The method continues with the computing device sending the plurality of sets of data access requests to the DSN memory.

Abstract: A maintenance free storage container includes a plurality of storage servers, wherein the maintenance free storage container allows for multiple storage servers of the plurality of storage servers to be in a failure mode without replacement. The maintenance free storage container further includes a container controller operable to manage failure mode information of the plurality of storage servers, manage mapping of a plurality of virtual storage servers to at least some of the plurality of storage servers based on the failure mode information, communicate storage server access requests with a device external to the maintenance free storage container using addressing of the plurality of virtual storage servers, and communicate the storage server access requests within the maintenance free storage container using addressing of the plurality of storage servers.

Abstract: A computer booting method is provided for a computer system. The method comprises performing a power-on-self test. When the test result shows no error on the BIOS, a booting procedure is executed. When the test result shows the BIOS is damaged, whether the computer system stores a backup file of the BIOS is determined. When the computer system stores the backup file, the central processing unit reads the data of backup file and write it into a BIOS system memory and a reboot process is performed. When there is no backup file in the computer system, the computer system is connected to an internet server and downloads a BIOS backup file to the system main memory from the internet server. The central processing unit reads the BIOS backup file and write it into the BIOS system memory and a reboot process is formed.

Abstract: A method that determines the system impact of single event upset (SEU) and a single event upset (SEU) wrapper that controls a SEU controller is disclosed. The method injects faults into a component (e.g. FPGA, ASIC) of an operational system that is carrying live traffic and monitors the system's response to the faults to determine the impact of SEU on the system. The SEU wrapper sends the SEU controller a pattern scheme that includes information indicating when, where, how often, and/or how long to inject bursts of one or more faults into memory of the component of the system. A burst of faults contains faults that are consecutively injected into the array of memory blocks. After each fault in a burst is injected, one or more errors in one or more memory elements are detected and/or corrected. Information regarding the detection and/or the correction of an error is updated using registers that store counters. After injecting a burst of faults, the SEU controller waits for a predetermined amount of time.

Abstract: Determining port failover information is described. First information is determined by a first storage processor executing first code for performing port matching. The first information identifies a first set of port pairs. Each port pair includes a first port of the first or second storage processor and a second port of the first or second storage processor. Each port pair denotes the first port as protecting the second port. Upon failure or unavailability of the second port, the first port virtualizes the second port and requests directed to the second port are redirected to the first port. Similarly, second information is determined by the second storage processor executing second code for performing the port matching. Port failover processing is performed upon failure or unavailability of port(s) of the first storage processor and/or the second storage processor. Port failover processing uses the first information and/or the second information.

Abstract: A memory dump method includes performing information processing using a first partition including a first device board and a second device, detecting an error in the first device, after detecting the error, performing information processing using a second partition including a third device, after detecting the error, performing a memory dump on each of the first device and the second device to obtain dump data, and after the memory dump is performed, adding the second device to the second partition.

Abstract: A method begins by a processing module detecting a potential dispersed storage network (DSN) protocol issue that effects access of dispersed storage error encoded data within a DSN. The method continues with the processing module identifying a DSN entity based on the DSN protocol issue and generating a DSN protocol inquiry frame. The method continues with the processing module transmitting the DSN protocol inquiry frame to the DSN entity. The method continues with the processing module receiving a DSN protocol response frame from the DSN entity and resolving the DSN protocol issue based on the DSN protocol response frame.

Abstract: A method of sampling sensor data from a computing system is presented. The computing system includes a plurality of components and a sensor network for monitoring the computing system. The sensor network includes primary sensor nodes operable to obtain primary parameter data from a measurement of a primary parameter of the components, and secondary sensor nodes operable to obtain secondary parameter data from a measurement of secondary parameters of the components. The method includes: a) obtaining secondary parameter data from secondary sensor nodes relating to components; b) processing, in a computing device, the secondary parameter data; c) determining, based upon determined or pre-determined relationships between the secondary parameters and the primary parameter, a sample rate for the primary parameter data for the components; and d) obtaining primary parameter data from the primary sensor nodes relating to components at the determined sample rate.

Abstract: Embodiments are directed towards a controller that provides individual network accessibility to a storage drive. The controller may include a first connector operative to couple with a storage-drive connector, a second connector operative to couple with a backplane connector of a multi-storage-drive chassis, memory, and processor. The controller may convert communication received through the first connector into an Ethernet protocol for output through the second connector, and convert communication received through the second connector into a storage-drive protocol for output through the first connector. A physical shape of the controller may fit adjacent to the storage-drive connector and occupy less space than is bounded by peripheral edges of an end of a separate housing of a storage drive coupled to the storage-drive connector. The controller may manage power provided to the storage drive and may coordinate with other controllers to manage power-up sequences of multiple storage drives.

Abstract: A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

Abstract: A plug-in card storage device includes a plug-in card including a memory to store received input data and an error correction circuit to be equipped electrically connectable to the memory and to correct an error in the input data outputted from the memory; a device main body to have the plug-in card implemented therein; and a processor to determine whether or not to activate the error correction circuit, by calculating a reliability index value of the plug-in card based on an error rate of the memory provided in the plug-in card implemented in the device main body, so as to approximate the reliability index value to a reference value.

Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract: Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not.

Abstract: Embodiments of an invention for protecting information processing system secrets from debug attacks are disclosed. In one embodiment, a processor includes storage, a debug unit, and a test access port. The debug unit is to receive a policy from a debug aggregator. The policy is based on a value of a first fuse and has a production mode corresponding to a production value of the first fuse and a debug mode corresponding to a debug value of the fuse. The test access port is to provide access to the storage using a debug command in the debug mode and to prevent access to the storage using the debug command in the production mode.

Abstract: A data storage device comprises storage media and a controller. The storage media may comprise a plurality of media defects, at least some of the media defects being listed in a grown defect list and a primary defect list comprising a plurality of entries sorted in an order according to physical address locations. The controller may be configured to generate a push down list from the primary defect list and the grown defect list by populating the push down list with entries from the primary defect list such that the push down list entries maintain the order; translating each entry in the grown defect list to a physical address location; and inserting each translated physical address location with updated push down count into the push down list.

Abstract: The subject disclosure relates to analyzing memory allocations for one or more computer-implemented processes. In particular, in conjunction with employing tags for tracking memory allocation commands, currently allocated memory can be examined for various characteristics of inefficient memory use. For example, as memory is initially allocated, a predetermined bit pattern can be written to the newly allocated memory. Thus, detection of the predetermined bit pattern can be indicative of wasted memory use. Moreover, additional features can be provided to both analyze data and present views associated with that analysis relating to identification of memory fragmentation, over-allocation, sparse memory use, duplication of allocations, multiple module loads, and so forth.

Abstract: A tape drive for exchanging data with a tape cartridge, which has tape media and auxiliary memory that is not tape media, is operable, in response to a boot request from a computer apparatus that is bootable from a kind of initial program load device that is not a tape drive, to read boot data stored on the auxiliary memory and to output the boot data for booting the computer apparatus.

Abstract: The method includes receiving a command at a first storage system of a block storage cluster. The command is transmitted by the initiator system to the first storage system via a network and includes a request for data. The method further includes transferring the stored data from the first storage system to the initiator system via the network when data requested in the data request is stored by the first storage system. The method further includes transmitting a referral response from the first storage system to the initiator system when a portion of the data requested in the data request is not stored by the first storage system, but is stored by a second storage. system of the block storage cluster.

Abstract: A method begins by a dispersed storage (DS) processing module of a DS unit selecting a data slice for corruption analysis and requesting integrity information for the data slice from one or more other DS units of a dispersed storage network. When the one or more requested integrity information is received, the method continues with the DS processing module analyzing the one or more received integrity information and local integrity information of the data slice stored in the DS unit. When the analysis of the one or more received integrity information and the local integrity information of the data slice is unfavorable, the method continues with the DS processing module identifying the data slice as being corrupted.

Abstract: Methods, computer-readable media, and computer systems are provided for initiating storage of data on multiple storage devices and confirming storage of the data after the data has been stored on one but not necessarily all of the devices. A storage server receives, from a client, a request to store data. In response to the request, the storage server initiates, in parallel, storage of the data on multiple storage systems. The storage server detects that the data has been stored on any one of the storage systems, such as an auxiliary system, and, in response, indicates, to the client, that the data has been stored. The storage server may flush or discard data on the auxiliary storage system upon detecting that the data has been successfully stored on a target storage system, where the data persists.

Abstract: A storage system is provided with a memory region, a cache memory region, and a processor. The memory region stores the time relation information that indicates a time relationship of a data element that has been stored into the cache memory region and that is to be written to the logical region and a snapshot acquisition point of time to the primary volume. The processor judges whether or not the data element that has been stored into the cache memory region is a snapshot configuration element based on the time relation information for the data element that is to be written to a logical region of a write destination that conforms to the write request that specifies the primary volume and that has been stored into the cache memory region.

Abstract: A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.

Abstract: In accordance with embodiments of the present disclosure, a method may comprise identifying one or more portions of the memory having defects. The method may also include storing one or more addresses in the memory defect list, each of the one or more addresses associated with a portion of the one or more identified portions. The method may further include indicating to components of an information handling system that the one or more identified portions are unusable such that the other components are prevented from allocating and using the one or more identified portions.

Abstract: A system, method and computer program product for distributing task assignments on a computer network comprising a client grid having at least one server coupled to at least one client node and a plurality of client computers coupled to the client node through a plurality of monitoring agents. Each monitoring agent collects data regarding the resources a particular client computer makes available to the grid and transmits the data to the grid server when the client computer requests a grid task. The system generates a resource probability distribution based on the historical computing resource data and employs a scheduling algorithm to distribute grid tasks to the client computers using at least the probability distribution.

Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).

Abstract: Re-arranging data handling in a computer-implemented system that comprises a plurality of existing physical entities. At least one reliability rating is assigned to each of various existing physical entities of the computer-implemented system; and in response to change. Reverse predictive failure analysis uses the assigned reliability ratings to determine cumulative reliability rating(s) for at least one arrangement of the system. Data handling is re-arranged with respect to at least a portion of the existing computer-implemented system to provide a designated cumulative reliability rating.

Abstract: Subject matter disclosed herein relates to on-the-fly remapping a memory device by hardware-switching data paths to locations of the memory device.

Abstract: In a method for managing test results of an electronic device, the electronic device includes one or more expansion slots. The method selects a hard disk drive to insert into each expansion slot, executes a read-write test on each expansion slot, and saves test result(s) of the tests on each expansion slot into a file. Before managing the test results, the method sets a file name for each expansion slot for which test results is to be managed, and selects a test item from the read-write test. The method determines test results which expansion slots with are required to be managed and determines a test order of the expansion slots. After the test results are imported, the method amends a file name corresponding to each expansion slot according to the test order, and manages the test results of each expansion slot.

Abstract: A remote data memory access method for use in a computer system having a plurality of nodes, each node using a respective memory and remote data memory access between nodes being performed by transferring user data from the memory used by one node to the memory used by another node, the method comprising: maintaining memory correctness information of the user data at a subunit level; selecting subunits of user data for transfer in dependence upon memory correctness information of each subunit; and selectively transferring the subunits so selected. The method preferably involves transferring the memory correctness information of at least the selected subunits of user data, in addition to the selected subunits of user data. The memory correctness information may be compressed prior to transfer.

Abstract: A system and method for arbitrating exchange identifier assignments for I/O operations are disclosed. In an exemplary embodiment, the method comprises receiving, by a storage system, a data command from a host system. The data command is directed to a virtual device of the storage system, the virtual device comprising a plurality of physical devices of the storage system. A range of exchange identifier values are allocated to the data command. The range may include a predefined number of exchange identifiers, the predefined number determined prior to the receiving of the data command. A plurality of I/O operations corresponding to the data command are issued, where each of the plurality of I/O operations is directed to a physical device of the plurality of physical devices of the storage system. An exchange identifier within the range of exchange identifier values is associated with each of the plurality of I/O operations.

Abstract: An information processing apparatus includes a determination unit configured to determine whether incorrect updating processing in which information stored in a memory of the information processing apparatus is incorrectly updated has been executed in a first application program for receiving an instruction issued by a user and for controlling execution of processing corresponding to the instruction; a forcible termination unit configured to, when the determination unit determines that the incorrect updating processing has been executed, forcibly terminate the first application program; and a restart control unit configured to, when the determination unit determines that the incorrect updating processing has been executed, after the forcible termination unit terminates the first application program, notify the user of the occurrence of the incorrect updating.

Abstract: A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes a segment length field describing the length of memory reserved for the data record and the data record contains at least one data instance object. Each of the data instance objects has a data instance header and data field. The header includes a data instance state field and a data instance length field. The data instance length field contains data representing the length of the data instance data field allowing for variable length “in place” updating. The data instance state field contains data representing an object state of the instance data. Only one of the data instance objects of the data record of the single segment data object has a valid object state. The state field facilitates a power loss recovery process.

Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

Abstract: A method, system and computer program product for generating device fingerprints and authenticating devices uses initial states of internal storage cells after each of a number multiple power cycles for each of a number of device temperatures to generate a device fingerprint. The device fingerprint may include pairs of expected values for each of the internal storage cells and a corresponding probability that the storage cell will assume the expected value. Storage cells that have expected values varying over the multiple temperatures may be excluded from the fingerprint. A device is authenticated by a similarity algorithm that uses a match of the expected values from a known fingerprint with power-up values from an unknown device, weighting the comparisons by the probability for each cell to compute a similarity measure.

Abstract: A method for processing data includes storing a type information of a configuration element of a first data process system in association with an identification information of the configuration element in a configuration information storage part, determining the type information corresponding to a message output from the first data process system, the message including the identification information, comparing a first message group including a plurality of first messages and a second message group including a plurality of second messages, the plural second messages being stored in association with the type information of a second data process system in a message group storage part, determining whether the plural first messages match the plural second messages, and determining whether the type information of the plural first messages match the type information of the plural second messages when the plural first messages do not match the plural second messages.

Abstract: Memory leak detection can be automated by assigning and recording an increasing sequence number to each memory allocation requested by an action. Call stacks associated with the action are also recorded. Several repetitions of the action can be executed. Allocations that occur in each action and that have similar or matching callstacks are defined as leaks. Allocations that do not have matches can be ignored.