Memory Or Storage Device Component Fault Patents (Class 714/42)
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Patent number: 8745448Abstract: A storage system comprises a storage device for storing data, a control apparatus which controls the storage device and comprises multiple communication ports, and a switch apparatus which expands the number of storage device couplings and comprises multiple communication ports. Respective multiple communication ports of the control apparatus are coupled to respective multiple communication ports of the switch apparatus, and the switch apparatus is coupled to the storage device. The control apparatus configures at least one communication port of the multiple communication ports of the control apparatus, to a dedicated communication port for outputting only a prescribed command issued when a failure is detected.Type: GrantFiled: June 6, 2012Date of Patent: June 3, 2014Assignee: Hitachi, Ltd.Inventors: Tsutomu Koga, Koji Washiya
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Publication number: 20140149786Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.Type: ApplicationFiled: February 3, 2014Publication date: May 29, 2014Applicant: Micron Technology, Inc.Inventor: Chang Wan Ha
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Patent number: 8738996Abstract: A system includes a flash memory, an encoder, a first interface, a decoder and a controller. The encoder is configured to (i) receive data, and (ii) encode the data based on an error correction code. The first interface is configured to (i) write the encoded data to a memory cells in the flash memory, and (ii) read the encoded data back from the memory cells. The decoder is configured to (i) decode the encoded data read back from the memory cells, and (ii) based on the decoded data, determine a number of decoding errors for the plurality of memory cells. The controller is configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the memory cells. The first threshold is less than a maximum number of errors correctable by the error correction code for the memory cells.Type: GrantFiled: October 1, 2013Date of Patent: May 27, 2014Assignee: Marvell International Ltd.Inventors: Chen Kuo Huang, Sui-Hung Fred Au, Xueshi Yang, Lau Nguyen
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Patent number: 8737148Abstract: Systems and methods are provided for selectively retiring blocks based on refresh events of those blocks. In addition to refresh events, other criteria may be applied in making a decision whether to retire a block. By applying the criteria, the system is able to selectively retire blocks that may otherwise continue to be refreshed.Type: GrantFiled: March 15, 2013Date of Patent: May 27, 2014Assignee: Apple Inc.Inventors: Matthew J. Byom, Daniel J. Post, Vadim Khmelnitsky
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Patent number: 8732533Abstract: Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof. In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.Type: GrantFiled: September 21, 2011Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventor: David R. Resnick
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Patent number: 8732532Abstract: An information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, cause the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.Type: GrantFiled: September 7, 2011Date of Patent: May 20, 2014Assignee: Fujitsu LimitedInventor: Masanori Higeta
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Patent number: 8732523Abstract: A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack.Type: GrantFiled: October 24, 2011Date of Patent: May 20, 2014Assignee: ARM LimitedInventors: Emre Özer, Yiannakis Sazeides, Daniel Kershaw, Stuart David Biles
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Patent number: 8726120Abstract: A method begins with a processing module receiving an access request for the data object. The method continues by ascertaining that the data object is divided into a plurality of data segments and that plurality of data segments are dispersed storage error encoded to produce a plurality of sets of encoded data slices. The method continues by ascertaining batching of the plurality of sets of encoded data slices, wherein the plurality of sets of encoded data slices are arranged into a set of batched encoded data slices. The method continues by outputting a set of access requests for the set of batched encoded data slices to storage units of the DSN.Type: GrantFiled: October 4, 2013Date of Patent: May 13, 2014Assignee: Cleversafe, Inc.Inventors: Andrew Baptist, Ilya Volvovski, Wesley Leggette, Greg Dhuse, Jason K. Resch
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Patent number: 8726127Abstract: A method begins by a computing device determining that dispersed storage network (DSN) memory is to be accessed regarding data. The method continues when the computing device is paired with a DSN access token module with the DSN access token module retrieving a plurality of sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with at least one of the computing device and the DSN access token module decoding the plurality of sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function and executing, by one or more of the computing device and the DSN access token module, the DS error coding function to access the DSN memory regarding the data.Type: GrantFiled: January 10, 2012Date of Patent: May 13, 2014Assignee: Cleversafe, Inc.Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette
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Patent number: 8719618Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.Type: GrantFiled: June 13, 2012Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh
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Patent number: 8719642Abstract: A method for saving crash dump files of a virtual machine (VM) on a designated disk is disclosed. The method includes associating, by a hypervisor that virtualizes a plurality of virtual machines (VMs), each VM of the plurality of VMs with a crash dump disk that is solely dedicated to the VM, wherein each crash dump disk is located separate from its associated VM. The method further includes configuring, by the hypervisor, an OS of each VM with a crash file path to the crash dump disk associated with the VM, and configuring, by the hypervisor, each VM of the plurality of VMs to generate crash dump files for the VM upon a crash event of the VM and store, via the crash file path, the generated crash dump files to the crash dump disk associated with the VM.Type: GrantFiled: January 11, 2013Date of Patent: May 6, 2014Assignee: Red Hat Israel, Ltd.Inventor: Dor Laor
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Patent number: 8713374Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.Type: GrantFiled: September 13, 2012Date of Patent: April 29, 2014Assignee: MOSAID Technologies IncorporatedInventor: Greg A. Blodgett
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Patent number: 8707134Abstract: According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller configured to control data input and output to and from nonvolatile memories for channels. The encoding module configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories. The data controller configure to manage the encoded data in units of logical blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to planes of the same channel in each logical block.Type: GrantFiled: December 7, 2011Date of Patent: April 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kyosuke Takahashi, Motohiro Matsuyama
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Patent number: 8707101Abstract: Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a “rollover mode”. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite.Type: GrantFiled: November 9, 2010Date of Patent: April 22, 2014Assignee: International Business Machines CorporationInventors: Eli Almog, Oz Dov Hershkovitz, Christopher Krygowski
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Patent number: 8707105Abstract: A method begins by a processing module determining a memory usability indication for a set of memory devices, wherein the set of memory devices stores data as first dispersed storage error coded data using first dispersed storage error coding parameters. The method continues with the processing module comparing the memory usability indication to a memory usability level threshold. The method continues with the processing module adding one or more memory devices to the set of memory devices to produce an updated set of memory devices when the memory usability indication compares unfavorably to the memory usability level threshold. The method continues with the processing module storing the data as second dispersed storage error coded data using second dispersed storage error coding parameters in the updated set of memory devices.Type: GrantFiled: October 4, 2011Date of Patent: April 22, 2014Assignee: Cleversafe, Inc.Inventors: Gary W. Grube, Timothy W. Markison
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Publication number: 20140108869Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Applicant: Infineon Technologies AGInventors: Simon Brewerton, Simon Cottam, Frank Hellwig
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Patent number: 8700950Abstract: Systems and methods are disclosed for recovering from a data access error encountered in data stripes implemented in a data redundancy scheme (e.g., RAID) in a solid state storage device. In one embodiment, the storage device holds parity data in a temporary, volatile memory such as a RAM and writes the parity data to the non-volatile memory when a full stripe's worth of new write data has been written to the non-volatile memory. In one embodiment, upon detecting that a data access error has occurred in a partially written stripe, the storage device initiates a write of the parity data for the partially written stripe to the non-volatile memory and executes a RAID recovery procedure using the newly written parity data to attempt to recover from the detected error. This approach allows for a recovery from the data access error without waiting for the full stripe to be written.Type: GrantFiled: February 11, 2011Date of Patent: April 15, 2014Assignee: Western Digital Technologies, Inc.Inventor: Mei-Man L. Syu
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Publication number: 20140101490Abstract: The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.Type: ApplicationFiled: October 21, 2013Publication date: April 10, 2014Applicant: Micron Technology, Inc.Inventors: Terry M. Cronin, Joseph M. Jeddeloh
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Patent number: 8694822Abstract: In general, embodiments of the present invention provide a DR solution for a networked computing environment such as a cloud computing environment. Specifically, a customer or the like can select a disaster recovery provider from a pool (at least one) of disaster recovery providers using a customer interface to a DR portal. Similarly, using the interface and DR portal, the customer can then submit a request for DR to be performed for a set (at least one) of applications. The customer will then also submit (via the interface and DR portal) DR information. This information can include, among other things, a set of application images, a set of application files, a set of recovery requirements, a designation of one or more specific (e.g., application) components for which DR is desired, dump file(s), database file(s), etc. Using the DR information, the DR provider will then generate and conduct a set of DR tests and provide the results to the customer via the DR portal and interface.Type: GrantFiled: November 9, 2010Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventor: Rajesh Radhakrishnan
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Patent number: 8694825Abstract: A mechanism is provided for protecting storage fabrics from an errant device causing a single point of failure. The mechanism identities a source of the out-of-context traffic, isolates the TAG to prevent further catastrophe, and ensures that device isolation control operations are processed timely allowing device isolation and removing the source of the issue. Should device isolation not solve the issue, the mechanism allows the host to use a binary search method to isolate the device that may be hiding its true identity and sourcing possibly malicious traffic.Type: GrantFiled: July 20, 2011Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventor: Paul N. Cashman
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Patent number: 8694841Abstract: A method to enable defect margining of a disk drive may comprise executing a data access command on a target sector on the disk drive. Upon encountering a data access error at the target sector, an address of the target sector may be added to an error list. The address of the target sector in the error list may then be converted to a physical location on the disk drive. A thermal asperity scan may be performed at and around the physical location and, upon detecting a thermal asperity, and at least sectors around the detected thermal asperity may be margined, and the data stored within the margined sectors may be relocated. Instead of sectors, entire tracks may be margined and the data stored therein relocated to a spare or reserve location, one track at a time.Type: GrantFiled: June 20, 2012Date of Patent: April 8, 2014Assignee: Western Digital Technologies, Inc.Inventors: Heon Ho Chung, Chun Sei Tsai, Carl E. Barlow, Kenneth J. Smith
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Patent number: 8689091Abstract: In a system, a data receiving device comprises a timing signal generation unit that generates a timing signal used for receiving the divided transmission data in each of the transmission paths, a data receiving unit that receives the divided transmission data transmitted by the data transmitting device for each of the transmission paths by using the timing signal generated by the timing signal generation unit, and an error detection unit that extracts the error detection information from the divided transmission data received for each of the transmission paths by the data receiving unit and detects an error of transmission data included in the divided transmission data by using the extracted error detection information.Type: GrantFiled: January 4, 2012Date of Patent: April 1, 2014Assignee: Fujitsu LimitedInventor: Kenji Uchida
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Publication number: 20140089740Abstract: A method for use in a computerized storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode.Type: ApplicationFiled: November 26, 2013Publication date: March 27, 2014Applicant: International Business Machines CorporationInventors: Paul N. Cashman, Timothy F. McCarthy, Roderick G. Moore, Jonathan L. Settle, Jonathan W. Short
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Publication number: 20140089739Abstract: A serial advanced technology attachment dual in-line memory module device includes a capacitor to be tested, a control chip, a display device, a testing chip, and a selecting chip. Voltage pins of the testing chip and the selecting chip are connected to a power source. A testing pin of the testing chip is connected to the capacitor. A first input output (I/O) pin of the selecting chip is connected to a first I/O pin of the testing chip. A second I/O pin of the selecting chip is connected to a second I/O pin of the testing chip. A third I/O pin of the selecting chip is connected to an input pin of the control chip. A fourth I/O pin of the selecting chip is connected to an output pin of the control chip. A fifth I/O pin of the selecting chip is connected to the display device.Type: ApplicationFiled: October 30, 2012Publication date: March 27, 2014Inventors: XIAO-GANG YIN, GUO-YI CHEN
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Patent number: 8683270Abstract: Subject matter disclosed herein relates to a memory device and a method of operating same.Type: GrantFiled: April 29, 2010Date of Patent: March 25, 2014Assignee: Micron Technology, Inc.Inventors: Chris Bueb, Poorna Kale
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Patent number: 8683260Abstract: A method is used in managing ownership of logical volumes. A path to a logical volume is determined, where upper-layer software selects the path to the logical volume. Based on the selection of the path, ownership of the logical volume is assigned. Lower-layer software assigns ownership of the logical volume based on information received from the upper-layer software.Type: GrantFiled: December 29, 2010Date of Patent: March 25, 2014Assignee: EMC CorporationInventors: Qi Zhang, Qing Liu, Peter Tolvanen, Brahmadev Anand
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Patent number: 8667323Abstract: Processing for file system volume error detection and processing for resultant error correction are separated to support system availability and user satisfaction. File system volumes for storing data structures are proactively scanned while the volumes remain online to search for errors or corruptions thereon. Found errors are scheduled to be corrected, i.e., spot corrected, dependent on the severity of the identified errors, error correction scheduling and/or at the determination of a file system administrator and/or user, to assist in maintaining minimal user and file system impact. When spot correction is initialized, one file system volume at a time is taken offline for correction. Spot correction verifies prior logged corruptions for the offline volume, and if independently verified, attempts to correct the prior noted corruptions. Volumes are retained offline only for the time necessary to verify and attempt to correct prior noted volume corruptions.Type: GrantFiled: December 17, 2010Date of Patent: March 4, 2014Assignee: Microsoft CorporationInventors: Sarosh C. Havewala, Neal R. Christiansen, John D. Slingwine, Daniel Chan, Craig A. Barkhouse
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Patent number: 8667338Abstract: A system and method for a software override capability for enforcing a predetermined state for an otherwise hardware-programmable device. Software that may think it knows what it is doing may try to control a hardware device, but may not know about a hardware issue, such as another feature or defect requiring that the device stay in a certain state. The technique programmatically maintains a persistent hardware state independent of any other control software. To other software, the software layer of the invention is indistinguishable and inseparable from hardware. Nothing can slip in between. Any insertion attempt will be detected and disallowed. Features of the processor or system chips actually weld the software to the hardware, which feature disallows any software intervention between the welded software layer and the hardware.Type: GrantFiled: February 13, 2012Date of Patent: March 4, 2014Assignee: AFTG-TG, LLCInventor: Phillip M. Adams
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Patent number: 8667336Abstract: A method, apparatus, and system are disclosed. In one embodiment, the method determines whether one or more manageability conditions are present in a computer system, and then invokes an out-of-service manageability remediation environment stored within a portion of a flash device in the computer system when one or more manageability conditions are present.Type: GrantFiled: June 14, 2007Date of Patent: March 4, 2014Assignee: Intel CorporationInventors: Selim Aissi, Hani Elgebaly, Venkat Gokulrangan, Ayeshwarya B. Mahajan, Jasmeet Chhabra
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Patent number: 8667337Abstract: Deterioration of performance due to diagnosis processing performed when a failure occurs is prevented. A storage apparatus 10 includes a controller 11A and a plurality of expanders 112A, 121A coupled to the controller 11A to form a first system, and includes a controller 11B and a plurality of expanders 112B, 121B coupled to the controller 11B to form a second system. The controller 11A accesses the storage drive 171 through the expanders 112A, 121A, and the second controller 11B accesses the storage drive through the expanders 112B, 121B. In the storage apparatus 10, the controller 11A stores a maximum number (concurrently-executable maximum number) of communication ports 80 that are concurrently diagnosable in the first system, and repeatedly executes a process of selecting the communication ports 80 not exceeding the concurrently-executable maximum number and a process of causing the expanders 112A, 121A to diagnose the selected communication ports 80.Type: GrantFiled: April 12, 2011Date of Patent: March 4, 2014Assignee: Hitachi, Ltd.Inventors: Takashi Itoyama, Ikuya Yagisawa, Yoshifumi Mimata
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Patent number: 8661288Abstract: Systems and methods are provided for performing diagnostics on a removable media drive. An example system includes a monitoring unit configured to collect information about a media access to the media drive and a media access to a removable media contained in the media drive. The example system also includes a storage unit having a threshold table with at least one threshold value for the media access to the media drive. A processing unit is configured to compare the collected information of the monitoring unit to the at least one threshold value contained in the threshold table. The processing unit is also configured to determine diagnostic data relating to the removable media drive in accordance with the comparison.Type: GrantFiled: August 5, 2011Date of Patent: February 25, 2014Assignee: Harman Becker Automotive Systems GmbHInventors: Gerrit Fuchs, Krasnodar Jandrijevic, Juan Medrano
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Patent number: 8661294Abstract: A program verification circuit comprises a failed state counting unit and a failed bit counting unit. The failed state counting unit counts failed program states among a plurality of program states, and generates a first program mode signal indicating whether counting of failed bits is required. The failed bit counting unit selectively counts failed bits in response to the first program mode signal, and generates a second program mode signal indicating whether a program operation is completed.Type: GrantFiled: December 22, 2010Date of Patent: February 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Sang Lee, Oh-Suk Kwon
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Patent number: 8656227Abstract: An on-line client service method for a storage apparatus includes establishing a link between a client host and the storage apparatus for detecting the current status of the storage apparatus, the client host generating a diagnostic result of the storage apparatus, the client host transmitting the diagnostic result to a far-end server, the far-end server determining whether the storage apparatus functions abnormally according to the diagnostic result. If the storage apparatus functions abnormally, the client host reloads a firmware provided by the far-end server to the storage apparatus, and determines whether the storage apparatus functions abnormally after the storage apparatus is reloaded with the firmware.Type: GrantFiled: July 8, 2011Date of Patent: February 18, 2014Assignee: Transcend Information, Inc.Inventor: Ren-Wei Chen
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Patent number: 8656228Abstract: A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.Type: GrantFiled: June 23, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Mark A. Check, David F. Craddock, Thomas A. Gregg, Pak-kin Mak, Gary E. Strait
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Patent number: 8650437Abstract: A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.Type: GrantFiled: June 29, 2010Date of Patent: February 11, 2014Assignee: International Business Machines CorporationInventors: Richard E. Fry, Marc A. Gollub, Luis A. Lastras-Montano, Eric E. Retter, Kenneth L. Wright
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Patent number: 8645796Abstract: Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.Type: GrantFiled: June 24, 2010Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Michael Fee, Edward T. Gerchman, Arthur J. O'Neill, Jr.
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Patent number: 8645758Abstract: Embodiments of the invention relate to page faulting of memory operations in a subject code block. An aspect of the invention concerns an apparatus comprising a component for identifying a first object node having a first dependency path and second object node having a second dependency path, and a component for calculating a numerical difference between a first addressing value and a second addressing value, where the first and second addressing values are respectively associated with the first and second dependency paths. The apparatus may include a dependency generator for ordering a subject order list of the subject code block in an object dependency non-page-faulting order when the numerical difference is equal to or less than an assigned memory page size.Type: GrantFiled: February 28, 2011Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventor: Paul Michael Peter Brian Ronald Walker
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Patent number: 8640116Abstract: A loader module for loading program code into a memory is described, whereby the memory may be partially defective, with non-defective parts of the memory being indicated by diagnostic information. The loader module is adapted for loading program code, in accordance with the diagnostic information, into non-defective parts of the memory, and for relinking the program code in accordance with the memory locations it has been loaded to. Furthermore, a method for loading program code into a memory is described. The method comprises the following steps which may be carried out in arbitrary order: loading program code, in accordance with diagnostic information, into non-defective parts of the memory, and relinking the program code in accordance with the memory locations it has been loaded to.Type: GrantFiled: July 22, 2004Date of Patent: January 28, 2014Assignee: Broadcom CorporationInventor: John Redford
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Patent number: 8631281Abstract: Systems, methods and apparatus for archive verification including the verification of media in a library, are disclosed. More specifically, a method of archive verification may include performing an initial verification on a set of media to obtain an initial result for each of the media. Based on the results of the initial verification a subsequent set of media may be selected for subsequent verification utilizing a set of rules. A subsequent verification may then be performed on each of the subsequent set of media. Based on the results of the subsequent verification it can then be attempted to determine if any of the media require still require subsequent verification using the set of rules. This iterative process may continue until no media need any subsequent verification.Type: GrantFiled: August 23, 2010Date of Patent: January 14, 2014Assignee: KIP CR P1 LPInventors: Jeffrey Ricks Stripling, Robert C. Sims
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Patent number: 8627148Abstract: The present application provides a method, an apparatus and a system for memory dump processing. The method comprises: invoking a first set of processing units to process a first stage of memory dump processing for each of memory blocks; invoking each set of processing units other than the first set of processing units to process a subsequent processing stage after completing the first stage respectively, to write the memory blocks into a storage device. The technical solutions provided in the present application enable processing each stage for each of the memory blocks in a pipeline manner, avoid instantaneous peak flow of disk I/O transmission and improve memory dump performance.Type: GrantFiled: December 29, 2011Date of Patent: January 7, 2014Assignee: Huawei Technologies Co., Ltd.Inventors: Jun Li, Chao Zhang
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Publication number: 20140006873Abstract: There is provided a system that includes a first apparatus and a second apparatus configured to perform communication therebetween using a signal line, wherein the first apparatus includes a holding section configured to hold a signal level of a signal outputted from the second apparatus using the signal line, and the second apparatus includes, a detection section configured to detect a failure in which a signal level does not change from a certain signal level when the detection section detects that the signal level is not correspondent with a predetermined level, the signal level being held in the holding section after a signal of the predetermined level is inputted to the signal line by the second apparatus.Type: ApplicationFiled: June 27, 2013Publication date: January 2, 2014Applicant: FUJITSU LIMITEDInventor: Takashi Kidamura
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Patent number: 8621270Abstract: A redundant array of independent nodes are networked together. Each node executes an instance of an application that provides object-based storage. The nodes are grouped into a plurality of systems each having multiple nodes. An object recovery method comprises: receiving, by a first system of the plurality of systems from a client application, a read request for an object, the object having been replicated to/from at least one second system among the plurality of systems; if the object of the read request is available in the first system, returning by the first system the object of the read request to the client application; and if the object of the read request is not available in the first system, performing a read from replica process by the first system to access a replica of the object from a second system among the plurality of systems and using the replica of the object to return the object of the read request to the client application.Type: GrantFiled: September 24, 2010Date of Patent: December 31, 2013Assignee: Hitachi Data Systems CorporationInventors: Benjamin Isherwood, Donald P. Pannese, Richard Rogers, Vitaly Zolutusky
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Patent number: 8621276Abstract: Perceived corruptions encountered on file system volumes, and which cannot be initially remedied online, are processed to verify whether they are true, existing volume data structure corruptions or, alternatively, false positives. Upon the verification of one or more of a volume's corruptions, error scanning is performed to check for, and attempt to remedy online, all the existing corruptions on the volume. Subsequent to error scanning processing, if one or more verified corruptions continue to exist on a file system volume, at file system boot up time spot corruption correction is performed to attempt to remedy the existing, verified corruptions on the volume. Spot corruption correction is performed to attempt to correct verified data structure corruptions on a volume of the file system while the volume is maintained offline for the time necessary to attempt to correct its prior identified corruptions.Type: GrantFiled: December 17, 2010Date of Patent: December 31, 2013Assignee: Microsoft CorporationInventors: Sarosh C. Havewala, Neal R. Christiansen, John D. Slingwine, Daniel Chan, Craig A. Barkhouse, Lane Haury, Kiran Kumar G. Bangalore, Thiago Sigrist
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Publication number: 20130346805Abstract: A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.Type: ApplicationFiled: June 21, 2012Publication date: December 26, 2013Inventors: Steven T. Sprouse, Alexandra Bauche, Yichao Huang, Jian Chen, Jianmin Huang, Dana Lee
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Patent number: 8612804Abstract: Embodiments of the invention are directed to systems and methods for improving wear leveling performance in solid-state memory. The embodiments described herein make more consistent the number of wear leveling operations that need to be performed, so that sudden spikes in the number wear leveling operations may be reduced in solid-state memory. In one embodiment, a rule-based wear leveling approach is used to spread out the execution of wear leveling operations that otherwise would have been triggered in clusters. Under the rule-based approach, wear leveling is periodically triggered by a specified interval of erase counts associated with a unit of solid-state memory such as a group of blocks, rather than by a threshold based on erase counts.Type: GrantFiled: September 30, 2010Date of Patent: December 17, 2013Assignee: Western Digital Technologies, Inc.Inventors: Ho-Fan Kang, Cliff Pajaro
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Patent number: 8606767Abstract: A method for invalidating metadata associated with a target count-key-data (CKD) volume is disclosed. The method initially receives a command for a target CKD volume. The command is either an “establish” command for establishing a point-in-time copy relationship, or a “withdraw” command for withdrawing a point-in-time copy relationship. The method determines a track range, spanning a number of data tracks in the CKD volume, associated with the command. Each data track in the track range is associated with a metadata track. For each metadata track whose associated data tracks are fully contained in the track range, the method performs a first procedure. For each metadata track whose associated data tracks are not fully contained in the track range, the method performs a second procedure different from the first procedure. A corresponding apparatus and computer program product are also disclosed.Type: GrantFiled: February 8, 2012Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Theresa Mary Brown, Nedlaya Yazzie Francisco, Beth Ann Peterson, Suguang Li
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Patent number: 8607100Abstract: A motherboard testing device applied to a motherboard which includes two memory channels, and a CPU. Each of the two memory channels includes two memory slots. The motherboard testing device includes four memory modules received in the four memory slots, a switching chip, a microcontroller, and a testing module. The switching chip includes four input pins electrically connected to the four memory modules, four output pins electrically connected to the CPU, and a controlling pin electrically connected to the microcontroller. The microcontroller forms a plurality of combination modes of the memory slots by electrically combining the four memory slots, and controls the switching chip to electrically connect memory slots of each combination mode to the CPU. The testing module tests whether the CPU controls the memory modules received in the memory slots of each combination mode to work in proper working modes.Type: GrantFiled: December 30, 2011Date of Patent: December 10, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Yi-Tsang Hsieh, Yung-Po Chang
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Patent number: 8607099Abstract: Data structure errors, or corruptions, identified during, e.g., normal computing device system processing, file system processing or user access processing, are verified prior to the file system identifying the error for offline correction or notifying the user or system administrator a data structure error exists. Identified data structure corruptions are verified while the file system volumes are maintained online and otherwise accessible to other processing tasks and user access. Verified data structure corruptions are logged for further corrective processing. Data structure corruptions that cannot be verified, i.e., false positives, are not further processed and are not identified to file system administrators or users as corruptions, freeing the file system to concentrate on normal processing and true, verifiable errors.Type: GrantFiled: December 17, 2010Date of Patent: December 10, 2013Assignee: Microsoft CorporationInventors: Sarosh C. Havewala, Neal R. Christiansen, John D. Slingwine, Craig A. Barkhouse, Daniel Chan
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Patent number: 8601323Abstract: Systems and methods for advanced management of runtime errors are described herein. Based on a preference, a runtime error manager selects one or more error dumps generated in a computer system landscape. The runtime error manager filters one or more data portions from the selected error dumps. The filtered data portions are supplemented with additional information collected from the nodes of the computer system landscape, or received from external systems. The data portions and the supplemental data are used to assign users responsible to resolve one or more of the logged runtime errors. The data portions and the supplemental information are used to create and send notifications to the responsible users or to instantiate and manage workflows in behalf to the responsible users.Type: GrantFiled: December 13, 2010Date of Patent: December 3, 2013Assignee: SAP AGInventor: Efstratios Tsantilis
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Patent number: 8595566Abstract: Data storage services are provided for clients for backup of data objects from the clients. A data object is sent to a first location in a first storage device. A determination is made if the data object was successfully stored at the first location, and if so, meta data corresponding with the data object is stored, wherein the meta data includes first path information on a first data path of the data object to the first location. The data object is migrated from the first location to a second location in a second storage device. A determination is made if the data object was successfully stored at the second location, and if so, second path information on a second data path of the data object is added to the second location to the meta data corresponding with the data object, to update the meta data.Type: GrantFiled: September 10, 2012Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Colin S. Dawson, Glen Hattrup, Howard N. Martin, David M. Morton