Memory Or Storage Device Component Fault Patents (Class 714/42)
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Patent number: 8595573Abstract: A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.Type: GrantFiled: February 26, 2012Date of Patent: November 26, 2013Assignee: Apple Inc.Inventors: Ofir Shalvi, Naftali Sommer, Oren Golov
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Patent number: 8589841Abstract: A method, apparatus and computer program product for automatic parity check identification. The method comprising: automatically identifying a parity signal in a circuit design, wherein the parity signal is defined as a parity function of a set of support signals, wherein the automatic identification comprises: obtaining a candidate parity signal and a corresponding set of candidate support signals; and verifying that a bit flip in exactly one of any of the corresponding candidate set of support signals induces a bit flip on a value of the candidate parity signal; wherein said method further comprises reporting the automatically identified parity signal.Type: GrantFiled: April 5, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Eli Arbel, Sergey Novimov, Karen Yorav
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Patent number: 8589737Abstract: A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.Type: GrantFiled: June 20, 2008Date of Patent: November 19, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Michael Rohleder, Gary Hay, Stephan Mueller, Manfred Thanner
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Patent number: 8589735Abstract: A mechanism for verifying order of entities being processed by a device under test (DUT) is provided. The mechanism includes arranging the entities into a temporal order, and encoding the entities to maintain the temporal order of the entities and produce encoded entities with each being a random value. The encoded entities each have a one-to-one mapping to their corresponding one of the entities in the temporal order. The encoded entities are input into the DUT to verify its output, and responsive to detecting an error in the output corresponding to one encoded entity, the one encoded entity is decoded into a current decoded error entity. It is determined which is lower in the temporal order between the current decoded error entity and a previous decoded error entity. Responsive to the current decoded error entity being lower than the previous decoded error entity, the current decoded error entity is stored.Type: GrantFiled: May 16, 2011Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Clinton E. Bubb, Chaitanya Kancherla, Roopesh A. Matayambath, Ralf Winkelmann
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Patent number: 8583972Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.Type: GrantFiled: June 1, 2012Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Patent number: 8583880Abstract: A method for secure data reading and a data handling system is provided. The method protects the data reading from fault attacks by repeating read request in an interleaved manner, in particular the method comprises the steps of (M200) dispatching a first read request; (M400) dispatching a second read request; (M600) dispatching a further first read request; and (M1000-a) producing an anomaly signal if a first result produced by the memory in response to the first read request does not agree with a further first result produced by the memory in response to the further first read request.Type: GrantFiled: April 29, 2009Date of Patent: November 12, 2013Assignee: NXP B.V.Inventors: Mathias Wagner, Ralf Malzahn
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Patent number: 8582954Abstract: A media player may include a media reader to read media content from a recording medium inserted into the media reader. The media player may also include a media analysis component to identify one or more valid portions of the recording medium containing media content and one or more invalid portions of the recording medium without media content. In one embodiment, the media player includes an archival component to store the media content from the one or more valid portions in a storage medium and a playback component to play back the one or more valid portions of the media content from the storage medium concurrently with the identification of the one or more valid portions by the media analysis component and the storage of the media content by the archival component.Type: GrantFiled: December 10, 2008Date of Patent: November 12, 2013Assignee: Intel CorporationInventors: David J. Watson, James Bielman, Phillip L. Barrett, Nicole A. Hamilton
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Patent number: 8583966Abstract: Methods and structure for diagnosing errors in the initialization of DDR memory “on board” a storage controller or a storage expander are presented herein. The features and aspects discussed herein allow for the debugging of the DDR memory initialization. A memory diagnostic system is operable on a storage controller and includes an initialization module in communication with a firmware module of the storage controller. The memory diagnostic system is adapted to initialize a Double Date Rate (DDR) memory of the storage controller. The memory diagnostic system also includes an application programming interface adapted to retrieve initialization information from the initialization module and transfer the initialization information to a debug system via a direct communication link between the application programming interface and the debug system to diagnose the initialization of the DDR memory and to debug the initialization module based on the initialization information.Type: GrantFiled: April 29, 2011Date of Patent: November 12, 2013Assignee: LSI CorporationInventor: Sagar G. Gadsing
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Patent number: 8572440Abstract: A system and method of identifying a memory includes detecting defects in regions of the memory, comparing the detected defects with defects contained in a previously-created defect map associated with the memory and stored in another memory of a device accessing the memory, confirming the identity of the memory where a result of the comparison indicates the detected defects match defects contained in the previously-created defect map; and denying the identity of the memory where the result of the comparison indicates the detected defects do not match the defects contained in the previously-created defect map.Type: GrantFiled: November 15, 2010Date of Patent: October 29, 2013Assignee: e.Digital CorporationInventor: Patrick Nunally
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Patent number: 8566637Abstract: A method is used in analyzing drive errors in data storage systems. An error tag and total good I/O count are maintained for a drive. For each failed I/O, the following is performed. An error weight per error is retrieved. A new error tag is calculated from the error weight, a previous error tag, and the total good I/O count. An error ratio is calculated from the new error tag and a total I/O count. The error ratio is compared with thresholds. If one or more of the thresholds has been crossed, action is taken on the drive. The error tag is reduced as good I/O is produced.Type: GrantFiled: December 23, 2010Date of Patent: October 22, 2013Assignee: EMC CorporationInventors: Peter Puhov, Shay Harel, Huzefa Hakimi, Lili Chen, Zhiqi Liu
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Patent number: 8565053Abstract: A method of operating a disk drive comprises scanning each Logical Block Address (LBA) of the disk drive to detect a read error or reading the LBA from a media defect list. The LBA may then be converted to a corresponding physical location on the media and a scan of the corresponding physical location and of nearby physical locations that are within a proximity threshold of the corresponding physical locations may be performed to find media defects. Based thereon, it may then be determined whether a media scratch is present and at least one or more data sectors associated with the media scratch may be relocated to a spare location on the media if the media scratch is determined to be present. If the media scratch is determined not to be present, only the data sector associated with the corresponding physical location may be relocated to the spare location.Type: GrantFiled: June 19, 2012Date of Patent: October 22, 2013Assignee: Western Digital Technologies, Inc.Inventor: Heon Ho Chung
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Patent number: 8560892Abstract: Memory and method for storing a plurality of memory bits. The memory has a data storage element and a processor. The data storage element has a plurality of lines, each having a plurality of segments having a plurality of data bits. A plurality of error correction codes are each associated with one of the lines. A plurality of validity bits, each being associated with one of the lines, are configured to indicate that one of the error correction codes associated with the one of the lines is valid or invalid. The processor is configured to generate one of the error correction codes for all of the data bits in the segments associated with one of the lines.Type: GrantFiled: December 14, 2010Date of Patent: October 15, 2013Assignee: Medtronic, Inc.Inventor: James W. Nicholes
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Patent number: 8555130Abstract: A method begins by a processing module receiving a write request that includes a batch of encoded data slices and a corresponding batch of slice names, wherein the batch of encoded data slices includes encoded data slices that have slices names that have a common data object storage name, a common slice storage name, and a different data segment storage name. The method continues with the processing module determining whether a storage file exists based on the common data object storage name. The method continues with the processing module creating the storage file based on the common data object storage name when the storage file does not exist. The method continues with the processing module storing the batch of encoded data slices in the storage file based on the corresponding batch of slice names.Type: GrantFiled: October 4, 2011Date of Patent: October 8, 2013Assignee: Cleversafe, Inc.Inventors: Andrew Baptist, Ilya Volvovski, Wesley Leggette, Greg Dhuse, Jason K. Resch
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Patent number: 8549378Abstract: Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.Type: GrantFiled: June 24, 2010Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Luiz C. Alves, Luis A. Lastras-Montano, Patrick J. Meaney, Eldee Stephens, Barry M. Trager
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Patent number: 8549384Abstract: Apparatus having corresponding methods and computer-readable media comprise an encoder configured to provide encoded data according to an error correction code; a flash memory interface configured to write the encoded data to a location in flash memory, and to read the encoded data from the location in the flash memory; a decoder configured to decode the encoded data read from the location in the flash memory, and to indicate a number of resulting decode errors; and a retirement module configured to retire the location responsive to a number of resulting decode errors reaching an error threshold T.Type: GrantFiled: June 24, 2010Date of Patent: October 1, 2013Assignee: Marvell International Ltd.Inventors: ChengKuo Huang, Sui-Hung Fred Au, Xueshi Yang, Lau Nguyen
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Patent number: 8549366Abstract: The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.Type: GrantFiled: January 6, 2010Date of Patent: October 1, 2013Assignee: Fujitsu LimitedInventors: Masanori Higeta, Kenji Suzuki, Takatsugu Sasaki
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Patent number: 8543862Abstract: A computer is programmed to execute a diagnostic procedure either on a pre-set schedule or asynchronously in response to an event, such as an error message, or a user command. When executed, the diagnostic procedure automatically checks for integrity of one or more portions of data in the computer, to identify any failure(s). In some embodiments, the failure(s) may be displayed to a human, after revalidation to exclude any failure that no longer exists.Type: GrantFiled: November 25, 2011Date of Patent: September 24, 2013Assignee: Oracle International CorporationInventors: Mark Dilman, Michael James Stewart, Wei-Ming Hu, Balasubrahmanyam Kuchibhotla, Margaret Susairaj, Hubert Ken Sun
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Patent number: 8543801Abstract: A method for booting a computer system is disclosed. The computer system has a main memory. The method includes the steps of providing a backup memory, replacing the main memory by the backup memory when the computer system is booted and the main memory fails to operate normally, and decompressing the program codes of the BIOS to the backup memory to perform the backup booting procedure.Type: GrantFiled: February 3, 2010Date of Patent: September 24, 2013Assignee: ASUSTeK Computer Inc.Inventors: Shao-Kang Chu, Hsu-Hung Cheng
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Publication number: 20130246857Abstract: A controller includes an address generator that sets a plurality of different paths, each connecting an information processing apparatus connected to a storage apparatus via a network, first and second storage mediums, and the controller, and generates a second address that is different from a first address used for a communication with the information processing apparatus via the network; an access monitor that determines that no access has been issued for a certain time duration from the information processing apparatus to the first or second storage medium; an access issuing unit that issues a test access to the first and second storage mediums on one of the paths, using the second address; and an access decoder that converts the test access to an access including the first address, receives a result of the access including the first address from the first or second storage mediums, and checks for an error.Type: ApplicationFiled: February 13, 2013Publication date: September 19, 2013Applicant: FUJITSU LIMITEDInventor: Kiyoto MINAMIURA
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Patent number: 8539284Abstract: An application can specify reliability values via a communication path between the application and the registers. Application reliability could increase if the application itself could specify the timeout and retry values. For instance, some errors might be prevented if the timeout value is lengthened by a short amount. A longer timeout value would result in slower performance because the memory component could not be accessed during the timeout period. However, resolving errors in memory devices would prevent unrecoverable error indicators from being returned to the application, which would in turn limit application and system crashes. Creating a communication path between the application and the hardware registers would allow the application to modify the reliability of memory operations.Type: GrantFiled: January 13, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Jay W. Carman, Anshuman Khandual, Jyotindra Patel
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Patent number: 8539289Abstract: In a memory testing method for testing a memory module of a computing device, an operating voltage of the memory module is adjusted to a first voltage or a second voltage. A predetermined data set is written into the memory module after the operating voltage of the memory module is adjusted, and the written data set is read out from the memory module, to accomplish a data writing and reading process of the memory module. A register value that presents how many memory errors have occurred during the data writing and reading process is acquired from an ECC register of the memory module, to determine whether the memory module is stable during the adjusting of the operating voltage according to the register value.Type: GrantFiled: December 7, 2011Date of Patent: September 17, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Jie-Jun Tan, Yu-Long Lin, Hua Dong
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Publication number: 20130238941Abstract: With a command delay time measurement unit that issues a first test command while the medium error status generator generates the medium error status, and measures a delay time of a command response for the first test command as a command delay time, and a response interval measurement unit that issues a plurality of second test commands to the storage apparatuses to be examined under a higher load when no error occurs, and measures an interval of each command response for the plurality of second test commands as a response interval, and by calculating, for each of the plurality of types of the storage apparatuses, a reference time for each storage apparatus type by adding the command delay time and the response interval, an error can be detected more efficiently.Type: ApplicationFiled: April 8, 2013Publication date: September 12, 2013Applicant: FUJITSU LIMITEDInventors: Shun ANDO, Yuji Noda
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Patent number: 8533538Abstract: Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and modifying by the memory controller the C/A signal in response to determining an error in the memory module, wherein the error pin is a parity error pin of the memory module, and wherein the memory module comprises a Double Data Rate 4 (DDR4) interface.Type: GrantFiled: June 28, 2010Date of Patent: September 10, 2013Assignee: Intel CorporationInventors: Santanu Chaudhuri, Joseph H. Salmon, Kuljit S. Bains
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Patent number: 8533535Abstract: A memory device and a method of controlling the memory device are provided, comprising: generating commands at a memory controller; counting a number of commands in response to a clock signal; storing the commands and the count numbers corresponding to the commands; transmitting to a memory device the commands, the count number of the commands, and data; receiving at the memory device the commands, the count number of the commands, and data sent from the memory controller; counting at the memory device the number of commands received in response to the clock signal; storing at the memory device the count number of commands received; and transmitting the count number of the commands received to the memory controller, wherein said transmitting the count number of the command to the memory controller is performed upon indication of an error condition.Type: GrantFiled: January 12, 2011Date of Patent: September 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Tae-youg Oh
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Patent number: 8533539Abstract: Systems and methods for fault handling are presented. In one embodiment, a fault handling method includes: performing an error type detection process including determining if an error is a media error or a connectivity error; performing a detachment determination process to establish an appropriate detachment scenario, wherein the appropriate detachment scenario includes not detaching any mirrors if the connectivity error involves all mirrors; and returning an application write with a failure. In one embodiment, the detachment determination process detaches a mirror in accordance with results of a read-write-back process. In one exemplary implementation, the detachment determination process includes a connectivity status inquiry and mirrors are detached in accordance with results of the connectivity status inquiry. In one exemplary implementation, the connectivity status inquiry includes a SCSI connectivity inquiry.Type: GrantFiled: September 17, 2010Date of Patent: September 10, 2013Assignee: Symantec CorporationInventors: Shailesh Marathe, Rajesh Chepuri
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Patent number: 8527806Abstract: The present invention provides an information processing device having a CPU which executes an OS and firmware, and a plurality of memory controllers which are connected to the CPU, control writing to and reading from a plurality of memory units, and perform error monitoring, wherein the plurality of memory units each connected to the plurality of memory controllers, the memory controllers sequentially read memory areas of the plurality of memory units connected to the memory controllers, and perform error area monitoring, and the firmware converts addresses recognized by the memory controllers corresponding to the error areas into logical addresses recognized by the OS, and supplies the logical addresses to the OS.Type: GrantFiled: September 21, 2007Date of Patent: September 3, 2013Assignee: Fujitsu LimitedInventor: Shin Endou
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Patent number: 8516301Abstract: A method for diagnosing problems in a computer system by visualizing flows through subsystems of the computer system. Diagnostic tools include a user interface which includes a triage map which graphically depicts subsystems, such as applications, through which a Business Transaction flows, and the calling relationship between the subsystems. The subsystems can be depicted by nodes which include alerts and performance information. The user can run a command to find transactions of a specific Business Transaction and/or front end subsystem which meet filter criterion such as response time and user identifier. Each captured transaction can be listed with information such as response time and reporting agent. Details of a particular transaction instance, such as its invoked components, can also be viewed in a transaction trace.Type: GrantFiled: April 8, 2011Date of Patent: August 20, 2013Assignee: CA, Inc.Inventors: Laura G Beck, Natalya E Litt, Nathan A Isley
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Patent number: 8516299Abstract: A dispersed storage device for use within a dispersed storage network operates to select a set of dispersed storage units for storage of a data object by slicing an encoded data segment of a data object into error coded data slices, determining slice metadata for the error coded data slices, determining memory characteristics of dispersed storage units capable of storing the error coded data slices and selecting the set of dispersed storage units for storing the error coded data slices based on the slice metadata and the memory characteristics.Type: GrantFiled: August 24, 2012Date of Patent: August 20, 2013Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, S. Christopher Gladwin
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Patent number: 8514677Abstract: A method of recording a temporary defect list on a write-once recording medium, a method of reproducing the temporary defect list, an apparatus for recording and/or reproducing the temporary defect list, and the write-once recording medium. The method of recording a temporary defect list for defect management on a write-once recording medium includes recording the temporary defect list, which is created while data is recorded on the write-once recording medium, in at least one cluster of the write-once recording medium, and verifying if a defect is generated in the at least one cluster. Then, the method includes re-recording data originally recorded in a defective cluster in another cluster, and recording pointer information, which indicates a location of the at least one cluster where the temporary defect list is recorded, on the write-once recording medium.Type: GrantFiled: December 21, 2007Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-hee Hwang, Jung-wan Ko
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Patent number: 8516298Abstract: A data protection method for damaged memory cells is provided. A power-on self-test (POST) is executed, and an initial backup memory is reserved in a memory. An operating system (OS) is executed, and data is loaded from a kernel region of the OS in the memory into a mirror region, so that when a processor accesses the data in the kernel region, it also accesses the data in the mirror region. An uncorrectable error (UE) is detected to determine a damaged page, and a backup page is selected from the initial backup memory or dynamically obtained from the OS to back up data in the damaged page. A mapping address of the damaged page and backup page are recorded into a page mapping table in a memory controller. Accordingly, when the OS accesses the damaged page, the memory controller accesses the backup page instead according to the page mapping table.Type: GrantFiled: June 10, 2011Date of Patent: August 20, 2013Assignee: Inventec CorporationInventors: Ying-Chih Lu, Yu-Hui Wang
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Patent number: 8516310Abstract: The embodiments provide a failure diagnosis method for a main memory in an information processing device equipped with a write-back cache. According to the method, an application program stored in the main memory is divided by the storage size of write-back cache, and the regions are stored in advance. Then, a read signal from the main memory to the write-back cache is detected. It is determined whether the region corresponding to the read signal has yet to be diagnosed. If the region has yet to be diagnosed, a command to diagnose failure of the region is issued. If a write signal (write back) to a particular region is detected during the diagnosis of the particular region, the diagnosis of the particular region is stopped. Thus, the failure diagnosis of the main memory is executed in parallel with the execution of the application program.Type: GrantFiled: February 11, 2011Date of Patent: August 20, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Naoya Ohnishi, Hiroshi Nakatani, Yoshito Sameda
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Publication number: 20130212427Abstract: Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.Type: ApplicationFiled: February 14, 2012Publication date: August 15, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma
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Patent number: 8510605Abstract: A computer system having a plurality of devices including a data storage part which includes a plurality of cells to store data, and a controller to inspect whether there is a defective cell in the data storage part if a condition to execute a cell inspection function is met, and sets the defective cell to be assigned to one of the devices if a defective cell is found.Type: GrantFiled: April 25, 2011Date of Patent: August 13, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventor: Kyu-in Han
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Patent number: 8510596Abstract: A method or apparatus detects a memory corruption of at least one portion of memory during run-time and corrects the memory corruption of the at least one portion of memory by replacing the at least one portion of memory with a backup of the at least one portion of memory. In this way, memory corruption can be corrected in a timely fashion while minimizing security risks.Type: GrantFiled: July 6, 2007Date of Patent: August 13, 2013Assignee: Virsec Systems, Inc.Inventors: Satya V. Gupta, Prashant Shenoy
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Patent number: 8504847Abstract: A data element can be encoded into multiple encoded data elements using an encoding algorithm that includes an encoding function and one or more encoder constant. The encoded data elements can be organized into multiple pillars, each having a respective pillar number. Each of the pillars is sent to a different storage unit of a distributed storage network. To recover the original data element, the encoded data elements are retrieved from storage, and the encoder constant is recovered using multiple encoded data elements. Recovering the encoder constant allows the encoding algorithm originally used to encode the data elements to be determined, and used to recover the original data element. The security of the stored data is enhanced, because an encoded data element from a single pillar is insufficient to identify the encoder constant.Type: GrantFiled: April 18, 2010Date of Patent: August 6, 2013Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Wesley Leggette
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Patent number: 8504878Abstract: Embodiments of the invention provide systems and methods for analyzing memory heap information for investigation into a memory leak caused by an application. According to one embodiment, a method of analyzing heap data can comprise obtaining the heap data from a memory. The heap data can represent a plurality of objects of one or more classes, each object identifying a referrer instance, a field in the referrer, and a referent instance. A statistical analysis can be performed on the heap data to identify objects within the heap that are contributing to a growth of the heap. The heap can be traversed based on the referrer instance of one or more objects identified as contributing to the growth of the heap to a root object identified as not contributing to the growth of the heap.Type: GrantFiled: May 4, 2010Date of Patent: August 6, 2013Assignee: Oracle International CorporationInventor: Oleksandr Otenko
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Patent number: 8499227Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.Type: GrantFiled: September 23, 2010Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Larry J. Koudele, John L. Seabury, Stephen P. Van Aken, Guy R. Wagner
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Patent number: 8499192Abstract: A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.Type: GrantFiled: September 21, 2010Date of Patent: July 30, 2013Assignee: STMicroelectronics (Rousset) SASInventor: Hubert Rousseau
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Patent number: 8499201Abstract: Mechanisms for measuring, analyzing, and presenting performance data associated with a memory controller system are described. The mechanisms include a performance monitor that detects and analyzes performance including efficiency and latency of a memory controller system. In addition to determining performance, the systems identifies reasons for loss of memory controller system efficiency. Moreover, the reasons, the efficiency, and the latency are analyzed and presented in a manner easily understandable to a user.Type: GrantFiled: July 22, 2010Date of Patent: July 30, 2013Assignee: Altera CorporationInventors: Gordon Raymond Chiu, Joshua David Fender, Clement C. Tse, Deshanand Singh
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Patent number: 8499217Abstract: Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.Type: GrantFiled: May 14, 2008Date of Patent: July 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Hwan Song, Jun Jin Kong, Jae Hong Kim, Kyoung Lae Cho, Sung Chung Park
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Patent number: 8499198Abstract: A data storage device (DSD) test system is disclosed comprising a first DSD tester operable to download a first version of an operating system to a first DSD and execute a first test on the first DSD, and a second DSD tester operable to download a second version of the operating system to a second DSD and execute a second test on the second DSD while the first DSD tester is executing the first test on the first DSD.Type: GrantFiled: December 14, 2010Date of Patent: July 30, 2013Assignee: Western Digital Technologies, Inc.Inventors: Carl R. Messenger, Karsten C. Strecke
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Patent number: 8495464Abstract: Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.Type: GrantFiled: June 28, 2010Date of Patent: July 23, 2013Assignee: Intel CorporationInventors: Henry Stracovsky, Michael Espig, Victor W. Lee, Daehyun Kim
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Patent number: 8495431Abstract: A method, system and computer program product for generating device fingerprints and authenticating devices uses initial states of internal storage cells after each of a number multiple power cycles for each of a number of device temperatures to generate a device fingerprint. The device fingerprint may include pairs of expected values for each of the internal storage cells and a corresponding probability that the storage cell will assume the expected value. Storage cells that have expected values varying over the multiple temperatures may be excluded from the fingerprint. A device is authenticated by a similarity algorithm that uses a match of the expected values from a known fingerprint with power-up values from an unknown device, weighting the comparisons by the probability for each cell to compute a similarity measure.Type: GrantFiled: May 30, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Fadi H. Gebara, Joonsoo Kim, Jeremy D. Schaub, Volker Strumpen
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Patent number: 8495112Abstract: Management of a file hierarchy for a clustered file system can be distributed across nodes of the cluster. A cluster file hierarchy is accessed to determine location of a file in response to a request to write to a file. A first node maintains the cluster file hierarchy. It is determined that management of a fileset object, which represents a fileset that includes the file, has been delegated to a second node based, at least in part, on said accessing the cluster file hierarchy. A node file hierarchy maintained by the second node is accessed responsive to determining the delegation. The cluster file hierarchy represents filesets of the clustered file system and the node hierarchy represents a subset of one or more of the filesets. Location of the file is determined based, at least in part, on said accessing the node file hierarchy.Type: GrantFiled: September 10, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Janet E. Adkins, Joon Chang, David J. Craft, Gokul B. Kandiraju, Manoj N. Kumar
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Patent number: 8495432Abstract: Described are embodiments of an invention for blocking write access to memory modules of a solid state drive. The solid state drive includes a controller access module or a memory access module that controls write access to the solid state drive and the memory modules of the solid state drive. Upon determining that a memory module has failed, the failed memory module or the entire solid state memory device is configured to be read only to prevent an errant write of data over critical data. Further, a failed memory module, or solid state device memory having a failed memory module, may be replaced upon failure.Type: GrantFiled: May 31, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Louie Arthur Dickens, Timothy A. Johnson, Craig Anthony Klein, Gregg Steven Lucas, Daniel James Winarski
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Patent number: 8495436Abstract: An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle.Type: GrantFiled: June 17, 2012Date of Patent: July 23, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Deepak Agrawal, Rachna Lalwani
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Publication number: 20130185598Abstract: Methods and apparatus are provided for multi-tier detection and decoding in flash memory devices. Data from a flash memory device is processed by obtaining one or more read values for at least one bit in a given page of the flash memory device; converting the one or more read values for the at least one bit to a reliability value; performing an initial decoding of the at least one bit in a given page using the reliability value; and performing an additional decoding of the at least one bit in the given page if the initial decoding is not successful, wherein the additional decoding uses one or more of additional information for the given page and at least one value for at least one bit from at least one additional page.Type: ApplicationFiled: December 31, 2012Publication date: July 18, 2013Inventor: LSI Corporation
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Publication number: 20130185599Abstract: Methods and apparatus are provided for detection and decoding in flash memories using a correlation of neighboring bits or errors in neighboring bits. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a given page of the flash memory device; converting the one or more read values for the plurality of bits to a reliability value for a bit among said plurality of bits based on a probability that a data pattern was written to the plurality of bits given that a particular pattern was read from the plurality of bits; and decoding the bit in the page using the reliability value. The probability that the data pattern was written to the plurality of bits given that the particular pattern was read from the plurality of bits is obtained from one or more tables.Type: ApplicationFiled: December 31, 2012Publication date: July 18, 2013Applicant: LSI CorporationInventor: LSI Corporation
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Patent number: 8489922Abstract: A method and apparatus for networked recovery system is described herein. In one embodiment, a process is provided to obtain a type of recovery selected by a user. A non-volatile partition of a storage volume containing a recovery disk image is accessed. The recovery disk image does not include an installation package. If the obtained type of recovery is a predetermined type of recovery, a network connection is established using the recovery disk image and data is downloaded over the network connection for the obtained type of recovery. The obtained type of recovery of the system is performed.Type: GrantFiled: November 17, 2010Date of Patent: July 16, 2013Assignee: Apple Inc.Inventor: Jack R. Matthew
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Patent number: 8489940Abstract: Methods and apparatus for managing exchange IDs for multiple asynchronous dependent I/O operations generated for virtual Fibre Channel (FC) target volumes. Features and aspects hereof allocate a range of exchange identifier (X_ID) values used in issuing a plurality of physical I/O operations to a plurality of physical FC target devices that comprise the virtual FC target volume. The plurality of physical I/O operations are dependent upon one another for completion of the original request to the virtual FC target volume and allow substantially parallel operation of the plurality of physical FC target devices. A primary X_ID is selected from the range of allocated X_ID values for communications with the attached host system that generated the original request to the virtual FC target volume.Type: GrantFiled: April 16, 2010Date of Patent: July 16, 2013Assignee: NetApp, Inc.Inventors: Howard Young, Srinivasa Nagaraja Rao