Abstract: A module unit for connecting a data bus participant to a local bus. The module unit has a first input interface and a first output interface which can be connected to the local bus, a first data connection interface which can be connected to the data bus participant, and a first switch which is adapted so as to assume a first or a second switch state depending on a control input from the data bus participant, connect the first input interface to the first output interface in the first switch state, and connect the first data connection interface to the first output interface in the second switch state.

Abstract: A system, computer program product, and method are presented for providing confidence values for replacement data for data that has issues indicative of errors, where the data issues, the replacement data, and confidence values are related to one or more KPIs. The method includes identifying one or more potentially erroneous data instances and determining one or more predicted replacement values for the potentially erroneous data instances. The method further includes determining a confidence value for each predicted replacement value and resolving the one or more potentially erroneous data instances with one predicted replacement value of the one or more predicted replacement values. The method also includes generating an explanatory basis for the resolution of the one or more potentially erroneous data instances.

Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.

Abstract: A neural network data processing apparatus includes: an instruction parsing module, configured to split a DMA task into multiple subtasks and acquire configuration information of a data sub-block corresponding to each subtask, where the subtasks are in a one-to-one correspondence with data sub-blocks of transported neural network data; a data reading module, configured to read a first data sub-block according to the configuration information, where the first data sub-block is a data sub-block among data sub-blocks corresponding to multiple subtasks; a data processing module, configured to compress the first data sub-block; a data write-out module, configured to output compressed data resulting from the compression of the first data sub-block.

Abstract: In an embodiment, a method comprises at a network device in an enterprise network, selecting one or more time servers used for establishing a timing reference according to a predetermined priority order of selection that begins with determining whether the network device is configured with information indicating one or more time servers to be used. A timing reference is established for the network device based on a selected time server.

Abstract: A backplane testing system is provided. Based on the connection relationship and signal transfer relationship of a differential signal transceiver, a backplane and a loop device, the differential signal transceiver generates a set of pseudo random binary sequence (PRBS) as a differential signal, and sends the differential signal and receives the returned differential signal, and then determines whether the differential signals sent and received are the same; and the differential signal transceiver generates a test signal that conforms to the IEEE-1149.6 boundary scan test standard, and sends the test signal and receives the returned test signal through a second positive differential signal circuit and a second negative differential signal circuit, and then determines whether the test signals sent and received through the second positive differential signal circuit are the same and whether the test signals sent and received through the second negative differential signal circuit are the same.

Abstract: A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command to the slave functional block. The slave functional block includes a first bus protector. The first bus protector receives the first command on behalf of the slave functional block and transmits a dummy signal corresponding to the first command to the master functional block in response to the slave functional block being in a state of not being able to receive the first command or not being able to transmit a response signal corresponding to the first command.

Abstract: Disclosed is a bus data monitor (“BDM”) for use with a MIL-STD-1553 data bus (“1553 bus”). The BDM includes one or more processing units and a computer-readable medium. The computer-readable medium includes encoded thereon computer-executable instructions to cause the one or more processing units to receive data from the 1553 bus in signal communication with the BDM, access a rule set from a computer file stored on the computer-readable medium, compare the received data from the 1553 bus against the rule set, and determine if the received data violates any of the sub-rules defined in the rule set, where the rule set includes a plurality of defined sub-rules.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: A central network component, a FlexRay-compatible central network component, and a method for bit processing in a central network component are described. In one embodiment, a central network component for facilitating communication among communication nodes includes a bit oversampling module configured to oversample bits received from a first communication node of the communication nodes with an oversampling factor to generate oversampled bit streams, a time point selection module configured to select time points in the oversampled bit streams, where the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor, and a bit outputting module configured to output the inner samples to a second communication node of the communication nodes between the time points. Other embodiments are also described.

Abstract: A memory system may include a nonvolatile memory device and a controller. The nonvolatile memory device may include a data area and a device information area, the device information area being inaccessible accessed by a host. The controller may be configured to perform the training operation with respect to a data signal transmitted to or received from the nonvolatile memory device based on training information stored in the device information area. The controller may be configured to select one of a first training operation and a second training operation based on an identification code of the training information, and to perform the selected one of the first training operation based on a rooted training code generated by the controller and the second training operation based on a dynamic training code of the training information, the second training operation including performing a fewer number of searches than the first training operation.

Abstract: Checksum values are generated and used to verify the data integrity. A client executing in a parallel computing system stores a data chunk to a shared data object on a storage node in the parallel computing system. The client determines a checksum value for the data chunk; and provides the checksum value with the data chunk to the storage node that stores the shared object. The data chunk can be stored on the storage node with the corresponding checksum value as part of the shared object. The storage node may be part of a Parallel Log-Structured File System (PLFS), and the client may comprise, for example, a Log-Structured File System client on a compute node or burst buffer. The checksum value can be evaluated when the data chunk is read from the storage node to verify the integrity of the data that is read.

Abstract: A computer analyzes the root cause of an event, which has occurred in any of multiple management-target apparatuses, based on one or more rules in a storage device, that denote an association between one or more condition events corresponding to one or more events capable of occurring in any of the multiple management-target apparatuses and a conclusion event, which is the cause in a case where the one or more condition events have occurred. The computer, based on an event occurrence log including contents and an occurrence date and time of an event, determines a first event group, which is multiple events presumed to occur as a result of the same cause, creates a new rule in which the multiple events of the first event group are the condition events and one event of the first event group is the conclusion event, and stores the created new rule.

Abstract: Configurable, error-tolerant communication of memory control information between components of a memory system. A controller component and memory component each have a variable-width command/address (CA) interface that operates in conjunction with an error detection/correction (EDC) channel to enable a variable level of error detection and correction with respect to command/address information conveyed between the two components as the widths of the CA interfaces are adjusted.

Abstract: A computer-implemented method for detecting fault conditions experienced by remote physical ports may include (1) identifying a network connection between a first physical port operating in a first communication mode and a second physical port operating in a second communication mode, (2) monitoring at least one count that identifies the number of block-sized transmission errors encountered by the first physical port, (3) determining that the second physical port has experienced a fault condition based at least in part on the count that identifies the number of block-sized transmission errors encountered by the first physical port and then, in response to determining that the second physical port has experienced the fault condition, (4) deactivating the network connection to avoid dropping network traffic directed to the network connection. Various other systems, methods, and apparatuses are also disclosed.

Abstract: A method begins with a computing device dividing data into data partitions. For a data partition of the data partitions, the method continues with the computing device associating indexing information with the data partition. The method continues with the computing device segmenting the data partition into a plurality of data segments. The method continues with the computing device dispersed storage error encoding the plurality of data segments to produce a plurality of sets of encoded data slices. The method continues with the computing device grouping encoded data slices of the plurality of sets of encoded data slices to produce a set of groupings of encoded data slices.

Abstract: The present invention relates to methods and systems for method of implementing proactive token renewal and management in secure conversations. The method includes transmitting an secure conversation token (SCT) bootstrap request, receiving a first SCT in response to the SCT bootstrap request, and determining a round trip time (RTT) of the SCT bootstrap request. The method further includes determining the expiration time of the first SCT, based on the combination of the RTT and the expiration of the first SCT, scheduling an SCT renew request, and initiating the SCT renew request. Further, the method includes receiving a second SCT in response to the SCT renew request, receiving an indication that the first SCT has expired, and in response to the indicating, utilizing the second SCT.

Abstract: A method for providing port arbitration verification for a design under test (DUT) is provided. The method includes sampling the availability of ports at a predetermined number of clock cycles prior to an arbitration point. The method predicts a winner at each of the clock cycles and determines a verification result based on a match between one of the predicted winners and an actual arbitration winner for the DUT.

Abstract: A computing device for indicating a physical layer error is described. The computing device includes a processor and instructions stored in memory that is in electronic communication with the processor. The computing device generates a command for a testing device. The command includes a directive to capture at least one physical layer signal corresponding to a communications interface between a first electronic device and a second electronic device. The computing device also obtains data representing the at least one physical layer signal. The computing device additionally stores the data in a storage device to obtain stored data. The stored data indicates any physical layer error.

Abstract: A method for decreasing the risk of monitoring data failing to be stored includes periodically sending a test message from the monitoring device to a Networked Storage Device, NSD, generating an NSD fail signal in the monitoring device if events following the sending of the test message indicates that the NSD is not operating properly, and sending, in response to the NSD fail signal, a fail message from the monitoring device for detection outside housing of monitoring device.

Abstract: In some embodiments, an apparatus includes a gateway device configured to be operatively coupled to a Fiber Channel switch by a first data port and a second data port. The gateway device is configured to designate the first data port as a primary data port and the second data port as a secondary data port. The gateway device is configured to associate a set of virtual ports with the first data port and not the second data port when in the first configuration. The gateway device is configured to associate the set of virtual ports with the second data port when in the second configuration. The gateway device moves from the first configuration to the second configuration when an error associated with the first data port is detected.

Abstract: A controller module (CM) includes buffers that feed back signals output using respective signal lines used for mutual communication with other CM, and a first detecting unit and a second detecting unit that detect abnormality such that the levels of the signals output using the signal lines do not change from respective specific levels when each level of the fed-back signals does not coincide with an expected level being a level previously determined according to a predetermined timing.

Abstract: An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.

Abstract: Various systems, processes, and products may be used to manage the transmission and reception of messages. In particular implementations, a system, process, and product for managing message transmission and reception may include the ability to receive a plurality of messages to be transmitted over a communication network, wherein some of the messages have a higher priority and some of the messages have a lower priority, and enqueue descriptors for the messages in a direct memory access queue. The system, process, and product may also include the ability to determine whether an overrun of the queue has occurred, analyze the queue if an overrun has occurred to determine if lower priority messages are associated with any of the descriptors in the queue, and replace, if descriptors for lower priority messages are in the queue, the descriptors for the lower priority messages with descriptors for higher priority messages.

Abstract: The tracking of cluster-wide connectivity information is optimized. I/O errors that result from failed operations in which specific nodes attempt to access shared storage are detected. The start-times of failed operations are tracked. The tracked start-times are compared to the time at which the cluster-wide connectivity information was last updated. Responsive to the results of the comparing, the cluster-wide connectivity information is updated in response only to a single I/O error that results from a single failed operation that was initiated after the update time, wherein additional errors resulting from failed operations with start-times after the update time are also detected, thereby preventing redundant updates of the cluster-wide connectivity information. The update time is set to the time at which the cluster-wide connectivity information is updated.

Abstract: Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.

Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

Abstract: Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.

Abstract: Systems, apparatuses, and method for handling timeouts in a link state training sequence are described. All modules of a port undergoing link state training placed into an intermediate state prior to entry into the lowest power state.

Abstract: A system and method for an approach of detecting faults in a redundant bus system based upon four timers.

Abstract: An approach is provided in which a network hardware adapter stores offload information in a shared memory area that is located on a host system. The offload information includes connection information that was offloaded to the network hardware adapter by an application executing on the host system. An operating system (e.g., a network device driver) detects a network adapter error corresponding to the network hardware adapter and, in turn, retrieves the offload information stored in the shared memory area. As such, an analysis application utilizes the retrieved offload information to debug the network adapter error.

Abstract: An approach is provided in which a network hardware adapter stores offload information in a shared memory area that is located on a host system. The offload information includes connection information that was offloaded to the network hardware adapter by an application executing on the host system. An operating system (e.g., a network device driver) detects a network adapter error corresponding to the network hardware adapter and, in turn, retrieves the offload information stored in the shared memory area. As such, an analysis application utilizes the retrieved offload information to debug the network adapter error.

Abstract: Systems and methods presented herein provide for resetting a controller in a Single Root Input/Output Virtualization (SR-IOV) architecture. The architecture includes a physical function that periodically issues a heartbeat command to a physical function of an SR-IOV controller, starts a first timer, determines a firmware failure of the controller upon expiration of the first timer, and issues a command to reset the firmware of the controller. The architecture also includes a plurality of a virtual function drivers coupled to a plurality of virtual functions of the controller. Each virtual function driver periodically issues a heartbeat command to its corresponding virtual function, starts a second timer having a duration that is less than a duration of the first timer, determines a firmware failure of the controller upon expiration of the second timer, and pauses input/output operations to its corresponding virtual function until the firmware of the controller is reset.

Abstract: A display screen control device comprises: a communicating part for performing data communication with a web server; a browser for acquiring a display screen available for the user to make the entry operation from the web server via the communicating part and displaying the acquired display screen on a display part; an error detecting part for detecting whether or not a display error of a content contained in the display screen acquired by the browser is occurred with the display screen being displayed; an error determining part for determining whether or not the content in which the display error is detected is necessary for the user to continue the entry operation when the display error is detected by the error detecting part; and an annunciation controlling part for controlling displaying or not displaying an annunciation image to alert the user to again acquire the display screen on the display part.

Abstract: A method for maintaining reliable communication on a link between an expander and a storage device is provided. The method includes detecting, by a processor coupled to the link, an error corresponding to the link, and maintaining a count of detected errors for the link, by the processor. The method also includes determining, by the processor, if the count of detected errors is above a first error threshold. If the count of detected errors is not above the first error threshold, then the method repeats the detecting, maintaining, and determining steps. If the count of detected errors is above the first error threshold, then the method provides the processor placing the storage device into a segregated zone.

Abstract: Various embodiments for automated error recovery in a computing storage environment by a processor device are provided. In one embodiment, if a failure is caused by an operation of a hardware management console (HMC) and a malfunction of a current network connection, a cleanup operation is performed on at least a portion of a current HMC configuration, an alternative network connection to the current network connection is made, and a retry operation is performed.

Abstract: An example system includes a bus, a logic device, a controller, and a non-volatile memory. The bus is configured to propagate data including at least system console output data. The logic device is configured to monitor the data on the bus and to store the system console output data in a buffer. The controller is configured to detect a system error, and, in response to the system error, to acquire at least a portion of the system console output data from the buffer. The non-volatile memory is configured to store the portion of the system console output data acquired by the controller.

Abstract: A method and system for controller level identification and isolation of a degraded physical link (PHY) in a serial attached small computer system interface (SA-SCSI) or SAS domain. The method and system uses computer readable code embodied within the controller level of an SAS domain to monitor a plurality of PHY pairs associated as connecting through a wide port. The invention compares a history of PHY pair errors to a tunable timer to determine if PHY errors reach a threshold. Should the threshold be exceeded, the controller disables the error prone PHY pair and delivers a notification. The controller may then re-enable the disabled PHY after user action or port power up.

Abstract: Consistent with embodiments of the present disclosure, a method involves a redriver circuit with compliance test mode features. A redriver circuit is configured to process received compliance patterns for a compliance test mode. A compliance test mode is detected by a redriver circuit having a first input port and a second input port. The redriver detects the presence of a remote receiver termination on both input ports, monitors both input ports to detect received data and enters compliance test mode in response to no received data being detected on the input ports for a set period of time. Compliance patterns are tracked by monitoring for valid signal levels on the second input port. De-emphasis is controlled on at least one input port in response thereto.

Abstract: A technique automatically handles a failure during online data migration from a source array to a target array. While a host initially accesses data from the source array using multipath I/O software, the technique involves (i) transitioning the source array to a passive mode, and the target array to an active mode, and (ii) beginning a data transfer operation which transfers data from the source array to the target array. The technique further involves modifying the data on both the target array and the source array in response to modification commands sent to the target array from the host while the data transfer operation is ongoing. The technique further involves automatically failing back to providing access to the data from the source array in response to an event in which the target array loses communication with the source array for a predefined amount of time.

Abstract: A system for maintaining direct hardware access in the event of PNIC failure. A host for the system includes: a processor; a first and a second PNIC, where the first PNIC is activated and all other PNICs are deactivated; a host operating system; a virtual machine; and a hypervisor for transferring packets between the host operating system and the virtual machine. The host operating system includes a link aggregator, multiple host VNICs, and a virtual switch associated with the VNICs. The first virtual machine includes a virtual network protocol stack and a guest VNIC. The link aggregator is configured to determine whether the first PNIC has failed. Based on a determination that the first PNIC has failed, the link aggregator is further configured to: remove a virtual function mapping between the first PNIC and the virtual machine; determine the second PNIC; deactivate the first PNIC; and activate the second PNIC.

Abstract: A method including creating a commit-in-progress context from a copy of a data object in a redirect-on-write file system; and begin storing the commit-in-progress context in a persistent storage device. The method further includes, while storing the commit-in-progress context in the persistent storage device: receiving a notification of a pending modification to the first data object, creating an update-in-progress context from a copy of the commit-in-progress context, and begin applying the modification to the update-in-progress context. The method further includes detecting that a connectivity error has occurred between the commit-in-progress context and the storage device, and in response, identifying whether the commit-in-progress context is successfully stored in the storage device.

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract: A computer system includes multiple modules that perform communication via a bus, and abnormality detection circuits that monitor signals on the bus related to communication between the modules to detect a hang-up, wherein each of the abnormality detection circuits is arranged to correspond to a part of the multiple modules, and, when detecting the hang-up, generates and outputs a signal instructing reactivation only of the corresponding module.

Abstract: Server management data describes observed operating condition of a pool of spare servers. Based on a demand forecast of a specific target system, a dynamic allocation period is determined as a period during which the target system needs additional server resources to handle an expected demand. Based on the dynamic allocation period and server management data, a set of allocation candidates are nominated from the spare server pool, by eliminating therefrom spare servers which are likely to fail during the dynamic allocation period. An appropriate allocation candidate is then selected for allocation to the target system, such that the selected candidate will satisfy a specified requirement during its allocation period.

Abstract: Various embodiments herein include at least one of systems, methods, and software to detect and reduce messages from network entity management clients that are not utilized by a network management system. Once identified, the network management system may send a command to the network entity management clients to no longer send particular message types to the network management system. The network management system may also, or alternatively, be configured to take no action when such messages are subsequently received.

Abstract: Error handling is simplified for a self-virtualizing IO resource that utilizes a physical function adjunct partition for a physical function in the self-virtualizing IO resource to coordinate error recovery for the self-virtualizing IO resource, by restarting each virtual function adjunct partition associated with that physical function to avoid the need to coordinate error recovery within the logical partitions to which such virtual function adjunct partitions are assigned.

Abstract: A communicating unit used in an X-ray image pickup apparatus in this invention has an error detecting function to detect communication errors, and an FIFO for temporarily storing data received from a control and image processing apparatus, which is an external apparatus, by a receiving function of a communication control unit. Only when no error is detected within a predetermined period before and after receipt of data, by the receiving function of the communication control unit, from the control and image processing apparatus, a transmitting function of the communication control unit performs controls to transmit and write the data received and temporarily stored in the FIFO to/in an external portion. Thus, when a cable is plugged or unplugged or the control and image processing apparatus which is an external apparatus is rebooted, the error detecting function detects this as a communication error. In such cases also, an inadvertent writing of the data can be prevented.

Abstract: A computer program product for performing input/output (I/O) processing is provided. The computer program product is configured to perform: obtaining information relating to an I/O operation at a channel subsystem; generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data check word generation field and/or a data check word save field; responsive to receiving an input data transfer request including at least one data check word, storing the at least one data check word in the data check word save field and performing a check of the data to determine whether the data has been corrupted; and responsive to receiving an output data transfer, generating at least one data check word based on the data check word generation field and appending the at least one data check word to the data.

Abstract: An input/output processing method includes generating and storing at least one address control word (ACW) including a data check word generation field and/or a data check word save field in local channel memory of a channel subsystem, and generating and forwarding to a network interface an address control structure specifying a location in the local channel memory of a corresponding ACW. The method also includes, responsive to a data transfer request, storing the at least one data check word in the data check word save field and routing the data to a host memory location specified by the corresponding ACW responsive to performing a check of the data and determining that the data has not been corrupted, or retrieving the data based on the corresponding ACW, generating and appending at least one data check word and routing the data and the at least one data check word to the interface.