Abstract: A device for monitoring a processor is described. A watchdog simultaneously monitors the system clock, the software base functions and performs a check of the tests of the system components of the processor. If an error is detected, the watchdog communicates this to the processor, an error counter is incremented and at least one device that is connected to the processor is blocked. If the error counter attains a predetermined value, the block is continued until the device of the present invention is deactivated. If an additional error is detected during a blocking time, the blocking time is extended.

Abstract: A event-driven portable data bus message logger includes an event message receiver for receiving an event message including an event field, an event message storage operably connected to the event message receiver for storing the event message, a data bus message receiver for receiving data bus messages including a data field and a data checksum, a comparator for comparing a current data field of a current data bus message to the event field; and a trigger operably connected to the comparator for storing the current data bus message, a preceding data bus message, and a subsequent data bus message in a snapshot storage if the current data field is substantially similar to the event field.

Abstract: A system and method enables a file server, to support multi path input/output operations for Fibre Channel devices. Upon each Fibre Channel Arbitrated Loop initialization event generated, the system and method updates a path and device instance to track multiple paths to a given device. While the file server is attempting input/output operations, the failure of a given path can be corrected by the use of another path associated with a given device. The data structures generated by the low levels of the storage operating system are exposed for use by upper level services for routing a storage device identification purposes.

Abstract: A circuit module has a module board and a plurality of circuit chips that are arranged on the module board. A module main bus having a plurality of lines of the circuit module branches into a plurality of sub-buses having a plurality of lines. Each of the sub-buses is connected to one of the circuit chips. Each circuit chip has an indication signal generating unit for providing an indication signal based on a combination of the signals received on the plurality of lines of the sub-bus connected to the respective circuit chip, and an indication signal output for outputting the indication signal.

Abstract: Volatile memory is placed into a data-preserving safe state in a computer system in response to any one of a reduction in power applied to the volatile memory, a bus reset signal on a data communication bus of the computer system, and an absence of a bus clock signal on the bus. The volatile memory is powered from an auxiliary uninterruptible power supply in response to the reduction in power. The volatile memory is also placed into the data-preserving safe state in response to a cessation in executing software instructions by a CPU of the computer system. Placing the volatile memory into the safe state in response to and under these conditions enhances the opportunity to preserve data in response to error and malfunction conditions.

Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 40-bit wide data every 167 Mhz clock cycle, and the interconnect bus transmits 10-bit wide data at every transition of a 333 Mhz clock cycle. In another embodiment, the transmitter controller accepts 32-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 32-bit wide data every 167 Mhz clock cycle, and the interconnect bus of this embodiment transmits 8-bit wide data at every transition of a 333 Mhz clock cycle. Output pins of the transmitter interface can be connected to any input pins of the receiver interface. Furthermore, the high-speed parallel interface does not require a fixed phase relationship between the receiver's internal clock(s) and the bus clock signal.

Abstract: An information recording device includes a control unit and a memory interface unit. An ICV for each sector data of data to be stored in units of sectors is stored in the redundant part of each sector. An ECC and an ICV are stored in the redundant part of each sector, so that sector-unit ICV storage can be performed without reducing the storage capacity of the data part of the sector. processing that combines data parts by using the file system of a device can be performed similarly to conventional data combination processing that only combines data parts in which ones purely used as data are stored. The control unit does not have any load because only each sector which is regarded as valid (no interpolation) as a result of ICV checking is transmitted to the control unit, and the ICV checking is performed by the memory interface unit.

Abstract: A system and method for delayed error handling. In one embodiment, a computerized method includes sending a Small Computer Systems Interface (SCSI) command to a peripheral device through a network connection, waiting for a SCSI response from the peripheral device, detecting an error in the network connection, waiting for an amount of time that is consistent with the network connection to the peripheral device being re-established, and determining if the error in the network connection has been corrected. In another embodiment, a computerized method includes detecting the iSCSI error on an IP network connection to an iSCSI peripheral device after an iSCSI command has timed out, waiting (upon detection) for an amount of time for the IP network connection to become re-established, checking (while waiting) to determine if the IP network connection has been re-established, and performing an iSCSI error-recovery function if the IP network connection has been re-established.

Abstract: A method, system, and computer program product are disclosed for improving isolation of I/O errors in logical partitioned data processing systems. A machine check is generated that indicates that an I/O error has occurred in the system. The PCI host bridge (PHB) that generated the machine check is identified. The system includes multiple PHBs, each with its own set of slots. Some of these slots may be enabled for enhanced error handling while others of them are not. The adapters that are not enabled for enhanced error handling and that are coupled to the PHB that generated the machine check are identified. It is then determined that the I/O error occurred in at least one of these slots that are not enabled for enhanced error handling.

Abstract: A central node for a data bus system includes a bus monitor unit with receiver means for registering signals on the data bus, and evaluation means which detect incorrect communication on the data bus and at least temporarily block communication by the user that causes the incorrect communication or compensate the incorrect communication of a user which is triggered by the interference influences. The bus monitor unit includes timing means which are triggered according to time patterns for the transmission of each user of the data bus, in order to detect an incorrect communication of a user if the latter transmits outside the time provided for it. The bus monitor unit is integrated into the central bus node and a plurality of bus branches of different users are combined at the central node so that the bus monitor unit can check a plurality of users for incorrect communication. In order to increase reliability, in addition to the bus monitor unit, a diagnostic unit is integrated into the central node.

Abstract: Methods and systems for repairing ports are disclosed. Embodiments may detect a hard failure of a port, select an alternative port from existing ports in use within an array, and share the alternative port to route operands bound for the first port and the alternative port, to transmit operands associated with the failed port to the corresponding destination unit. Embodiments include an additional wire, or an alternative port path, that couples the alternative port to the destination unit that is associated with the first port. For instance, in a multi-pipeline processor, an operand of an instruction that is bound for the failed read port may be routed via an alternative read port to the corresponding execution unit. Similarly, data bound for failed write ports may be, e.g., written back to a register file by routing the data via an alternative write port of the register file.

Abstract: A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

Abstract: Integrated circuit bus integrity may be verified without specialized test equipment. In a diagnostic mode, the integrated circuit may output a series of predetermined activation patterns onto the data bus to verify integrity of the data bus. Further bus verification may be provided by an address capture mode where address bus contents are reflected onto the data bus. A microprocessor may control diagnostic mode operation.

Abstract: A slave interface is equipped with a register that stores a retry set value SRI that is unique for a slave device and a pseudo random number generator that generates a random number value RN, and when a non-acknowledgement response is sent corresponding to a transmission request REQb from a master device, the slave interface transmits non-acknowledgement response incidental information NAINFb that includes the retry set value SRI and the random number value RN to the master interface 2a. The master interface 2a extracts the retry set value SRI and the random number value RN from the non-acknowledgement response incidental information NAINFb, calculates a retry interval value by adding these, and when the interval time according to the retry interval value has passes, resends the transmission request REQb to the slave device. Since the retry interval time is independently set every time, live-lock may be prevented.

Abstract: Methods and arrangements to enhance a bus are disclosed. Embodiments may test bus segments, device interfaces, couplings between devices and device interfaces for bit errors. Several embodiments generate a test signal in response to coupling a device to a device interface, transmit the test signal on the bus, and generate an error signal when the bus signal at the device interface is different from the anticipated bus signal. The test signal may comprise one or more patterns of bits configured to identify one or more faults associated with a bus segment, a bus switch of the device interface to isolate the adapter card from the bus, and circuitry or buffers of the adapter card as plugged into the slot of the device interface. In many of these embodiments, a bus signal is determined at the bus-side and/or slot-side of the device interface.

Abstract: Queued mode event reporting is provided. When an event occurs within a computer, an event report is generated describing the event. If the event report cannot be immediately transmitted, it is stored in a queue for future transmission. The queue for storing the report is chosen based on whether a user should have access to the report and on whether a notification should be provided to the user when the event occurs or prior to sending the event report or at both times. A queue trigger program is also configured to execute when the computer goes online and when a user logs into the computer. The queue trigger program causes the queued reports to be sent, if possible, and causes the appropriate notifications to be shown.

Abstract: A two-phase method to perform root-cause analysis over an enterprise-specific fault model is described. In the first phase, an up-stream analysis is performed (beginning at a node generating an alarm event) to identify one or more nodes that may be in failure. In the second phase, a down-stream analysis is performed to identify those nodes in the enterprise whose operational condition are impacted by the prior determined failed nodes. Nodes identified as failed as a result of the up-stream analysis may be reported to a user as failed. Nodes identifies as impacted as a result of the down-stream analysis may be reported to a user as impacted and, beneficially, any failure alarms associated with those impacted nodes may be masked. Up-stream (phase 1) analysis is driven by inference policies associated with various nodes in the enterprise's fault model.

Abstract: A data stream is transferred through a parallel data bus while the read or write strobe is adjusted. The resultant data is compared to the original data to detect errors with each data line of the parallel bus. The results are displayed on a grid whereby the characteristics of each line of the data bus may be visually understood. The characteristic image of the performance of the data bus may be used for debugging the bus, as well as for other uses wherein the performance is very highly characterized.

Abstract: A streaming direct memory access (DMA) engine is disclosed. The streaming DMA engine includes several power reduction capabilities. A controller throttles the DMA engine according to the system throughput requirement and the system processor operation state. The DMA engine holds off a new read request to the memory if the data present in the DMA engine requires re-transmission. The DMA engine holds off a new write request to the memory if the data present in the DMA engine is corrupted, until the corrupted data is discarded.

Abstract: An I2C MUX with an anti-lock device comprises an I2C multiplexer (I2C MUX) and a reset unit. The I2C MUX is used to connect with a system, which has a central processing unit (CPU), an I2C main control unit, and a plurality of I2C elements. The reset unit is connected to the CPU and the I2C MUX. The I2C main control unit emits a signal to the CPU, and the CPU then sends an open-circuited signal to the reset unit. The reset unit sends a reset signal to the I2C MUX to reconnect the I2C MUX with one of the multiple normal I2C elements and the I2C main control unit when the connection between the chosen I2C element, the I2C MUX and the I2C main control unit is broken.

Abstract: In a computer system, which makes an error detectable in case plural PCI target devices respond in one PCI cycle and the PCI protocol has become illicit, a processor 1 is connected over a PCI bus 10 to plural PCI devices a 100 to d 130, each of which activates corresponding target operating signal a 20 to d 50 respectively when operating as a PCI target device. The PCI bus monitor circuit 200 monitors the target address of a command executed on the PCI bus 10 and the target operating signals a 20 to d 50 from the plural PCI devices a 100 to d 130. If plural PCI target devices have responded for one PCI cycle, the PCI bus monitor circuit 200 sends an error report signal 210 to the processor unit 1.

Abstract: A method for managing a plurality of failures in a video and data network is provided. The method includes discovering a failure in the video and data network. The discovered failure is the root cause of the failure. Next, the root cause failure is correlated with the plurality of failures to determine related failures generated as a result of the root cause failure. The related failures are then suppressed. One or more user's affected by the root cause failure are determined. If the root cause failure is automatically resolvable, the root cause failure is automatically resolved.

Abstract: A method, apparatus, and computer instructions for processing errors in a hierarchical input/output sub-system having an input/output bridge with a plurality of hardware devices in a level below the bridge. A value is read from a selected register to form a read value in response to detecting an error. The selected register is reset. Each bit in the read value associated with the error is cleared to form a cleared value. The cleared value is written into the selected register such that errors occurring since the register was cleared are preserved. The error registers below the bridge are scanned in response to an absence of an error being detected in a bridge within the input/output sub-system. A determination is made as to whether the error has previously occurred in response to a presence of an error being found by scanning the registers below the bridge. The error is reported in response to an absence of a determination that the error has previously occurred.

Abstract: One embodiment of a system for disabling a computer bus upon detection of a power fault includes a bus bridge device coupled to a bus and a power regulator that delivers power to the bus. If the power regulator detects a power fault, then the power regulator asserts a fault signal to the bus bridge device. The power regulator also removes power from the bus. The bus bridge device disconnects an internal logic unit from the bus in response to the assertion of the fault signal. The bus bridge device, in further response to the assertion of the fault signal, alerts the system of the power fault by asserting an interrupt signal.

Abstract: The present invention features a method for performing an end-to-end data path integrity check in a computer or computer-like system such as a storage router. A predetermined data test pattern is stored in a memory and then transmitted across a data path by a data initiator to a data receiver. The received data test pattern is then retransmitted to the data initiator where it is compared to the original data. Any discrepancies cause an error condition to be declared. The data path may be disabled until the defective component in the data path is isolated and fixed. The method is hardware independent so it may be easily used in an open systems environment where hardware components may be provided by different vendors.

Abstract: The present invention provides a method, system and apparatus by which TCP connections may be failed-over from one system to another within a highly available network service, and appear transparent to the remote client. The connection state and ownership information of a system is broadcast within the network, so that if a first system crashes while running an application, a predetermined take-over policy causes a peer system to assume connection without loss of data such that a permanent connection has been established from the client's point of view. After the failed system has been restored to a normal state, new connections are established by the first system. A connection cache device stores connection information for use during the failover.

Abstract: A method, apparatus, and computer instructions for processing errors in a hierarchical hardware sub-system in the data processing system in which the hierarchical hardware sub-system includes a host processor bridge having a mapping registers section and a control and status registers section. In response to detecting an error freezing the mapping registers section in the host bridge, a component within the hierarchical hardware sub-system connected to the host bridge is identified to form a selected component. An address is written to a register within the control and status registers section of the host bridge in which the address is to an error register in the component. Data is read in response to a result from the address written in the register being placed in the control and status registers portion of the host bridge.

Abstract: A segmented protection system and method. The invention comprises a plurality of Processing Modules arranged in series along a Protection Bus. A number of Protection Groups may be formed along the Protection Bus, with each Protection Group comprising at least one Protection Processing Module and at least one Working Processing Module. Upon failure of the Working Processing Module, the Protection Processing Module substitutes for the failed Working Processing Module.

Abstract: A computer network employs a fault-tolerant or redundant switch architecture. The network includes redundant data paths coupling end nodes and switches. Fault-tolerant repeaters (FTRs) can be stand-alone devices or can be incorporated into the switches. Using error detection, the FTR checks to see if the data is good on all paths. If the data received on one path is “bad” and the data is “good” on another path, the FTR transmits the “good” data in place of the “bad” data. For any switch, a pair of incoming ports may be configured as redundant incoming ports and a pair of outgoing ports may be configured as redundant outgoing ports.

Abstract: A communications system may include a plurality of communications buses, at least one bus device connected to the plurality of communications buses, and a plurality of bus controllers for sending a plurality of bus enable signals to the at least one bus device. The at least one bus device may include selection circuitry for selecting one of the communications buses based upon the plurality of bus enable signals while being tolerant of an error on at least one of the bus enable signals. First and second bus enable signals may have a same value and may be generated by a primary bus controller upon receiving power. A third bus enable signal may be generated by a redundant bus controller upon receiving power.

Abstract: The present invention provides a method, system and apparatus for providing failsafe detection for a differential receiver. A bus activity signal (11) is activated when receiving a differential data signal of sufficient amplitude to transition through a predetermined threshold. A failsafe signal (620) indicates a low differential voltage condition. A countdown time period commences (85) upon activation of either signal, and a failsafe condition is determined (89) to exist if the failsafe signal is active (87) when the countdown time period expires (86).

Abstract: A system for generating transactions on a bus includes at least one instruction memory storing predefined bus stimuli instructions and at least one phase generator coupled between the bus and the instruction memory for providing signals to the bus in response to the instruction memory.

Abstract: A core logic chipset for a computer system is provided which can be configured as a bridge between either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chipset and either an AGP or PCI device(s). The common bus, which is part of a fault-tolerant interconnect system, includes a first bus portion and a lower bus portion. When an error (e.g., a parity error) is detected on the first bus portion, the transaction is transferred over the second bus portion. When an error is detected on the second bus portion, the transaction is transferred over the first bus portion. If errors are detected on both portions, the transaction may be terminated.

Abstract: The present invention is an I2C (inter-IC control) bridge device which implements a communication protocol layered on top of a standard I2C protocol. The layered protocol used by the bridge device is termed the “Layered I2C Protocol”—abbreviated “LIP”. Thus the bridge device is called a “LIP bridge device”. The LIP bridge device provides I2C address extension, data integrity checking, and fault detection and isolation when inserted between an I2C bus master and it's intended target I2C device. Each LIP bridge device has at least two attached I2C busses—a parent bus and a child bus. The LIP bridge operates as a slave on its parent bus, and a master of its child bus. The Layered I2C protocol is specified to operate on a bus between one or more bus masters and the parent bus of one or more LIP bridge devices. The child bus is used for attaching multiple I2C devices and/or one or more LIP bridge devices.

Abstract: A method and apparatus for detecting and in some cases recovering from errors in a source synchronous bus. One embodiment of a disclosed apparatus includes a plurality of strobe inputs to receive a plurality of strobe signals. A plurality of data inputs receive a plurality of data signals transmitted in a source synchronous manner in conjunction with the strobe signals. Bus control logic produces an externally visible indication that an error has occurred if a glitch on one or more of the plurality of strobe signals is detected.

Abstract: A dirty memory for a computer system is configured hierarchically. This provides for more rapid identification of pages of memory that have been dirtied and require attention. For example for the reintegration of an equivalent memory state to the memories of respective processing sets in a fault tolerant computer following a lockstep error. The dirty memory includes at least two levels. A lower level includes groups of dirty indicators, each dirty indicator being settable to a given state indicative that a page of memory associated therewith has been dirtied. At least one higher level includes dirty group indicators settable to a predetermined state indicative that a group of the lower level associated therewith has at least one dirty indicator in a state indicative that a page of memory associated therewith has been dirtied. There can be more that two layers. Logic controls the operation of the hierarchical dirty memory.

Abstract: The present invention provides a system and method of detecting a process failure and a network failure in a distributed system. The distributed system includes at least two processes, each executing on a host, operable to transmit messages (i.e., heartbeats) to each other on a plurality of networks in the distributed system. A process in the system is operable to execute a network failure algorithm for detecting failure of a network in the system. The process failure algorithm includes calculating a difference in the period of time to receive a heartbeat on a first network from a process and a period of time to receive a heartbeat on a second network from the process. If the difference exceeds a network failure threshold, the second network is suspected of failing. A process in the system is also operable to execute a process failure algorithm.

Abstract: A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

Abstract: A method system, and computer program product for determining the source of a fault within a bus, such as, for example, an inter integrated circuit (I2C) bus is provided. In one embodiment, a bus driver monitors the bus for faults. If a fault occurs on the bus, the bus driver resets each switch on the bus and then turns on the first switch connected to the bus driver. If the fault is encountered after turning on the first switch, then it is determined that the fault was caused by either the first switch, a device connected to the bus as a result of turning on the first switch, or one of the bus connectors just switched on as a result of turning on the first switch. If the fault is not encountered, the next switch is turned on and the process is repeated until the fault is encountered. The fault when encountered will be caused by either the most recently turned on switch or a device or bus connectors switched in by the turning on of the last switch.

Abstract: Reliability and robustness of a cluster having a host connected thereto via a cluster interconnection fabric may be enhanced by determining if an error condition exists in an I/O controller connected to the host via the cluster interconnection fabric by attempting to communicate with it a first predetermined time period after an inquiry by an operating system as to whether or not an I/O controller driver stack should be unloaded and commanding the operating system to unload the I/O controller driver stack upon a determination that the error condition still exists. The determination as to whether the error condition still exists may be repeated a predetermined number of times prior to commanding the unloading of the I/O controller driver stack upon a determination that the error condition still exists.

Abstract: The invention relates to a microprocessor-controlled standard field device (3′, 4′, 5′, 6′), such as a measuring sensor or an actuator, for connecting to a field bus system (1) that, in turn, is connected to, for example, a freely programmable controller (2′). According to the invention, the field device (3′, 4′, 5′, 6′) is equipped with a security layer (10) for carrying out a security proven communication. A secure and simultaneously cost-effective communication with a control device (2) via a field bus system (1) is made possible by implementing a security layer (10) in a conventional operationally proven or redundant standard field device (3, 4, 5, 6).

Abstract: A method for managing allocation of network resources within the distributed computer system is provided. Specifically, the network traversal time and the end node response time for requests and/or packets being routed in a switch-connected system area network are utilized to determine the total round trip time for completion of the particular network operation. The sum of the timeout values for all switches that participate in routing the request from a requester (source) to the receptor node (target) is provided to the requester's channel adapter (CA). The time-out values are provided by the switch manufacturer and are sent to a network Subnet Manager (SM) via SM packets (SMP). The timeout values added together represent the SubnetTimeout. The time-out value of the target channel adapter (CA), the ResponseTime, is also provided to the requester. The requester then utilizes one of two timeout equations to calculate the overall response time required for the request to be completed.

Abstract: Method and apparatus for link physical error tracking that includes a one or more shift registers, one or more counters, and a comparator. The shift register receives one or more status bits for an input data stream denoting whether bytes of the input data stream have a link physical error. The counter increments an error count when receiving at least one status bit that denotes a link physical error, and decrements the error count when receiving at least one status bit from an output of the shift register that denotes a link physical error. The comparator compares the error count with a maximum value. A retrain signal is generated if the error count becomes larger than or equal to the maximum value. The retrain signal may be used to signal that a connection between two nodes needs to be retrained to get the two nodes back into synchronization. Link physical errors that occur aligned and misaligned with a rising edge of a symbol clock are trackable.

Abstract: A method for testing a computer bus using a bridge chip having a freeze-on-error option that enables a computer system's central processing unit (CPU) to recover and continue processing even when the computer bus is not functional. The testing method of the present invention remains transparent to a user and can be accomplished while performing standard diagnostics tests. In general, the present invention injects an input/output (I/O) error into a specific bus slot of the computer bus to test the functionality (such as the error recovery capability) of the bus. The present invention then recovers from the failure condition without having the computer system shutdown or stop working and without having to restart the computer system. More specifically, the method for testing a computer bus according to the present invention includes enabling the freeze-on-error option on the bridge chip, injecting an error into the specified computer bus slot and recovering from the injected error.

Abstract: Apparatus and methods for rebuilding logical I/O devices in a cluster computer system. The apparatus include controllers programmed to cooperate towards this end. The apparatus has first and second nodes with respective bus controllers communicatively coupled to each other and to the logical I/O device by means of a bus. The first controller receives a request to rebuild the logical I/O device and, in response, conditionally communicates a rebuild request for the logical I/O device over the bus to the second controller. (The logical I/O device can be a logical device depending from a multi-logical-device, third controller.) Before conditionally communicating, the apparatus determines whether a rebuild of a logical I/O device is already in progress and, when a rebuild is already in progress, aborts the new request to rebuild. When an rebuild is not already in progress, the apparatus then sets a state variable to indicate that a rebuild is now in progress.

Abstract: In an information processing system, a failed bus operation is detected. In response to the detecting, a primary power plan is cycled in the information processing system.

Abstract: A method and mechanism, operating within an application layer of the architectural model of a communications protocol, for maintaining high availability in a computer network utilizing virtual Internet Protocol (IP) addresses. A backup connection is created wherein a second network card is added to a node of a computer network. A failover mechanism operating within the application layer captures an original virtual IP configuration corresponding to a primary network connection of the node and monitors the primary network connection. Upon detecting a failure of the primary network connection, the failover mechanism halts monitoring of the primary connection, captures the current virtual IP configuration of the primary network connection, configures the second network interface with the parameters of the primary network interface, and brings up the second interface. If the current virtual IP configuration was successfully captured, it is used in the configuration of the second interface.

Abstract: A method and apparatus for detecting data strobe errors. A strobe error detection circuit has a strobe input and a counter coupled to the strobe input to count strobe pulses received. The circuit also has a comparator to determine if a strobe error has occurred based on the magnitude of the difference between a first count of strobe pulses and a second count of strobe pulses. In an embodiment, the first count is read from a memory location at a first time and the second count is read at a second time.

Abstract: Digital signals are sent in a predetermined sequence from one end of a bus wire and are received at the other end. Each of the digital signals of the received sequence is compared with a corresponding predetermined signal of the predetermined sequence to determine whether an error has occurred. Data obtained concerning bus errors may be used to handle bus errors during runtime.

Abstract: Method and apparatus for reading the internal address space of an adapter in a system during a dump are described. The adapter includes a control port and a data port used as channels for exchanging control messages and dump data between the adapter and the system. The system starts the dump by sending to the data port a specification of a block of the adapter's internal address space. In response, the adapter sends dump data portions to a system buffer via the data port.