Abstract: An information processing device comprising a group of hardware of various types in the first layer, kernel modules and a hang checking part in the second layer, and a group of user programs and a monitoring program for monitoring and grasping the operating states of the user programs in the third layer. The kernel modules are used to access hardware corresponding thereto in response to a request from the user program. The hang checking parts performs hang checking by inspecting whether the hardware access performed by the kernel module is in a normal state or not, and outputting a hardware trouble detection notification in cases where an abnormality in hardware access is detected. The monitoring program checks the operating states of the user programs corresponding to the notification, and executes a specified operation against hardware trouble when these operating states become such that the execution of the operation is permissible.

Abstract: A mechanism to obtain a quiescence state for a component coupled to a bidirectional communications interface is obtained. A transition to quiescence may be may by activating a first defeature in the component to cause messages received over a communication bus coupled between the component and another component to be ignored, and activating a second defeature in the component to prevent messages from being sent over the communication bus by the component. Operations may then be performed on the component while the defeatures are activated.

Abstract: A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator; and determining parametric information pertaining to the I/O circuit of the device under test from the phase signal.

Abstract: Method and system for testing a network device is provided. The system includes, a test program running on a host system that communicates with the network device through a bus functional module; and a test module that includes a packet counter that counts test packets that are received from a buffer and written in a memory of the test module; and an idle timer that counts time that has expired after a last test packet has been received by the memory module of the test module; wherein if the packet counter value exceeds a threshold value then all test packets residing in the memory of the test module are sent for testing network device logic and if the idle timer expires at any given instance, then all the test packets in the memory of the test module are sent for testing network device logic.

Abstract: A segmented protection system and method. The invention comprises a plurality of Processing Modules arranged in series along a Protection Bus. A number of Protection Groups may be formed along the Protection Bus, with each Protection Group comprising at least one Protection Processing Module and at least one Working Processing Module. Upon failure of the Working Processing Module, the Protection Processing Module substitutes for the failed Working Processing Module.

Abstract: Described are techniques for obtaining configuration information and conditionally executing a system call in accordance with a specified configuration state. A host issues a request for configuration information from a data storage system. The data storage system maintains a separate table of configuration information representing a configuration state of the data storage system. The host receives a response including a custom value indicating the current configuration state. The host may issue a request to the data storage system to conditionally execute a call if the data storage system is in a configuration state corresponding to the custom value.

Abstract: A method and apparatus for diagnosing database performance problems using a plurality of wait classes is provided. A set of statistical data that describes current activity within a database system is periodically retrieved. The set of statistical data may include information about the current activity of each user session connected to the database system. Thereafter, a set of cumulative statistical data that describes activity in the database system over a period of time is updated to reflect the retrieved set of statistical data. The set of cumulative statistical data includes statistics associated with each of a plurality of wait classes. A graphical user interface that displays the set of cumulative statistical data may be presented to a user. The graphical user interface allows the user to quickly ascertain the nature of the database performance problems by providing a view of the set of cumulative statistical data.

Abstract: In a bridge which connects between an expansion bus of a primary system and that of a secondary system, a local error such as an expansion bus error and CPU hang-up which occurs in the secondary system is recognized. The primary system is notified of the local error as a system error.

Abstract: A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.

Abstract: The embodiments of the present invention disclose a method for isolating a bus failure, which includes: acquiring, from a Compact PCI bus, an address of a target board being accessed; counting retry responses on the Compact PCI bus, wherein the retry responses are generated by access to the target board; sending a reset signal to the target board in response to that the times of the retry responses exceed a retry times threshold. With the embodiments of this invention, the normal operation of a failed device in the system may be restored in time, which may avoid that the bus is hanged up and is favorable for maintenance.

Abstract: A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.

Abstract: Method and systems are described for testing an address line inter-coupling a processor and a memory. The contents of a first address in the memory are initially compared with the contents of a second address in the memory, wherein each of the first and second addresses are addressable in the memory by a different value applied on the address line. If the contents of the first and second addresses match, the contents of either one of the first and second addresses are changed, and a subsequent comparison of the contents of the first and second memory addresses is performed. If the second comparison determines that contents of the first and second memory address still match, then a fault condition associated with the address line is identified.

Abstract: An error reporting and correcting method applied to a peripheral. The peripheral can be connected to the user terminal via the network. In the error reporting and correcting method, an error record file is generated immediately after an error operation occurs to the peripheral. The error record file is uploaded via the network by the user host, and a correction program corresponding to the error file is downloaded to the user host via the network. After being downloaded, the correction program for automatically performing error correction is automatically installed in the user host.

Abstract: A scheme for monitoring links in a point-to-point architecture computer system is discussed. The scheme monitors labels for transactions to determine if they have been reissued within a user selected time window. A corresponding position in a register is updated to reflect the value of the transaction identifier. Subsequently, after the expiration of a counter, the corresponding position in the registers is compared to other predetermined positions in other registers to determine if the transaction identifier has been used (reissued). Otherwise, a possible hang condition might have occurred.

Abstract: A method utilizes targeted boot diagnostics in connection with a boot operation to automate the handling of hardware failures detected during startup or initialization of a computer. In particular, in response to detection of a failure after initiation of and during performance of a boot operation, a targeted diagnostic operation is initiated on at least one hardware device in the computer in response to detecting the failure, such that after the targeted diagnostic operation is initiated, the boot operation may be completed.

Abstract: A method based on a circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package pin, the pad management circuit couples the first data signal as the second data signal and couples the first output enable signal as the second output enable signal. When the configuration signal indicates the I/O pad is to be left unconnected, the pad management circuit asserts the second output enable signal and generates the second data signal having a predetermined value.

Abstract: A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

Abstract: An apparatus, system, and method are disclosed for autonomously overriding a global resource lock. The apparatus includes a determination module, an override module, and an assertion module. The determination module determines whether a global resource lock is owned by a peer resource controller and that the peer resource controller is offline in response to the peer resource controller owning the global resource lock. The atomic module atomically overrides ownership of the global resource lock from the peer resource controller. The assertion module asserts active ownership of the global resource lock. The apparatus, system, and method provide an autonomous override of the global resource lock, minimizing system downtime and user intervention.

Abstract: An apparatus, method and program product provide access for a host device to a shared resource via a spare adapter configured to replace any of a plurality of access adapters.

Abstract: A integrated circuit (IC) implementation of a protection circuit detects and resolves a fault on a bus, such as a stuck-low condition on an I2C bus. The circuit includes logic that detects a fault condition caused by the slave device, e.g. when one or both lines are low for a period longer than a timeout value in the I2C example. Upon detecting the fault condition, the logic disconnects the slave device from the data line and the clock line, for example by activation of switches incorporated in the IC. This typically frees the bus for use by other devices. The logic may also send the slave device one or more clock signals to clear the fault and/or a stop bit when the fault clears to reset the data register in the slave device.

Abstract: A system, device and method are described that provide dynamic calibration of high-speed systems, such as high-speed DDR memory systems. In accordance with certain embodiments of the invention, a DDR controller includes functionality that both initializes settings associated with a data window and dynamically maintains the data window within a defined threshold of operation. In various embodiments, an initial calibration module is provided on the DDR controller for performing a full calibration wherein a data window is initially generated and a center point of the data window is established within a specified threshold. Interrupts may be generated to evaluate the data window and center point and/or recalibrate the data window and center point in response to the evaluation or an interrupt generated from another source, such as a system error or user generated interrupt. If a timer expiration interrupt occurs, the data window and its center point are re-evaluated.

Abstract: A method for debugging a target processor is provided that includes storing a plurality of data values to be sent to the target processor in a first-in first-out (FIFO) buffer unit, saving a copy of an address in a read address counter of the FIFO buffer unit, wherein the address is that of an initial data value of a sequential portion of the plurality of data values, performing a transfer operation to send the sequential portion to the target processor, wherein the read address counter is incremented as each data value is sent. The method also includes resetting the read address counter with the copy of the address if the transfer operation fails and performing the transfer operation again.

Abstract: A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training sequence when the received data are in the training sequence, and shifting the alignment point by reflecting an addition or a removal of a skip symbol on the received data through each of the four lanes when the received data are not in the training sequence. Therefore, the byte skew of the PCI Express bus may be effectively compensated for despite the addition or the removal of the skip symbol.

Abstract: A system for verifying the validity of assembled PCI devices of a computer includes: a device database (2) for storing data of PCI devices being inserted in PCI slots of a computer; a slot database (3) for storing PCI slot data of the computer; a data checking module (1) for obtaining the computer's PCI device data and PCI slot data from the device database and the slot database, integrating the PCI device data and PCI slot data, generating configuration data of a PCI device, and determining whether the PCI device is assembled with validity. A method for verifying the validity of assembled PCI devices of a computer is also disclosed.

Abstract: An error reporting and correcting method applied to a peripheral. The peripheral can be connected to the user terminal via the network. In the error reporting and correcting method, an error record file is generated immediately after an error operation occurs to the peripheral. The error record file is uploaded via the network by the user host, and a correction program corresponding to the error file is downloaded to the user host via the network. After being downloaded, the correction program for automatically performing error correction is automatically installed in the user host.

Abstract: A storage system in which a plurality of storage devices are connected by a pair of loops, disconnects a faulty storage device. The faulty storage device is disconnected from said loops by using, in conjunction, a first disconnect mode, in which a disconnect instruction is issued to a device control unit via a first path which connects controllers and device control units, and a second disconnect mode, in which a disconnect instruction is issued to a device control unit via a second path which connects loops connecting the plurality of storage devices, storage devices, and device control units. Even when a pair of connection ports of a storage device is abnormal, and even when the first path is abnormal, the faulty storage device can be disconnected reliably.

Abstract: An information storage device is disclosed (such as a disk drive) comprising an interface for connecting to a host through a cable, and control circuitry for communicating with the host over the cable by executing a communication process. The communication processes comprises the steps of transmitting a communication request to the host over the cable and waiting to receive a response from the host over the cable. A cable loss event is logged if the host fails to respond after executing the communication process at least twice. Performing the communication process multiple times before logging a cable loss event helps ensure a communication failure is actually due to a faulty cable connection.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: A streaming direct memory access (DMA) engine is disclosed. The streaming DMA engine includes several power reduction capabilities. A controller throttles the DMA engine according to the system throughput requirement and the system processor operation state. The DMA engine holds off a new read request to the memory if the data present in the DMA engine requires retransmission. The DMA engine holds off a new write request to the memory if the data present in the DMA engine is corrupted, until the corrupted data is discarded.

Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: Ethernet capability of a device under test is tested. A diagnostic tool is connected to the device under test. Menus displayed by the diagnostic tool are used to select an Ethernet test. The diagnostic tool discovers network settings of the device under test. Then the diagnostic tool configures an Ethernet connection between the diagnostic tool and the device under test.

Abstract: Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.

Abstract: A system and method to test a host bus adapter's (“HBAs”) ability to handle stream of invalid characters is provided. A data presenter module presents data to a HBA without being aware of a data format. A data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations. A bit offset change module changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters.

Abstract: Method, system and computer program product for protecting the integrity of data transferred between an input/output bus of a data processing system and an external network. A method for protecting the integrity of data transferred between an input/output bus and a network includes generating a Cyclic Redundancy Check (CRC) value on an interface between the input/output bus and an adapter for data being transferred from the input/output bus to the network, and checking a CRC value on the interface between the input/output bus and the adapter for data being transferred from the network to the input/output bus. By adding a CRC generator and a CRC checker on the interface between the input/output bus and the adapter, end-to-end data integrity protection is provided for data transferred between the input/output bus and the network.

Abstract: A system and method enables a file server, to support multi path input/output operations for Fibre Channel devices. Upon each Fibre Channel Arbitrated Loop initialization event generated, the system and method updates a path and device instance to track multiple paths to a given device. While the file server is attempting input/output operations, the failure of a given path can be corrected by the use of another path associated with a given device. The data structures generated by the low levels of the storage operating system are exposed for use by upper level services for routing a storage device identification purposes.

Abstract: A self-reparable semiconductor comprises first, second and spare functional units including first and second sub-functional units that cooperate to perform first and second functions. The first and second sub-functional units of the first, second and first spare functional units are functionally interchangeable, respectively. At least one of the first and second sub-functional units of the first functional unit at least one of receives and outputs an analog signal and includes an analog circuit. Switching devices communicate with the first and second sub-functional units of the first, second and first spare functional units and replace at least one of the first and second sub-functional units of at least one of the first and second functional units with at least one of the first and second sub-functional units of the first spare functional unit when the at least one of the first and second sub-functional units is non-operable.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM, and a 28 bit 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: A storage controlling apparatus controlling an access, for example, from a host to a physical device has a determining means determining whether or not a basic mode predetermined among two or more modes agrees with a mode set in a mode setting sequence run when the apparatus is reset or when data is transferred between modules, and a notifying means determining that transfer mode abnormality occurs when the determining means determines that the two modes do not agree with each other and sending an error notice. Whereby, a data transfer status in a mode differing from the basic mode can be detected as transfer mode abnormality, and the transfer mode abnormality can be solved.

Abstract: A method and apparatus for detecting and in some cases recovering from errors in a source synchronous bus. One embodiment of a disclosed apparatus includes a plurality of strobe inputs to receive a plurality of strobe signals. A plurality of data inputs receive a plurality of data signals transmitted in a source synchronous manner in conjunction with the strobe signals. Bus control logic produces an externally visible indication that an error has occurred if a glitch on one or more of the plurality of strobe signals is detected.

Abstract: The subject invention facilitates the efficient operation of the disassembly of the microprocessor bus by providing an apparatus and method for detecting and correcting a strobe phase inversion and predrive filtering in a 2× source synchronous data transfer bus. Apparatus according to the subject invention detects a data strobe inversion in a source synchronous 2× data bus and corrects for this inversion by reordering the received data as well as filtering predrive effects in real time. Specifically, this apparatus according to the subject invention monitors bus traffic in a multiprocessor environment and correctly captures all double data rate exchanges regardless of the source IC or destination IC in the system.

Abstract: Many computing system environments require continuous availability and high operational readiness. The ability to find, diagnose, and correct actual faults and potential faults in these systems is a high priority. By combining a continually updated database of computing system performance with the ability to analyze that information to detect faults and then communicating that fault information to correct the fault or provide appropriate notification of the fault results in achieving the goals of high availability and operational readiness. FIG. (1) shows how the data collectors, fault detectors and policy actions are combined to meet those goals.

Abstract: In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector to detect a hard failure of the interconnect if the retry is unsuccessful, and a transmission width reducer to reduce a transmission width of the interconnect in response to the hard failure detector. Other embodiments are described and claimed.

Abstract: A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subsystems. The subsystems may be comprised in the data acquisition device or may be external to the data acquisition device. The real-time monitoring circuit may receive a plurality of timing signals from the plurality of subsystems and may select a control loop timing signal out of the plurality of timing signals. The real-time monitoring circuit may determine whether the operations of the control loop are performed within a particular period of time by monitoring the control loop timing signal and communicating with the processing unit. In response to an error notification, the processing unit may take appropriate action, such as shutting down the system and/or reporting an error or warning.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: A method is provided for transmitting messages between bus users that are each linked with a communication bus for the purpose of exchanging messages and with a diagnostic device for detecting the failure of the communication bus. In a diagnostic operation mode that is different from the normal operation mode, the bus user receiving the message is requested by the diagnostic device to output the message to the communication bus, thereby diagnosing a message transmission between two bus users.

Abstract: In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.

Abstract: An apparatus, program product and method utilize targeted boot diagnostics in connection with a boot operation to automate the handling of hardware failures detected during startup or initialization of a computer. In particular, in response to detection of a failure after initiation of and during performance of a boot operation, a targeted diagnostic operation is initiated on at least one hardware device in the computer in response to detecting the failure, such that after the targeted diagnostic operation is initiated, the boot operation may be completed.

Abstract: A system and method for diagnosing faults in a communication network using a distributed alarm correlation system. The alarm correlation system may include node-level alarm correlation tools (ACTs) located at nodes in the network to provide node-level alarm correlation producing node-level correlation results. The node-level ACTs may share diagnostic knowledge with other node-level alarm correlation tools at other nodes. Each of the node-level ACTs may also share the diagnostic knowledge and the node-level correlation results with a higher-level ACT. The higher-level ACT may provide higher-level alarm correlation to produce higher-level correlation results.

Abstract: Methods and apparatus are provided for a fail-operational global time reference for a synchronous redundant data bus including multiple pluralities of timing servers cross-coupled between a plurality of buses in said redundant synchronous data bus system, the apparatus comprising each said timing server of the multiple pluralities of timing servers configured to transmit, receive, and monitor synchronization signals, to store a unique constant, and to independently and automatically select as timing master one or more timing servers from among the multiple pluralities of timing servers based on said synchronization signals received from one or more of said timing servers of said multiple pluralities of timing servers and further based upon a relationship among said unique constants stored in each timing server. Methods comprising selection protocols are also provided.

Abstract: One embodiment disclosed relates to a node system of a high-availability cluster. The node system includes at least a first register and an output port. The first register stores multi-state status data of the node, and the output port sends signals representing this multi-state status data. The multi-state status data includes at least one degraded state. The node system may also include a second register and an input port. The input port receives signals representing the multi-state status data of another node. The second stores this multi-state status data from the other node. Another embodiment disclosed relates to a method of status reporting for a node of a cluster. A set of rules is applied to determine current multi-state status of the node. The states of the multi-state status including a good state, a bad state, and at least one degraded state.