Abstract: Systems and methods for automatically or remotely rendering a solar array safe during an emergency or maintenance. A watchdog unit is disclosed for monitoring a signal from a central controller. If the signal is lost, interrupted, or becomes irregular, or if a shutdown signal is received, then the watchdog unit can shut down one or more solar modules. Shutting down a solar module can mean disconnecting it from a power bus of the solar array or lowering the solar module voltage to a safe level.

Abstract: In one embodiment, a device includes an interface to send and receive packets of network flows, and processing circuitry to track a connection status of each of the network flows, selectively assign some network flows of the network flows having a non-terminated connection status to a flow aging process based on a statistical model of connection termination, operate the flow aging process to identify idle network flows of the some network flows, and release resources associated with the idle network flows.

Abstract: Methods and systems for communication management are disclosed. A computing device may receive a computing request. The computing device may determine a timeout parameter associated with the computing request. A notification may be sent if the timeout parameter is predicted to be exceeded or if the timeout parameter is exceeded.

Abstract: A hardware-assisted paravirtualized hardware watchdog is described that is used to detect and recover from computer malfunctions. A computing device determines that a hardware-implemented watchdog of the computing device does not comply with predetermined watchdog criteria, where the hardware-implemented watchdog is configured to send a reset signal when a first predetermined amount of time elapses without receipt of a first refresh signal. If the hardware-implemented watchdog does not comply with the predetermined watchdog criteria, a runtime watchdog service is initialized using a second predetermined amount of time. The runtime watchdog service is directed to periodically send the refresh signal to the hardware-implemented watchdog before an expiration of the first predetermined amount of time that causes the hardware-implemented watchdog to expire.

Abstract: After an installation of an apparatus, although a state confirmation is necessary, if a display having a high display capability is mounted to the apparatus to facilitate checking, the apparatus becomes large. Further, although it is considered that a terminal such as a personal computer is connected to an apparatus to display state information, when the apparatus is installed in a high place or a narrow gap, the connection is difficult. An apparatus is provided which includes a storage unit that stores state information on a plurality of types of states, a switching unit that switches a to-be-output state from among the plurality of types of states in response to receiving a switching operation by a user, an identification information output unit that outputs a first indication for identifying a type of a to-be-output state, and a state information output unit that outputs state information on a to-be-output state.

Abstract: The present disclosure provides a mobile terminal and a system for controlling a laser projector. The system includes a first drive circuit, a second drive circuit, a watchdog timer, a microprocessor, and an application processor. The first drive circuit is configured to output an electrical signal to the laser projector. The second drive circuit is configured to supply power to the first drive circuit. The microprocessor is configured to send a first predetermined signal to the watchdog timer. The application processor is configured to send a second predetermined signal to the watchdog timer. The watchdog timer is configured to power off the second drive circuit, in response to that the watchdog timer does not read the first predetermined signal or the second predetermined signal.

Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.

Abstract: The present disclosure provides a mobile terminal and a system for controlling a laser projector. The system includes a first drive circuit, a second drive circuit, a microprocessor coupled to the first drive circuit, and an application processor. The first drive circuit is configured to output an electrical signal to the laser projector. The second drive circuit is configured to supply power to the first drive circuit. The application processor is configured to, read a preset signal from the microprocessor, and power off the second drive circuit to power off the first drive circuit and the laser projector, or send a reset signal for restarting the microprocessor to the microprocessor, in response to that the application processor cannot read the preset signal.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for outputting information. A specific embodiment of the method comprises: connecting a database, in response to receiving a request for detecting the database; performing a write operation on a heartbeat table in the database, in response to detecting the connection with the database being normal; performing a read operation on the heartbeat table in the database, in response to detecting the write operation for the heartbeat table being abnormal; performing on the database an operation of writing a file to a hard disk, in response to detecting the read operation on the heartbeat table being normal; and outputting first information for representing a cause of a database failure, in response to detecting the operation of writing the file to the hard disk being abnormal. This embodiment improves the accuracy of the detection on the database failure.

Abstract: A method and a device for processing a communication path are provided. The method includes: obtaining a path processing parameter from local configuration information or from a control layer device, obtaining path information and/or a restarting counter parameter from the control layer device; increasing a path with an opposite-end device when the path information is of increasing a path, identifying the state of the path and/or the state of the opposite-end device using the path processing parameter and/or the restarting counter parameter the opposite-end device; reporting the fault state of the path and/or the reset state of the opposite-end device to the control layer device when the path fails and/or the opposite-end device is reset, releasing sessions on the failed path and/or on a path connected with the reset opposite-end device.

Abstract: Embodiments of the present disclosure provide a system for controlling a camera component, the camera component is applicable for an electronic device, and the system may include a first processing unit and a target processing unit. The target processing unit is configured to control the camera component. The first processing unit is configured to determine whether the target processing unit writes data to the first processing unit in accordance with a preset time interval, and when the target processing unit does not write data to the first processing unit over the preset time interval, change an operating state of the camera component and/or control the electronic device to restart.

Abstract: An electro-phoretic display including a display panel and a driving circuit. The display panel is configured to display image frames. The driving circuit is coupled to the display panel. The driving circuit is configured to drive the display panel to display the image frames according to a driving signal. The driving signal includes a first pulse and a second pulse. A driving period of the driving signal includes a first stage, a second stage and a driving stage in sequence. The first pulse is located before the driving stage, and the second pulse is located in the second stage. The pulse width of the first pulse is larger than that of the second pulse. In addition, a driving method of an electro-phoretic display is also provided.

Abstract: A computer system manages multi-stage transactions. A plurality of response time values of transaction components for a plurality of transactions are received. Two or more transactions from the plurality of transactions are selected, wherein a quantity of the selected transactions is equal to a number of the transaction components in the plurality of transactions. Eigenvalues are calculated from the response time values for the selected transactions. The selected transactions are determined to have timed out by processing the eigenvalues using a machine learning classifier. Embodiments of the present invention further include a method and program product for managing multi-stage transactions in substantially the same manner described above.

Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.

Abstract: Techniques for configurable compute instance resets are described. A user can issue a request to securely reset one or more compute instances implemented within a service provider system. Each compute instance is reset to a previous point in time, such that any activity of the compute instance or effects thereof occurring since that point in time are completely eliminated. Each compute instance reset can include removing an existing volume of the compute instance, obtaining a volume, attaching the obtained volume to the compute instance, and rebooting the compute instance. Configuration data of the compute instance, such as an instance identifier or network addresses, can be maintained after the reset.

Abstract: Aspects of the disclosure provide a data storage device that includes a non-volatile memory and a controller. The controller includes a memory and a processor. The processor is configured to determine whether there is a deadlock in a communication link between the data storage apparatus and a host; and transmit, when there is a deadlock in the communication link between the data storage apparatus and the host, a recovery command to the host to re-establish a link layer connection between the data storage apparatus and the host.

Abstract: Described herein is a technology for account for messages or data that are not read by a receiver unit in a device. A sender unit collects data from a data source, which is passed on stored in an inter-processor communication (IPC) module. The receiver unit receives the data from the IPC module, while the sender unit predicts an expected time that that receiver unit will read the data and whether the receiver unit will actually read the data.

Abstract: Methods and apparatus for post data synchronization in live migration of domains. Host devices on a network may implement virtual machines (VMs) as domains in an execution environment, and may provide local persistent storage for data of the VMs. A migration technique for moving a domain including the persistent data from one host device to another host device is described in which the VM is instantiated on the target device, and the domain is switched to the target device. Synchronization of the VM's data from the persistent storage on the source device to the target device is then initiated, for example according to a distributed replicated storage technique that makes the target device's persistent storage the primary storage and the source device's persistent storage the secondary storage for the VM. Once the data is synchronized, the VM and its respective storage on the source device are released.

Abstract: Optimizing synchronization of enterprise content management systems is described. A system identifies multiple synchronization intervals corresponding to multiple synchronization tasks. The system estimates multiple execution times corresponding to the multiple synchronization tasks. The system calculates multiple remaining times corresponding to the multiple synchronization tasks, wherein the multiple remaining times are based on the multiple synchronization intervals corresponding to the multiple synchronization tasks minus the multiple execution times corresponding to the multiple synchronization tasks. The system orders the multiple synchronization tasks for execution based on corresponding multiple remaining times, from a lowest remaining time to a highest remaining time.

Abstract: The aim of the present disclosure is to provide a watchdog timer that can perform a fault diagnosis during the actual use of a semiconductor device. In a semiconductor device provided with a watchdog timer, the watchdog timer includes a counter; a counter control circuit that changes a count value of the counter to a desired value in the refresh period of the count value; and a fault diagnosis module. The fault diagnosis module includes a suppressing circuit that suppresses generation of a reset signal to the exterior of the watchdog timer in the refresh period; and a holding circuit that holds the reset signal.

Abstract: Disclosed is a peer and an operation method of the peer, the method including receiving, from a partner peer, buffermap timetable (BTT) information associated with a buffermap of the partner peer, verifying whether a difference value between a forced delay and time information of the peer corresponds to the BTT information, requesting, when the difference value corresponds to the BTT information, a fragment of a fragment number corresponding to the difference value from the partner peer, and deriving, when the difference value does not correspond to the BTT information, the fragment number based on the BTT information.

Abstract: The invention pertains to a control device (1) for a computer (10) for an automotive vehicle, said control device (1) being able to cooperate with the computer (10) to perform a plurality of functions, said control device (1) comprising: a command module (20); a reinitialization module (30), adapted to reinitialize said command module (20) for a duration of reinitialization less than a predetermined maximum duration of reinitialization, and a monitoring module (40), adapted to dispatch a reinitialization signal to said reinitialization module (30) should a malfunction be detected, the control device (1) being noteworthy in that the command module (20) comprises a sub-module of at least one temporarily interruptible function (23), said at least one temporarily interruptible function (23) exhibiting a permitted maximum duration of interruption greater than said predetermined maximum duration of reinitialization.

Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract: A microprocessor comprises a timer capable of resetting the device and a plurality of hardware registers (4) arranged logically so that a collective predetermined state of the registers (4) prevents the device from resetting. The device further comprises software (2) with a plurality of functions arranged to place said registers (4) in said predetermined state if each of said functions has executed properly.

Abstract: A method includes receiving a data signal over a multi-input multi-output (MIMO) channel. The method further includes equalizing the data signal, by an adaptive equalizer circuit having an associated target, to provide an equalized output of the data signal. As part of the method, taps of the equalizer circuit and coefficients of the target are estimated. A constraint is imposed on the coefficients of the target as part of the estimation of the coefficients of the target. A similar minimization process is used with constraint imposed on whitening filter taps associated with a DDNP detector in the MIMO channel.

Abstract: A redundant system is provided with a redundant failure detection configuration, and thereby is enabled to precisely detect a failure occurrence, and reliably execute a necessary system switching operation. In a redundant system 10, each of power supply mechanisms 200 for computers 150, 180 redundantly provided includes a processor 204 configured to: monitor a write process in which predetermined information from another apparatus 300 or another mechanism 112 of the corresponding computer 150 or 180 is written to a storage 201 of the power supply mechanism 200; execute an operation of powering off or resetting a power supply device 230 if the write process is not in conformity with a predetermined rule; and after the execution of the operation, give an instruction to perform a fail-over operation to the other computer out of the computers 150, 180.

Abstract: There is provided a drive control apparatus that can maintain a drive control system to be in a safe state even in a case where operational abnormality of avoiding a normal reset of a control processor or operational abnormality of avoiding solution even after resetting the control processor occurs in the control processor. The control processor includes an actuator control processing unit configured to generate a control signal for a drive circuit being a control target apparatus and an actuator, and a diagnosis processing unit configure to diagnosing the actuator control processing unit. The diagnosis processing unit cyclically outputs a reset signal to WDT in a case where the operation of the control processor is normal. The WDT continuously outputs a cutoff signal for cutting off a supply of the control signal from the control processor to the control target apparatus when the cyclic reset signal stops.

Abstract: Systems and methods for processing custom structured tags at a self-service terminal are disclosed. Custom structured tags received by a self-service terminal can include information to identify one or more devices attached to the terminal and identify one or more types of data to be obtained from a user by use of the attached devices. In some embodiments, a browser can natively interpret the custom structured tags. The self-service terminal can also be configured to receive and decode structured tags identifying or more actions to be performed by the device, such as printing a transaction record or dispensing currency.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: Disclosed are a method, a device, and a computer readable storage medium for detecting and processing a system fault. The method includes: an interrupt service routine sending a first stage kicking dog signal, and receiving a second stage kicking dog signal for a system detection task (S101); and when task dead loop or task abnormity is detected, performing system abnormity processing according to a preset processing policy, wherein when the interrupt service routine fails to receive the second stage kicking dog signal within a set period of time, the interrupt service routine stops sending the first stage kicking dog signal, and the system reboots (S102).

Abstract: A load control backup signal generating circuit for supplying a backup control signal to a switch of a load connected to an output of a control processor in a case that abnormality occurs in the control processor, includes a first input terminal that receives a constant period signal that is output periodically from the control processor when the control processor is normal, a constant period signal monitoring section that monitors a state of the constant period signal for identifying whether a length of the time during which a high or low level state of the constant period signal continues is longer than a predetermined time, and that outputs the signal corresponding to a result of the identification, and a backup signal output section that outputs the backup control signal when the output of the constant period signal monitoring section satisfies a predetermined condition.

Abstract: A method begins by a computing device sending a set of redundant dispersed storage error encoding write requests regarding a data object to a set of dispersed storage (DS) processing modules. The method continues with the set of DS processing modules dispersed storage error encoding the data object to produce a group of pluralities of sets of encoded data slices. The method continues with a set of storage units temporarily storing the group of pluralities of sets of encoded data slices. The method continues with the set of storage units permanently storing encoded data slices of the group of pluralities of sets of encoded data slices based on successful execution of a storage verification process to produce a plurality of sets of encoded data slices.

Abstract: An adaptive duo-gate MOSFET includes a trench MOSFET and an adaptive element. The trench MOSFET includes a source, a drain, a first gate, a second gate, and a dielectric layer between the first and second gates. Herein, the first gate may generate charge-coupling in blocking operation, and the second gate may form channel in the trench MOSFET when in conduction operation. The adaptive element is electrically coupled to the first gate, the second gate, and the source respectively. When a potential difference between the second gate and the source is larger than a predetermined value, the first gate and the source are electrically disconnected and then the first gate and the second gate are electrically connected. After a predetermined time, the first gate and the second gate are electrically disconnected and then the first gate and the source are electrically connected.

Abstract: The present disclosure provides system and method embodiments for a status register comprising a plurality of bits, where each of the plurality of bits of the status register is associated with one of a plurality of entities. A trigger mechanism is configured to write a trigger data pattern to the status register, where the trigger data pattern comprises a first state value for each of the plurality of bits of the status register. A capture mechanism is configured to write a second state value to each bit of the status register that is associated with an entity that is presently associated with a first type of entity status information, in response to a detection that the trigger data pattern is written to the status register.

Abstract: In accordance with one aspect of the present description, an integrated circuit die has a plurality of through-body-vias and a testing circuit on board the die which allows charges on a first and second through-body-via to redistribute between them to provide an indication whether one or both of the first and second through-body-vias has a defect. Other aspects are described.

Abstract: A network-based appliance includes a mechanism to erase data on the appliance's local storage. The appliance's normal system reset operation is overridden to enable a local user to place the appliance into a safe mode during which remote erasure of the storage is permitted, provided that mode is entered within a first time period following initiation of a system reset. If the appliance is placed in the mode within the time period, it can then receive commands to wipe the local storage. Once the safe mode is entered by detecting one or more actions of a local user, preferably the appliance data itself is wiped by another person or entity that is remote from the device. Thus, physical (local) presence to the appliance is necessary to place the device in the safe mode, while non-physical (remote) presence with respect to the appliance enables actual wiping of the storage device.

Abstract: A watchdog timer including a first register that stores a first overflow time, a second register that stores a second overflow time, a detector and a counter that continues to count a clock signal to the first overflow time. When the detector detects an execution of a program for a flash memory, the counter clears a count value and continues to count the clock signal to the second overflow time.

Abstract: A system and method for programming a memory device with debug data upon a system failure is disclosed herein. For example, the system can include a timer device, a buffer, a register, and a memory device. The buffer can be configured to receive debug data. The register can be configured to receive memory address information. Also, the memory device can be configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero. Further, the system can include a processing unit configured to provide the timer value to the timer device and the memory address information to the register.

Abstract: A method automatically recovers from a fault situation in a production plant and provides production resources and a manufacturing execution system having a production modeler for modeling the production resources into a plant model and a production scheduler to schedule operations of the modeled production resources. A production controller executes the production process and a fault manager detects fault situations and automatically decides a corrective action. A production resource runs an application for the operation of the production resource and a fault analysis agent provides categorized error situations and checks operational data representing the operation of the production resource against the categorized error situations and when, an error situation occurs, forwards an error event to the fault manager. The error events are collected and then analyzed by a neural network system to assign the error event to an error category. A corrective action is executed on the production resource.

Abstract: An apparatus and method for monitoring multiple micro-cores enable one watchdog to monitor a plurality of micro-cores. The multiple micro-core monitoring apparatus includes: a plurality of micro-cores that periodically output clear signals having different pulse waves; and a watchdog that respectively receives the clear signals having different pulse waves so as to determine presence or absence of an error in the micro-cores, and reset an erroneous micro-core.

Abstract: An in-vehicle electronic control device for diagnosing the details of an abnormality of a microcomputer appropriately is provided. A monitoring function for detecting a malfunction by monitoring input/output of a main function of a hardware part and a monitoring function for detecting an abnormality by monitoring the calculating result of a main function in a software part are provided in a microcomputer. The main function to be monitored is implemented with a different structure than the malfunction/abnormality monitoring function. Furthermore, a malfunction processing circuit for monitoring an abnormality of the microcomputer is provided outside the microcomputer.

Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

Abstract: An advantageous watchdog function deduces faulty operation of a graphics processing unit from historical-indicating parameters while also accommodating more active testing performed by an application. When a GPU fault is detected, the example non-limiting technology rapidly resets the GPU during an interframe time so the GPU is ready to process new frame instructions or display lists and avoids missing or skipping further frames.

Abstract: A method and system for generating a heartbeat of a process including at least one machine configured to perform a process cycle consisting of a plurality of timed events performed in a process sequence under an identified condition includes determining the duration of each of the timed events during the process cycle performed under the identified condition, ordering the durations of the plurality of timed events in the process sequence, and generating a heartbeat defined by the ordered durations of a process cycle. The identified condition may be one of a design intent, baseline, learnt, known, current or prior condition. The variance of the heartbeat between a first and at least a second identified condition may be analyzed to monitor and/or control the process or machine. The system may display the process heartbeat information and may generate a message in response to the heartbeat and/or variance thereof.

Abstract: A configurable advertisement count and skew timer in a virtual router can be used to improve the speed with which a backup virtual router assumes the role of master upon the master router's failure. Enhanced VRRP packets having a type other than one may be used to cause MAC address movement from a failed master router to a backup router assuming the role of master router without placing an undue load on other routers in the network, such as by dropping the enhanced VRRP packets having a type other than one without processing the packets in the control plane of a receiving virtual router.

Abstract: Context captured with sensors of an information handling system is applied to selectively lock access to currently unlocked information, with conditions for locking access based upon the context. Nervous states enforce locking of selected information based upon the confidence of the security of the information under sensed external conditions. Increased sensitivity for locking access includes reduced timeouts to a lock command, increased response to sensed conditions, and more rapid response where unlocked access is to sensitive information.

Abstract: Some embodiments of the present disclosure relate to a watchdog timer having an enhanced functionality that enables the watchdog timer to monitor a process flow of the microprocessor on a task-by-task basis that enables a simple output signal to be used to determine if the watchdog timer is malfunctioning. The watchdog timer has a state machine that increments a state variable from an initial value over a watchdog period. A deterministic service request, received from a microprocessor, controls operation of the watchdog timer. The deterministic service request has an indicator of a monitoring operation to be performed, a password, and an estimated state variable. A comparison element determines if the microprocessor is operating properly based upon a comparison of the received password to an expected password and the received estimated state variable to an actual state variable.

Abstract: This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal.

Abstract: Embodiments of the present invention provide a method for implementing a heartbeat service of a high availability cluster, including: writing, by a server, heartbeat counting information to a disk array, where the heartbeat counting information includes a write heartbeat message sequence number, a read peer heartbeat message sequence number, active-standby state information, a heartbeat message, and a heartbeat message length of the server, so that one or more corresponding servers read the heartbeat counting information, in the disk array, of the server; and reading heartbeat counting information, which is written by the one or more corresponding servers to the disk array, of the one or more corresponding servers, and repeating the write operation and the read operation. Correspondingly, the embodiments of the present invention further provide a server, which solves a spit-brain problem, and improves data security.

Abstract: The present invention provides a watchdog apparatus in which a main MCU and a sub MCU are connected by SPI communication, including: a token generating unit which generates a seed value and generates at least two tokens using the seed value; a watchdog signal generating unit which generates a watchdog signal corresponding to the generated token; a signal determining unit which determines whether the generated watchdog signal is in a normal state and thus provides an advantageous effect which may detect an abnormality of the MCU only using a software logic without providing an additional configuration.