Ecc, Parity, Or Fault Code (i.e., Level 2+ Raid) Patents (Class 714/6.24)
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Publication number: 20130227346Abstract: A method for controlling a nonvolatile memory device includes reading a sub stripe including a plurality of sub pages stored in a first region, writing data stored in valid sub pages of the sub stripe to a second region different from the first region, and generating parity data using the data written to the second region and constituting a new sub stripe.Type: ApplicationFiled: September 13, 2012Publication date: August 29, 2013Inventor: Yang-Sup Lee
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Patent number: 8522074Abstract: A method begins by a processing module receiving a first request to store a program. The method continues with the processing module determining first error coding dispersal storage function parameters and encoding a data segment of the program. The method continues with the processing module determining whether a second request to store the program is received. The method continues with the processing module encoding a second data segment of the program in accordance with the first error coding dispersal storage function parameters when the second request is not received. The method continues with the processing module changing the first error coding dispersal storage function parameters based on the another request to produce second error coding dispersal storage function parameters when the second request is received. The method continues with the processing module encoding the second data segment in accordance with the second error coding dispersal storage function parameters.Type: GrantFiled: July 23, 2010Date of Patent: August 27, 2013Assignee: Cleversafe, Inc.Inventors: Timothy W. Markison, Gary W. Grube, S. Christopher Gladwin, Alan E. Holmes, Wesley Leggette, Jason K. Resch
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Publication number: 20130219214Abstract: A RAID data storage system incorporates permanently empty blocks into each stripe, distributed among all the data storage devices, to accelerate rebuild time by reducing the number of blocks that need to be rebuilt in the event of a failure.Type: ApplicationFiled: February 17, 2012Publication date: August 22, 2013Applicant: LSI CORPORATIONInventors: Sumanesh Samanta, Luca Bert, Satadal Bhattacharjee
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Patent number: 8510595Abstract: A controller configures a plurality of solid state disks as a redundant array of independent disks (RAID), wherein the plurality of solid state disks store a plurality of blocks, and wherein storage areas of the plurality of solid state disks corresponding to at least some blocks of the plurality of blocks have different amounts of estimated life expectancies. The controller includes in data structures associated with a block that is to be stored in the storage areas of the plurality of solid state disks an indication that the block includes parity information corresponding to the RAID, wherein parity information comprises information corresponding to an error correction mechanism to protect against a disk failure.Type: GrantFiled: June 14, 2012Date of Patent: August 13, 2013Assignee: International Business Machines CorporationInventors: Andrew Dale Walls, Daniel Frank Moertl
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Publication number: 20130205167Abstract: Methods and systems for two device failure tolerance in a RAID 5 storage system. Features and aspects hereof provide for allocating a spare storage device in the storage system for use with a standard RAID level 5 storage volume to form an enhanced RAID level 5 volume. Additional redundancy information is generated and stored on the spare storage device such that the enhanced RAID level 5 volume is operated by the storage controller so as to survive a failure of up to two of the storage devices of the enhanced volume. The allocated spare storage device may be reallocated by the storage controller for another purpose in which case the storage controller continues to operate the enhanced volume as a standard RAID level 5 volume that can only tolerate a single failure of a storage device of the volume.Type: ApplicationFiled: February 8, 2012Publication date: August 8, 2013Applicant: LSI CORPORATIONInventor: Majji Venkata Deepak
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Publication number: 20130205168Abstract: Embodiments of the invention relate to correcting erasures in a storage array. A read stripe is received from a plurality of n storage devices. The read stripe includes an array of entries arranged in m rows and n columns with each column corresponding to one of the storage devices. The entries include data entries and mr+s parity entries. Each row contains at least r parity entries generated from the data entries according to a partial maximum distance separable (PMDS) code. It is determined that the read stripe includes at least one erased entry, at most mr+s erased entries and that no row has more than r+s erased entries. The erased entries are reconstructed from the non-erased entries, resulting in a recovered read stripe.Type: ApplicationFiled: July 18, 2012Publication date: August 8, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
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Patent number: 8504896Abstract: A method of operating a nonvolatile memory device including a memory cell array having first and second main cells for storing external input data, first spare cells for storing data for error correction code (ECC) processing on the data stored in the first and second main cells and second spare cells for storing data for ECC processing on the data stored in the first and second main cells which involves reading the data stored in the first spare cells, reading the data stored in the second main cells and the data stored in the second spare cells, and performing the ECC processing on the data read from the second main cells using the data read from the first spare cells and the data read from the second spare cells.Type: GrantFiled: May 5, 2010Date of Patent: August 6, 2013Assignee: Hynix Semiconductor Inc.Inventors: Sang Kyu Lee, Seung Jae Chung
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Patent number: 8495417Abstract: The present invention provides a system and a method for utilizing a parity protection module to back up data on striped aggregates. Specifically, the system computes parity data for data stored at a particular location of each of a plurality of constituent aggregates, and stores the parity on one of the constituent aggregates that is a parity owner for that particular location of data. In the event one of the constituent aggregates fails, new data may still be accessed by the system (the striped aggregates), both to write new data, and to read data stored on the failed aggregate. In particular, the parity protection module allows clients to read data from a failed aggregate by running a reverse parity computation, which may also be used to restore the data to the failed aggregate.Type: GrantFiled: January 9, 2009Date of Patent: July 23, 2013Assignee: NetApp, Inc.Inventors: Richard P. Jernigan, IV, Robert Wyckoff Hyer, Jr., Michael L. Kazar, Daniel S. Nydick
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Patent number: 8495464Abstract: Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.Type: GrantFiled: June 28, 2010Date of Patent: July 23, 2013Assignee: Intel CorporationInventors: Henry Stracovsky, Michael Espig, Victor W. Lee, Daehyun Kim
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Patent number: 8489916Abstract: A multi-disk fault-tolerant system, a method for generating a check block, and a method for recovering a data block are provided. The multi-disk fault-tolerant system includes a disk array and a calculation module connected through a system bus, the disk array is formed by p disks, and a fault-tolerant disk amount of the disk array is q; data in the disk array is arranged according to a form of a matrix M of (m+q)×p, where m is a prime number smaller than or equal to p?q; in the matrix M, a 0th row is virtual data blocks being virtual and having values being 0, a 1st row to an (m?1)th row are data blocks, an mth row to an (m+q?1)th row are check blocks. Therefore, during a procedure of generating the check block and recovering the data block in the multi-disk fault-tolerant system, calculation complexity is lowered.Type: GrantFiled: February 3, 2012Date of Patent: July 16, 2013Assignees: Chengdu Huawei Symantec Technologies Co., Ltd., University of Electronic Science and Technology of ChinaInventors: Yulin Wang, Jianye Yao
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Patent number: 8484506Abstract: A redundant array of independent disks level 5 (RAID 5) with a mirroring functionality is disclosed. In one embodiment, a method for adding a mirroring functionality to a RAID 5 includes forming an array using at least three drives for storing data, creating multiple data blocks and a parity for the multiple data blocks based on the data for every (2N?1)th stripe of the array, and generating a mirror image of the multiple data blocks and the parity for the multiple data blocks for every (2N?1)th stripe to its respective 2Nth stripe of the array, where the N is an integer starting from 1.Type: GrantFiled: November 29, 2008Date of Patent: July 9, 2013Assignee: LSI CorporationInventors: Ranjan Kumar, Preeti Badampudi, Shivprasad Prajapati
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Patent number: 8484536Abstract: Methods, systems, and apparatus, including computer program products, featuring generating a plurality of error-correcting code chunks from a plurality of data chunks. The error-correcting code chunks can be used to reconstruct one or more of the data chunks. The data chunks are allocated to a local group of storage nodes. The error correcting code chunks are allocated between the local group of storage nodes and one or more remote groups of storage nodes. Each remote group of storage nodes is allocated one or more unique error-correcting code chunks from the error-correcting code chunks. Any of the error-correcting code chunks not allocated to a remote group of storage nodes are allocated to the local group of storage nodes.Type: GrantFiled: March 26, 2010Date of Patent: July 9, 2013Assignee: Google Inc.Inventor: Robert Cypher
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Publication number: 20130173956Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.Type: ApplicationFiled: December 26, 2012Publication date: July 4, 2013Applicant: STREAMSCALE, INC.Inventor: STREAMSCALE, INC.
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Publication number: 20130173955Abstract: A disk array memory system comprises: a plurality of disks in a disk array for storage of content data and parity data in stripes, content data in a same stripe sharing parity bits of said parity data, each disk having a spare disk capacity including at least some of a predefined array spare capacity, said array spare capacity providing a dynamic space reserve over said array to permit data recovery following a disk failure event; a cache for caching content data prior to writing to said disk array; and a controller configured to select a stripe currently having a largest spare stripe capacity, for a current write operation of data from said cache, thereby to write all said data of said current write operation on a same stripe, thereby to maximize sharing of parity bits per write operation and minimize separate parity write operations.Type: ApplicationFiled: March 15, 2012Publication date: July 4, 2013Applicant: XtremlO LtdInventors: Renen Hallak, Tal Ben Moshe, Niko Farhi, Erez Webman
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Patent number: 8479078Abstract: A distributed storage network generates a plurality of data segments from a data object and stores each of the plurality of data segments as a plurality of encoded data slices generated from an error encoding dispersal function. When the distributed storage network receives a modification request for the data object, it determines a size of the plurality of data segments of the data object from a segment size field and identifies one of the plurality of data segments requiring modification. The identified data segment is reconstructed from the plurality of encoded data slices and modified in accordance with the modification request.Type: GrantFiled: July 19, 2010Date of Patent: July 2, 2013Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Bart Cilfone
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Patent number: 8464096Abstract: A method begins by identifying a data slice requiring rebuilding to produce an identified data slice, wherein the identified data slice is one of a plurality of data slices that constitute a data segment. The method continues by retrieving at least m number of data slices, wherein m data slices of the plurality of data slices enable reconstruction of the data segment, and wherein the at least m number of data slices does not include the identified data slice. The method continues by reconstructing the identified data slice from the at least m number of data slices to produce a rebuilt data slice. The method continues by writing the rebuilt data slice to one of a plurality of data slice servers.Type: GrantFiled: July 25, 2012Date of Patent: June 11, 2013Assignee: Cleversafe, Inc.Inventors: Vance T. Thornton, Jamie Bellanca, Dustin M. Hendrickson, Zachary J. Mark, Ilya Volvovski
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Patent number: 8458515Abstract: A system and method for supporting asynchronous write operations within data storage systems and repairing a failed component within data storage subsystems without interruption of service. A data storage cluster is coupled to a client. The cluster comprises a plurality of data storage locations addressable as rows and columns in an array. Each column of the array comprises a separate computer of a plurality of computers interconnected to each other via a network. A coordinating column corresponding to a particular row receives data from the client for storage in the row and sends an indication of storage completion to the client, in response to forwarding the received data to data storage locations within the row. Although the client receives a write complete status before the data is actually written in corresponding computers, the cluster has sufficient information to complete the write operation even in the event of a column being temporarily offline.Type: GrantFiled: November 16, 2009Date of Patent: June 4, 2013Assignee: Symantec CorporationInventor: Tariq Saeed
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Patent number: 8448019Abstract: A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.Type: GrantFiled: December 17, 2010Date of Patent: May 21, 2013Assignee: Fujitsu LimitedInventors: Yoshiteru Ohnuki, Norihito Gomyo
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Patent number: 8448044Abstract: A method begins by a processing module determining a retrieval threshold for retrieving a set of encoded data slices from a dispersed storage network (DSN), wherein the set of encoded data slices represents data encoded using a dispersed storage error encoding function having a pillar width of “n”, a decode threshold of “k”, and an encoding ratio of n?k>k and wherein the retrieval threshold is in accordance with the encoding ratio. The method continues with the processing module issuing data retrieval requests to the DSN for the set of encoded data slices and receiving encoded data slices of the set of encoded data slices to produce received encoded data slices. The method continues with the processing module decoding the received encoded data slices to recapture the data when a number of received encoded data slices compares favorably to the retrieval threshold.Type: GrantFiled: April 29, 2011Date of Patent: May 21, 2013Assignee: Cleversafe, Inc.Inventors: Greg Dhuse, Ilya Volvovski, Andrew Baptist, Sebastien Vas, Zachary J. Mark
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Patent number: 8448021Abstract: A method for storing data. The method including receiving a request to write data. In response the request, selecting, a RAID grid location in a RAID grid to write the data, writing the data to memory, updating a data structure to indicate that the RAID grid location is filled. The method further includes determining, using the data structure, whether a data grid in the RAID grid is filled, where the RAID grid location is in the data grid and based on a determination that the data grid is filled: calculating parity values for the RAID grid using the data, determining a physical address in persistent storage corresponding to the RAID grid location, writing the data to a physical location in persistent storage corresponding to the physical address, and writing the parity values to the persistent storage.Type: GrantFiled: October 23, 2012Date of Patent: May 21, 2013Assignee: DSSD, Inc.Inventor: Jeffrey S. Bonwick
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Patent number: 8448020Abstract: A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function.Type: GrantFiled: June 15, 2012Date of Patent: May 21, 2013Assignee: Cleversafe, Inc.Inventors: Steven Mark Hoffman, Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Patent number: 8423866Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.Type: GrantFiled: December 18, 2009Date of Patent: April 16, 2013Assignee: SanDisk Technologies, Inc.Inventors: Gautam Ashok Dusija, Jian Chen, Chris Avila, Jianmin Huang, Lee M. Gavens
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Patent number: 8412979Abstract: An apparatus, system, and method are disclosed for data storage with progressive redundant array of independent drives (“RAID”). A storage request receiver module, a striping module, a parity-mirror module, and a parity progression module are included. The storage request receiver module receives a request to store data of a file or of an object. The striping module calculates a stripe pattern for the data. The stripe pattern includes one or more stripes, and each stripe includes a set of N data segments. The striping module writes the N data segments to N storage devices. Each data segment is written to a separate storage device within a set of storage devices assigned to the stripe. The parity-mirror module writes a set of N data segments to one or more parity-mirror storage devices within the set of storage devices. The parity progression module calculates a parity data segment on each parity-mirror device in response to a storage consolidation operation, and stores the parity data segments.Type: GrantFiled: July 13, 2011Date of Patent: April 2, 2013Assignee: Fusion-IO, Inc.Inventors: David Flynn, David Atkisson, Jonathan Thatcher, Michael Zappe
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Patent number: 8407517Abstract: A system comprising a plurality of storage systems, which uses storage devices of multiple levels of reliability. The reliability as a whole system is increased by keeping the error code for the relatively low reliability storage disks in the relatively high reliability storage system. The error code is calculated using hash functions and the value is used to compare with the hash value of the data read from the relatively low reliability storage disks.Type: GrantFiled: April 8, 2010Date of Patent: March 26, 2013Assignee: Hitachi, Ltd.Inventors: Tomohiro Kawaguchi, Akira Yamamoto
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Publication number: 20130073901Abstract: Apparatus and method of storing, retrieving, transmitting and receiving data comprising a) separating the data into a plurality of data elements, b) matching the position of each data element according to its position in the data with a storage location, c) storing each data element at its matched storage location, d) generating parity data from groups of data elements such that any one or more of the data elements within a group may be recreated from the remaining data elements within the group and the parity data for that group, e) generating further parity data from further groups of data elements formed from the same data elements used in step d) in different combinations and f) storing the parity data and further parity data in separate storage locations.Type: ApplicationFiled: February 28, 2011Publication date: March 21, 2013Applicant: EXTAS GLOBAL LTD.Inventors: Iskender Syrgabekov, Yerkin Zadauly, Chokan Laumulin
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Patent number: 8402217Abstract: The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving data to be stored, dividing data into logical data blocks, assigning the blocks to a logical block grouping comprising at least one physical data storage block from two or more of multiple solid state physical memory devices, storing the blocks in physical data storage blocks, determining a code that corresponds to the persisted data, and storing the code that corresponds to the data stored in the logical block grouping. Blocks of damaged stored data may be recovered by identifying the logical data block and logical block grouping corresponding to the damaged physical data storage block, reading the data and the code stored in the identified grouping, and comparing the code to the read data other than the data stored in the damaged block.Type: GrantFiled: September 14, 2010Date of Patent: March 19, 2013Assignee: Marvell International Ltd.Inventor: Gregory Burd
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Publication number: 20130067275Abstract: According to one embodiment, a video server includes an allocator. The allocator allocates resources for performing rebuilding. When processing which needs to be performed in real time is requested during the rebuilding, the allocator determines whether resources for performing the requested processing are available. When resources for performing the requested processing are available, the allocator allocates available resources to the requested processing. When resources for performing the requested processing are not available, the allocator deallocates resources allocated to the rebuilding to secure resources for performing the requested processing, and allocates the secured resources to the requested processing.Type: ApplicationFiled: July 25, 2012Publication date: March 14, 2013Inventors: Hiroyuki Watanabe, Toshiki Mori, Naoko Satoh
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Patent number: 8397101Abstract: Method and apparatus for ensuring a most recent version of data is retrieved from a memory, such as a non-volatile flash memory array. In accordance with various embodiments, a controller is adapted to sequentially store different versions of an addressable data block having a selected logical address in different locations within a memory. The controller assigns a revision indication value to each said version, with at least two of said stored versions concurrently sharing the same revision indication value. In some embodiments, the revision indication value constitutes a repeating cyclical sequence count that is appended to each block, or logically combined with a code value and stored with each block. The total number of counts in the sequence is less than the total number of versions resident in the memory.Type: GrantFiled: June 3, 2010Date of Patent: March 12, 2013Assignee: Seagate Technology LLCInventors: Ryan James Goss, Mark Allen Gaertner
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Patent number: 8392813Abstract: Some embodiments of the invention shift the responsibility for creating parity and error correction blocks from the hardware or software RAID units or modules to the computer system's file system, allowing the file system's existing mechanisms of write atomicity to be used to help ensure consistency of the on-disk information throughout all or increasing portions of the information saving and/or updating cycle.Type: GrantFiled: December 22, 2009Date of Patent: March 5, 2013Assignee: Intel CorporationInventor: David Woodhouse
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Patent number: 8392796Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.Type: GrantFiled: January 30, 2012Date of Patent: March 5, 2013Assignee: Intel CorporationInventors: Kuljit S. Bains, Joseph H. Salmon
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Publication number: 20130055013Abstract: The present invention reduces the amount of rebuild processing and executes a rebuild process efficiently. Multiple storage devices configure a parity group. Of the multiple storage devices, a prescribed storage device in which a failure has occurred is blocked. Each storage device stores management information. The management information manages from among the storage areas of the storage device a prescribed area having data from a higher-level apparatus. A controller determines whether a storage area of the prescribed storage device is the prescribed area based on the management information, and executes a rebuild process with respect to the area determined to be the prescribed area.Type: ApplicationFiled: August 29, 2011Publication date: February 28, 2013Applicant: HITACHI, LTD.Inventor: Toshiya Seki
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Patent number: 8386835Abstract: A computer readable storage medium, embodying instructions executable by a computer to perform a method, the method including: validating a memory write of data segments using a first number of leaf hashes of a first hash tree, where each of the first number of leaf hashes is associated with one of the data segments of a first block size, generating interior node hashes based on the first number of leaf hashes, where each of the interior node hashes is associated with a second block size, generating a first root hash using the interior node hashes, where the first root hash is associated with a remote procedure call size, transmitting the first root rash and the data segments to a network file system, where the transmission is performed using the remote procedure call size, and validating the transmission of the data segments using the first root hash.Type: GrantFiled: May 17, 2010Date of Patent: February 26, 2013Assignee: Oracle International CorporationInventors: Andreas E. Dilger, Eric Barton, Rahul S. Deshmukh
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Patent number: 8386840Abstract: The invention concerns a distributed object storage system (1) comprising a maintenance agent (740) instructing an encoding module (400) to disassemble a repair data object into a specific number of repair sub blocks, this specific number being equal to or greater than said number of missing sub blocks and less then the predetermined number of sub blocks during a regular storage operation.Type: GrantFiled: October 28, 2011Date of Patent: February 26, 2013Assignee: Amplidata NVInventors: Bastiaan Stougie, Frederik De Schrijver, Romain Raymond Agnes Slootmaekers, Kristof Mark Guy De Spiegeleer, Wim De Wispelaere, Wouter Van Eetvelde, Joost Yervante Damad
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Patent number: 8386841Abstract: A computer-implemented method for improving redundant storage fault tolerance may include 1) identifying a plurality of storage devices storing an encoded set of data, with the encoded set of data including a redundant form of an underlying set of data, 2) determining that a subset of the plurality of storage devices have failed, 3) reconstructing encoded data lost due to the failure of the subset of the plurality of storage devices, and then 4) redundantly storing the reconstructed encoded data on the plurality of storage devices. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: July 21, 2010Date of Patent: February 26, 2013Assignee: Symantec CorporationInventor: Dilip Renade
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Patent number: 8386881Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.Type: GrantFiled: May 7, 2012Date of Patent: February 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Kanno, Hironori Uchikawa
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Patent number: 8381077Abstract: Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location.Type: GrantFiled: May 5, 2010Date of Patent: February 19, 2013Assignee: LSI CorporationInventor: Robert W. Warren
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Patent number: 8381025Abstract: A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function.Type: GrantFiled: May 12, 2010Date of Patent: February 19, 2013Assignee: Cleversafe, Inc.Inventors: Steven Mark Hoffman, Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Patent number: 8365039Abstract: In a non-volatile memory that reads a binary value from a storage cell by comparing the voltage level of a stored charge in that cell against a reference voltage, the accumulated errors in a range of memory locations may be analyzed to determined if there are more errors in one direction than the other (for example, more 0-to-1 errors than 1-to-0 errors). If so, the reference voltage may be adjusted up or down so that subsequent reads from that range may produce approximately the same number of errors in each direction. For multiple-bits-per-cell memories, where there are multiple reference voltages for each cell, each reference voltage may be adjusted separately by keeping track of the errors related to that particular threshold.Type: GrantFiled: September 16, 2008Date of Patent: January 29, 2013Assignee: Intel CorporationInventors: Chun Fung Man, Jonathan E. Schmidt
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Patent number: 8352782Abstract: A message is generated by a computer operating on a dispersed data storage network indicating the inaccessibility of a plurality of data slices. A rebuilder application operates on the dispersed data storage grid and rebuilds inaccessible data slices, including those identified by the message.Type: GrantFiled: December 29, 2009Date of Patent: January 8, 2013Assignee: Cleversafe, Inc.Inventors: Vance T. Thornton, Jamie Bellanca, Dustin M. Hendrickson, Zachary J. Mark, Ilya Volvovski
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Patent number: 8352781Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.Type: GrantFiled: July 6, 2009Date of Patent: January 8, 2013Assignee: STMicroelectronics International N.V.Inventors: Akhil Garg, Prashant Dubey
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Patent number: 8352805Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.Type: GrantFiled: April 15, 2009Date of Patent: January 8, 2013Assignee: Rambus Inc.Inventors: Ian Shaeffer, Craig E. Hampel
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Publication number: 20120331338Abstract: Provided is a two-way RAID controlled storage device of a serial attached small computer system interface/serial advanced technology attachment (PCI-Express) type, which provides data storage/reading services through a PCI-Express interface. The RAID controller typically comprises multiple sets of RAID equipment coupled to one another via a hardware host connect, an adaptive host interface controller, a host connect controller, a two-way RAID controller, a disk connect controller, an adaptive disk mount controller, and a hardware disk connect. Coupled to the hardware disk connect are a set of DDR, SSD memory disk units. Further, each set of RAID equipment typically comprises a programmable host interface unit, a disk controller, a high speed host interface, a disk monitoring unit, a disk plug and play controllers, and a programmable disk mount.Type: ApplicationFiled: June 21, 2011Publication date: December 27, 2012Inventor: Byungcheol Cho
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Patent number: 8341425Abstract: Provided is a storage device which partitions data from a host into multiple partitioned data and distributes, encrypts and stores them together with a parity to and in multiple memory mediums. This storage device executes processing of restoring the partitioned data or the parity stored in a memory medium to be subject to encryption re-key based on decrypted data of the partitioned data or the parity stored in each memory medium other than the memory medium to be subject to encryption re-key among the multiple memory mediums, storing the restored partitioned data or the parity in a backup memory medium while encrypting the restored partitioned data or the parity with a new encryption key, and thereafter interchanging the backup memory medium and the memory medium to be subject to encryption re-key so that the backup memory medium will be a memory medium configuring the parity group and the memory medium to be subject to encryption re-key will be the backup memory medium.Type: GrantFiled: May 25, 2009Date of Patent: December 25, 2012Assignee: Hitachi, Ltd.Inventors: Hirotaka Nakagawa, Masayasu Asano, Takeki Okamoto, Nobuyuki Osaki
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Patent number: 8335966Abstract: An efficient RAID-6 double parity erasure code scheme. Efficiency is provided by the addition of a single term to a diagonal parity equation. For example, in a five-wide layout (having five physical storage devices) the RAID-6 “parity diagonals” end up with six terms, which are the actual diagonal plus one more data block. As a result, no one data symbol contributes to the erasure code determined from the data symbols, such that no more than n+1 data symbols contribute to any one parity symbol.Type: GrantFiled: August 3, 2009Date of Patent: December 18, 2012Assignee: Dell Products L.P.Inventors: Richard F. Lary, Damon Hsu-Hung
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Patent number: 8327185Abstract: A method for storing data. The method including receiving a request to write data. In response the request, selecting, a grid location in a grid to write the data, writing the data to memory, updating a data structure to indicate that the grid location is filled. The method further includes determining, using the data structure, whether a data grid in the grid is filled, where the grid location is in the data grid and based on a determination that the data grid is filled: calculating parity values for the grid using the data, determining a physical address in persistent storage corresponding to the grid location, writing the data to a physical location in persistent storage corresponding to the physical address, and writing the parity values to the persistent storage.Type: GrantFiled: March 23, 2012Date of Patent: December 4, 2012Assignee: DSSD, Inc.Inventor: Jeffrey S. Bonwick
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Publication number: 20120304001Abstract: A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.Type: ApplicationFiled: May 24, 2011Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian E. Bakke, Brian L. Bowles, Michael J. Carnevale, Robert E. Galbraith, Adrian C. Gerhard, Murali N. Iyer, Daniel F. Moertl, Mark J. Moran, Gowrisankar Radhakrishnan, Rick A. Weckwerth, Donald J. Ziebarth
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Patent number: 8316258Abstract: A system and method for error detection in a data storage array includes one or more storage medium interconnected with a controller through a network. A data integrity engine in the controller applies a first error detection process to a data object to create one or more data blocks and associated parity codes. First and second error detection processes are applied to detect and repair errors in the data object.Type: GrantFiled: May 3, 2007Date of Patent: November 20, 2012Assignee: Oracle America, Inc.Inventor: James P. Hughes
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Patent number: 8316259Abstract: A method, system and article of manufacture for the storing convolution-encoded data on a redundant array of independent storage devices (RAID) is described. The convolution-encoded data comprises error correction coded data to eliminate the need for parity as used in conventional RAID data storage. The number of storage devices may vary to accommodate expansion of storage capacity and provide on demand storage.Type: GrantFiled: July 15, 2008Date of Patent: November 20, 2012Assignee: International Business Machines CorporationInventors: Daniel James Winarski, Craig A. Klein, Nils Haustein
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Patent number: 8316260Abstract: A method for storing data. The method including receiving a request to write data. In response the request, selecting, a RAID grid location in a RAID grid to write the data, writing the data to memory, updating a data structure to indicate that the RAID grid location is filled. The method further includes determining, using the data structure, whether a data grid in the RAID grid is filled, where the RAID grid location is in the data grid and based on a determination that the data grid is filled: calculating parity values for the RAID grid using the data, determining a physical address in persistent storage corresponding to the RAID grid location, writing the data to a physical location in persistent storage corresponding to the physical address, and writing the parity values to the persistent storage.Type: GrantFiled: July 23, 2012Date of Patent: November 20, 2012Assignee: DSSD, Inc.Inventor: Jeffrey S. Bonwick
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Patent number: 8296515Abstract: One embodiment of the present invention sets forth a technique for performing RAID-6 computations using simple arithmetic functions and two-dimensional table lookup operations. A set of threads within a multi-threaded processor are assigned to perform RAID-6 computations in parallel on a stripe of RAID-6 data. A set of lookup tables are stored within the multi-threaded processor for access by the threads in performing the RAID-6 computations. During normal operation of a related RAID-6 disk array, RAID-6 computations may be performed by the threads using a small set of simple arithmetic operations and a set of lookup operations to the lookup tables. Greater computational efficiency is gained by reducing the RAID-6 computations to simple operations that are performed efficiently on a multi-threaded processor, such as a graphics processing unit.Type: GrantFiled: December 16, 2009Date of Patent: October 23, 2012Assignee: Nvidia CorporationInventors: Nirmal Raj Saxena, Mark A. Overby, Andrew Currid