Abstract: In some embodiments, storage devices, such as a storage drive or a storage node, in an array of storage devices may be reintroduced into the array of storage devices after a period of temporary unavailability without fully rebuilding the entire previously unavailable storage device.

Abstract: A reproduction apparatus includes a reproduction unit reading a reproduced signal of the data recorded on an optical disk, a reproduced signal processing unit performing ECC decoding for the reproduced signal using a predetermined parameter value, a storage unit storing the parameter number associated with the currently set parameter value and a parameter table listing parameter values and associated parameter numbers, and a control unit controlling the reproduction unit and the reproduced signal processing unit. The control unit, when ECC decoding fails, changes the parameter values in the order of the parameter numbers and controls the reproduced signal processing unit until ECC decoding succeeds in retried reproduction processing and, when ECC decoding succeeds, stores the parameter number associated with the currently set parameter value and sets in the next retried reproduction processing the parameter value associated with the stored parameter number in the reproduced signal processing unit.

Abstract: To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.

Abstract: The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.

Abstract: A storage system includes data storage devices, spare storage devices used when a failure occurs in a data storage devices, a group management unit that divides the data storage devices into groups and implements a redundancy, a data storage device restoration unit that assigns the spare storage device as a replacement when a failure occurs, and a configuration change unit changing configuration of the group to which the data storage devices belong. The configuration change unit includes, a spare storage device securing unit that secures the spare storage device, a change processor that writes data concerning the group into the spare storage device, and a change restoration unit that performs continuation of the configuration change, or restoration of the group to a state in a start, using the data written into the spare storage device when the configuration change of the group is interrupted.

Abstract: Systems and/or methods that facilitate that facilitate error correction of data stored in memory components, such as flash memory devices are presented. An optimized correction component can be used to break data into two or more data blocks. The optimized correction component can facilitated creating one or two redundancy blocks that can be associated with the data blocks, wherein data blocks and the redundancy blocks can be assembled into a data stripe that can be stored in three or more of the memory components. Upon retrieval of the data stripe, the optimal correction component, an error correction code (ECC) component or a combination thereof can correct data blocks that contain errors wherein the decision whether the optimized correction component or the error correction code (ECC) component corrects the errors can be based in part on a predetermined criteria.

Abstract: A technique for selecting an erasure code from a plurality of erasure codes for use in a fault tolerant system comprises generating a preferred set of erasure codes based on characteristics of the codes' corresponding Tanner graphs. The fault tolerances of the preferred codes are compared based at least on the Tanner graphs. A more fault tolerant code is selected based on the comparison.

Abstract: A solid state disk device comprises a plurality of nonvolatile memories and a controller. The plurality of nonvolatile memories are electrically connected to a plurality of channels, respectively. The controller controls storing, erasing and reading operations of the nonvolatile memories. The controller divides input data into a number of units corresponding to a number of the plurality of channels and stores the divided input data in the nonvolatile memories through the plurality of channels.

Abstract: A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.

Abstract: A method for rearranging data blocks in a data storage system when adding new storage devices to create an expanded data storage system. A temporary configuration is selected for which the exchange of one or more data blocks between the temporary configuration and the source configuration produces the destination configuration before identifying and exchanging data blocks between the temporary configuration and the source configuration to produce the destination configuration. A single data element transfer chain embodiment provides superior performance in an embodiment that maintains (does not reduce) the source array data storage efficiency at the destination array after scaling. When adding a single new device to an existing array, the required data movement is minimized and does not exceed the capacity of the new device.

Abstract: A method is disclosed of maintaining data. The method includes the steps of providing a plurality of data storage mediums, each comprising a parity bit that provides an indication of the parity of the data in each respective data storage medium, at least one of the data storage mediums providing an exclusive OR function of a parity output bit of the at least one of the plurality of data storage mediums; encoding data provided by the exclusive OR functionality of the parity output bit to provide encoded data; time stamping the encoded data with a time stamp circuit that is coupled to the encoded data to provide time stamped encoded data; and providing the time stamped encoded data to a time-retrieval data storage medium.

Abstract: Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated.

Abstract: The embodiments of the invention provide methods of protecting data blocks while writing to a storage array, wherein storage units in the storage array include write logs. The data protection level of the write logs is equal to or greater than the data protection level of the storage units. Moreover, the write logs have metadata describing contents of the write logs, wherein the metadata include a sequence number identifying the age of the metadata. Each of the data blocks is a member of a parity group having addressable data blocks and first parity blocks. The addressable data blocks have at least one host data block and at least one associated data block.

Abstract: In a method of initializing a computer memory that receives data from a plurality of redrive buffers, a predetermined data pattern of a selected set of data patterns is stored in selected redrive buffers of the plurality of redrive buffers. Each of the selected set of data patterns includes a first initialization data pattern and an error correcting code pattern that is a product of a logical function that operates on the first initialization data pattern and an address in the computer memory. The selected set of data patterns includes each possible value of error correcting code pattern. A redrive buffer of the plurality of redrive buffers that has stored therein an error correcting code pattern that corresponds to the selected address is selected when sending a first initialization data pattern to a selected address. The selected redrive buffer is instructed to write to the selected address the first initialization data pattern and the error correcting code pattern that corresponds to the selected address.

Abstract: Disclosed is a method of calculating parity. The method dividing, by a client system, a file which is to be stored into chunks of a preset size and distributively storing the chunks in a plurality of data servers; sending, by the client system, a data write complete notification message to a metadata server; storing, by the metadata server, a file sent through the data write complete notification message in a recovery queue; and sending, by the metadata server, a random data server a parity calculation request for the file stored in the recovery queue.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: A storage subsystem provides redundancy protection for data associated with files stored in a storage subsystem. A request is received to change the redundancy protection for data associated with at least one of the files, where the request identifies the data for which the redundancy protection is to be changed. The redundancy protection for the data identified by the request is changed, while the redundancy protection for a remainder of the data associated with the files stored in the storage subsystem is maintained unchanged.

Abstract: The present disclosure is directed to a system and method for monitoring drive health. A method for monitoring drive health may comprise: a) conducting a predictive fault analysis for at least one drive of a RAID; and b) copying data from the at least one drive of the RAID to a replacement drive according to the predictive fault analysis. A system for monitoring drive health may comprise: a) means for conducting a predictive fault analysis for at least one drive of a RAID; and b) means for copying data from the at least one drive of the RAID to a replacement drive according to the predictive fault analysis.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device.

Abstract: An encoding system for encoding error control codes may include a first encoder configured to encode an input bit stream to generate first bit streams of C-bits, where c is an integer greater than zero, and a second encoder may be configured to receive the first bit streams and shuffle data of the received first bit streams to generate second bit streams. The data shuffling of the first bit streams may adjust an error distribution of the second bit streams. An encoding method may include encoding an input bit stream to generate first bit streams of C-bits, and receiving the first bit streams and shuffling data of the received first bit streams to generate second bit streams. An error distribution of the second bit streams may be adjusted based on the data shuffling.

Abstract: A flash memory system includes a flash memory for storing input data, and a memory controller controlling the flash memory, wherein the memory controller generates a first error correction code corresponding to the input data, and encrypts the first error correction code, and the flash memory includes a main area for storing the input data and a spare area for storing the encrypted first error correction code.

Abstract: A decoding system comprises an iterative decoder that utilizes parity constraints to iteratively decode a block of data that consists of multiple code words, and a processor that controls the iterative decoder to selectively remove a subset of the parity constraints for a number of decoder iterations and include one or more of the selectively removed parity constraints in other decoder iterations.

Abstract: Embodiments of the present invention provide a method, system, and computer program product for optimizing I/O operations performed by a storage server operating on behalf of multiple clients to access data on a plurality of storage devices (disks). Embodiments of the present invention eliminate the need for selected read operations to write new data to physical data blocks by zeroing the physical data blocks to which new data will be written. Additionally, the need for reading old parity to compute new parity is eliminated. Instead, new parity is computed from the data to be written without the need of old parity or the storage server sends a command to a disk that stores parity. A module implemented at the disk that stores parity executes the command without reading, by the storage server, old parity. Eliminating the need for reading old data and for reading old parity eliminates some rotation latency and improves overall system's performance.

Abstract: Rebuilding lost data in a distributed redundancy data storage system including multiple nodes, is provided. User data is stored as a collection of stripes, each stripe comprising a collection of data strips and associated parity strips, the stripes distributed across multiple corresponding data owner nodes and multiple corresponding parity owner nodes. A data owner node maintains the associated data strip holding a first copy of data, and a parity owner node maintains a parity strip holding a parity for the collection of data strips. Upon detecting a failure condition, the owner node initiates a rebuilding protocol for recovery of lost data and/or parity it owns. The protocol includes reconstruction of lost data or parity by a computation involving data and/or parity from a recovery strip set in a stripe, wherein a recovery strip set contains at least one surviving data or parity strip. The recovery strip set for a lost data strip contains at least one surviving parity strip.

Abstract: A memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to a data-write request information does not match a page size unit, thereby adjusting the size of the write data to the page size unit and then outputs the write data.

Abstract: Various embodiments of the present invention provide fault-tolerant, redundancy-based data-storage systems that rely on disk-controller-implemented error detection and error correction, at the disk-block level, and RAID-controller-implemented data-redundancy methods, at the disk and disk-stripe level, in order to provide comprehensive, efficient, and system-wide error detection and error correction. Embodiments of the present invention use disk-level and stripe-level data redundancy to provide error detection and error correction for stored data objects, obviating the need for certain costly, intermediate levels of error detection and error correction commonly employed in currently available fault-tolerant, redundancy-based data-storage systems.

Abstract: A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller. The link interface comprises first error correction logic integrated in the link interface that performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices. The first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data. Link interface control logic integrated in the link interface controls the transmission of the first data to the set of memory devices.

Abstract: A method and a system is provided for increasing reliability of data stored in storage segments by increasing redundancy data and by permitting user data to fit around defective locations in the storage segment. User data is compressed and reserved for a portion of a storage segment having a data size corresponding to an uncompressed size of the user data. The compressed user data is written to the reserved portion of the storage segment and a pad byte pattern is written to any remaining portion of the reserved portion of the storage segment. The remaining portion of the reserved portion of the storage segment is designated as unused.

Abstract: A method for reconstructing a RAID system is disclosed. Plural disks are corresponded to plural pieces of unique recognition data, where each disk corresponds to one of the recognition data. A disk profile is generated according to the recognition data using a RAID system, wherein the disk profile comprises a logic section combined with the disks and the logic section respectively corresponds to the recognition data of different disks based on stored data in different disks. The disks are mounted to a computer device providing the RAID system. The mounted disks are mapped to correct disk mount addresses according to the disk profile to reconstruct the stored data of the disks in the computer device.

Abstract: A client device or other processing device separates a file into blocks and distributes the blocks across multiple servers for storage. In one aspect, subsets of the blocks are allocated to respective primary servers, a code of a first type is applied to the subsets of the blocks to expand the subsets by generating one or more additional blocks for each subset, and the expanded subsets of the blocks are stored on the respective primary servers. A code of a second type is applied to groups of blocks each including one block from each of the expanded subsets to expand the groups by generating one or more additional blocks for each group, and the one or more additional blocks for each expanded group are stored on respective secondary servers. The first and second codes are advantageously configured to provide security against an adversary that is able to corrupt all of the servers over multiple periods of time but fewer than all of the servers within any particular one of the periods of time.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.

Abstract: A circuit is operated to detect unstable memory cells from among a plurality of memory cells in at least one page. A determination is made from an initial status of data stored in a memory cell whether no read error occurs when the data is read at a standard read voltage level, whether a read error occurs and the read error is correctable, and whether a read error occurs and the read error is uncorrectable. Responsive to determining that a read error occurs that is correctable, a further determination is made as to whether the memory cell is correctable by reading the data stored in the memory cell at a correction read voltage level, which has a different voltage level from the standard read voltage level, and by determining whether a read error occurring in the data read at the correction read voltage level is correctable or uncorrectable.

Abstract: Several methods and a system of a replicated service for write ahead logs are disclosed. In one embodiment, a method includes persisting a state of a distributed system through a write ahead log (WAL) interface. The method also includes maintaining a set of replicas of a WAL through a consensus protocol. In addition, the method includes providing a set of mechanisms for at least one of detection and a recovery from a hardware failure. The method further includes recovering a persistent state of a set of applications. In addition, the method includes maintaining the persistent state across a set of nodes through the hardware failover. In one embodiment, the system may include a WAL interface to persist a state of a distributed system. The system may also include a WAL replication servlet to maintain and/or recover a set of replicas of a WAL.

Abstract: An apparatus comprising a logically contiguous group of at least three drives, a first loop, a second loop, and a compression/decompression circuit. Each of the drives comprises (i) a first region configured to store compressed data of a previous drive, (ii) a second region configured to store uncompressed data of the drive, (iii) a third region configured to store compressed data of a next drive. The first loop may be connected to the next drive in the logically contiguous group. The second loop may be connected to the previous drive of the logically contiguous group. The compression/decompression circuit may be configured to compress and decompress the data stored on each of the drives.

Abstract: Apparatus and associated method that stores first metadata only at the same addressable storage location of a computer readable medium as that where associated first user data is stored, and afterward satisfies a read request for the first user data by retrieving the first user data from the addressable location of the computer readable medium where the first metadata is stored if the first metadata has a first value, and by reconstructing the first user data from other metadata stored at another addressable location of the computer readable medium than where the first metadata is stored if the first metadata has a second value.

Abstract: The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device.

Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes, each node comprising a processor and an array of failure independent data storage devices. Information is stored as a set of stripes, each stripe including a collection of multiple data strips and associated parity strips, the stripes distributed across multiple corresponding primary data nodes and multiple corresponding parity nodes. A primary data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the multiple data strips. A read-modify-write parity update protocol is performed for maintaining parity coherency, the primary data node driving parity coherency with its corresponding parity nodes, independently of other data nodes, in order to keep its relevant parity strips coherent.

Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes. Each node comprises a processor and an array of failure independent data storage devices. Information is stored as a set of stripes, each stripe including a collection of at least a data strip and associated parity strips, the stripes distributed across a primary data node and multiple corresponding parity nodes. A read-other parity update protocol maintains parity coherency. The primary data node for each data strip drives parity coherency with the corresponding parity nodes, independently of other data nodes, in keeping relevant parity strips for the primary data node coherent. A parity value is determined based on data other than a difference between new data and existing data. A new parity value is based on new data and dependent data, wherein with respect to one data value, dependent data comprises other data encoded in a corresponding parity value.

Abstract: A system, method and computer program product for receiving on a non-volatile, solid-state, cache memory system, a data segment, including a plurality of data elements, from one or more of a volatile, solid-state, cache memory system and a non-volatile, electromechanical memory system. The data segment may be stored on the non-volatile, solid-state, cache memory system. Each data element includes one or more data extents.

Abstract: A latency reduction method for read operations of an array of N disk storage devices (210) having n disk storage devices (210A-210H) for data storage and p of disk storage devices (210I, 210J) for storing parity data is provided. Utilizing the parity generation engine's (230) fault tolerance of for a loss of valid data from at least two of the N disk storage devices (210A-210J), the integrity of the data is determined when N?1 of the disk storage devices (210A-210J) have completed executing a read command. If the data is determined to be valid, the missing data of the Nth disk storage device is reconstructed and the data transmitted to the requesting processor (10). By that arrangement the time necessary for the Nth disk storage device to complete execution of the read command is saved, thereby improving the performance of memory system (200).

Abstract: A system, method, and computer program product are provided for providing data redundancy in a plurality of storage devices. In operation, storage commands are received for providing data redundancy in accordance with a first data redundancy scheme. Additionally, the storage commands are translated for providing the data redundancy in accordance with a second data redundancy scheme. Furthermore, the translated storage commands are outputted for providing the data redundancy in a plurality of storage devices.

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract: Embodiments of the present invention provide techniques for distributing the reconstruction process of a failed storage device in an array of storage devices to storage systems in a storage system cluster (cluster). The inventive technique includes a storage system securing the array, decomposing the reconstruction process into a number of tasks, distributing each task to other storage system in the cluster, and reconstructing data using results of the tasks performed by the other storage systems.

Abstract: A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises first error correction logic provided in write logic integrated in the memory hub device. The memory hub device comprises second error correction logic provided in read logic integrated in the memory hub device. The first error correction logic and the second error correction logic performs error correction operations on data transferred between a link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.

Abstract: A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices. The memory hub device also comprises first error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices. The memory hub device also comprises second error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: Monitoring and repairing memory includes selecting a first memory bank comprising a plurality of memory cells to analyze. The plurality of memory cells are copied from the first memory bank to a second memory bank, wherein a request to access the first memory bank is redirected to the second memory bank. A determination is made whether the first memory bank comprises an error of the memory cell.

Abstract: A NAND flash memory and method for managing data reads a header from each storage area, and identifies each storage area. Data of the primary storage area is updated if the primary storage area exists, and an operating system in the NAND flash memory is initiated according to the updated data in the primary storage area, or in the secondary storage area if the primary storage area does not exist but a secondary storage area does.

Abstract: A method, system, apparatus, and computer-readable medium are provided for storing data at a virtual tape library (“VTL”) computer or server. According to one method, a VTL computer maintains one or more storage volumes for use by initiators on an array of mass storage devices. Space on each of the volumes is allocated using thin provisioning. The VTL computer may also include a cache memory that is at least the size of a full stripe of the array. Write requests received at the VTL computer are stored in the cache memory until a full stripe of data has been received. Once a full stripe of data has been received, the full stripe of data is written to the array at once. The array utilized by the VTL computer may include a hot spare mass storage device. When a failed mass storage device is identified, only the portions of the failed device that have been previously written are rebuilt onto the hot spare. The array may be maintained using RAID-5.