Abstract: A method begins by a dispersed storage (DS) processing module receiving a request to store data in a dispersed storage network and determining dispersed storage error encoding parameters for encoding the data into sets of encoded data slices. The method continues with the DS processing module determining whether the request includes a desired write reliability indication. When the request includes the desired write reliability indication, the method continues with the DS processing module determining whether storage of the sets of encoded data slices is meeting the desired write reliability indication. When storage of a set of encoded data slices is not meeting the desired write reliability indication, the method continues with the DS processing module determining a storage compliance process for the set of encoded data slices to meet the desired write reliability indication and executing the storage compliance process for the set of encoded data slices.

Abstract: A memory module includes a module error interface, a module data interface, and a plurality of memory device. The module error interface communicates error information a system control path. The module data interface communicates data to and from a main memory path that is separate from the system control path. Each memory device includes a device controller, a device error interface and a device data interface in which the error data interface is separate from the device data interface. Each device controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the corresponding memory device to generate corrected data, generate error information, communicate the error information through the device error interface to the module error interface, and communicate the corrected data through the device data interface to the module data interface. The ECC controller records the error information.

Abstract: An information processing device according to an embodiment includes a buffer, a memory, and a controller. The buffer is capable of storing target data for transfer. The memory is capable of storing a fact that predetermined abnormality detection data is written in the buffer and storing an abnormality detection result of the buffer, the abnormality detection result being written by an external controller which controls a first control target. The controller controls a second control target which is different than the first control target; writes, in the buffer, the abnormality detection data to be transferred to the external controller; makes the memory to hold the fact; and, when the abnormality detection result indicates detection of abnormality, prohibits writing of data in at least such memory areas, from among memory areas in the buffer, in which abnormality is detected.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory.

Abstract: According to one general aspect, an apparatus may include a memory and a reconfigurable error correction array. The memory may be configured to store data. The reconfigurable error correction array may be configured to provide a plurality of levels of error correction to the memory based, at least in part, upon a number of errors detected within the memory.

Abstract: Use of hybrid error correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether the address corresponds to a first region of a memory for which ECC techniques are applied or a second region of the memory for which ECC techniques are not applied. The memory access is processed utilizing ECC techniques if the address corresponds to the first region of the memory, a transaction indicator and an execution unit indicator, and processed without utilizing the ECC techniques if the address corresponds to the second region of the memory.

Abstract: Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including: moving a portion of data used by a host from the storage device to another storage device of the storage system, and reducing declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host.

Abstract: A memory device has a controller, an address integrity feature, and an address register. The controller is configured to store error correction data in the address register when the address integrity feature is enabled.

Abstract: A decoding method for a parity check code, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading a codeword belonging to the parity check code from a rewritable non-volatile memory module, wherein the codeword includes message bits and first parity bits; performing an encoding procedure of the parity check code on the message bits to generate second parity bits; and generating a plurality of syndromes corresponding to the codeword according to the first parity bits and the second parity bits, wherein the syndromes are used to determine whether the codeword is a valid codeword. Accordingly, a complexity of a decoding circuit is decreased.

Abstract: A method for programming data, a memory storage device and a memory control circuit unit are provided. The method includes: receiving a writing command which instructs to write data to a logical address belonging to a logical programming unit; if a physical erasing unit of a physical programming unit which the logical programming unit is mapped to is a first type physical erasing unit, programming the data and a parity code corresponding to the data into the physical programming unit according to a first code rate; and if the physical erasing unit is a second type physical erasing unit, programming the data and the parity code corresponding to the data into the physical programming unit according to a second code rate. The first code rate is higher than the second code rate. Therefore, the lifespan of the physical erasing unit having a higher bit error rate may be extended.

Abstract: Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.

Abstract: A memory device using error correction code (ECC) implements a memory array parallel read-write method to reduce the storage overhead required for storing ECC check bits. The memory array parallel read-write method stores incoming address and data into serial-in parallel-out (SIPO) address registers and write data registers, respectively. The stored data are written to the memory cells in parallel when the SIPO registers are full. ECC check bits are generated for the block of parallel input data stored in the write data registers. During the read operation, a block of read out data corresponding to the read address are read from the memory cells in parallel and stored in read registers. ECC correction is performed on the block of read out data before the desired output data is selected for output.

Abstract: A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

Abstract: A memory system includes a flash memory including a block having first sub-blocks and second sub-blocks different from each other, the second sub-blocks including free pages only; and a controller configured to erase the flash memory in units of the sub-blocks, and in a garbage collection operation, the controller is configured to copy data of a valid page of the first sub-blocks to at least one of the second sub-blocks.

Abstract: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.

Abstract: A bypass mechanism allows a memory controller to transmit requested data to an interconnect before the data's error code has been decoded, e.g., a cyclical redundancy check (CRC). The tag, tag CRC, data, and data CRC are pipelined from DRAM in four frames, each having multiple clock cycles. The tag includes a bypass bit indicating whether data transmission to the interconnect should begin before CRC decoding. After receiving the tag CRC, the controller decodes it and reserves a request machine which sends a transmit request signal to inform the interconnect that data is available. Once the transmit request is granted by the interconnect, the controller can immediately start sending the data, before decoding the data CRC. So long as no error is found, the controller completes transmission of the data to the interconnect, including providing an indication that the data as transmitted is error-free.

Abstract: An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data.

Abstract: The present invention provides systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format. The present invention also provides systems and methods for protecting data stored on data storage medium so that the data may be recovered without errors.

Abstract: A method of operating a computer memory system with ECC features that will enable operational modes with less electrical power consumption. A chip mark normally used to mark a failing DRAM device may instead be used to mark a non-failing DRAM device before a computer memory system shuts off electrical power to the marked non-failing DRAM device to reduce power consumption, putting the rank of memory that contains the DRAM device in a low power consumption mode. Upon a request from the computer memory system, the chip mark may be removed from the marked non-failing DRAM device in order to return the non-failing DRAM device to normal operation.

Abstract: A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.

Abstract: A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2<p<2d), and a mapping unit operative to execute mapping of the target data from the data processing unit as page data within the page buffer.

Abstract: A method for data storage includes providing a mapping of data pages to physical pages, in which each physical page holds a non-integer number of the data pages, for storage of data in at least one memory block, including a plurality of the physical pages, in a memory device. The data pages that are mapped to the memory block are partitioned into groups, such that failure of any memory unit, which consists of a predefined number of the physical pages in the memory device, will produce errors in no more than one data page in each group. The data pages is stored in the physical pages of the memory block in accordance with the mapping, while a redundant storage scheme is applied among the data pages of each group.

Abstract: Methods facilitate data streaming in bulk storage devices by generating linked lists containing entries for both user data and metadata. These linked lists containing mixed data types facilitate receiving and outputting user data, and to insert or ignore, respectively, metadata corresponding to that user data without interrupting flow of the user data.

Abstract: A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is transmitted to a memory device over an address bus coincident with transmitting a no-operation instruction over a command bus.

Abstract: There is provided a method of writing data to a sector of a storage device, the sector comprising a data field and a protection information field and having identifying information identifying the location of said sector. The method comprises providing data to be written to an intended sector, generating, for said intended sector, a message comprising the data and the identifying information of said intended sector and performing, on said message, error correcting encoding to generate a codeword. The codeword comprises the message and parity information generated from said error correcting coding. The data can then be written to the data field of the sector, and the parity information can be written to said protection information field of the sector.

Abstract: A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices.

Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.

Abstract: A user station for a bus system is described and a method for transmitting messages between user stations of a bus system. The user station has a CAN-Controller for reading data of a message to be sent directly from a RAM without buffer storage in a buffer store, and a memory access error detection/processing device for detecting a memory access error of the CAN controller and for processing a detected memory access error.

Abstract: According to one embodiment, a semiconductor memory stores a program for causing a memory controller to operate in at least one of first and second modes. In the first mode, for each of the blocks, the memory controller autonomously erases and writes data and reads the written data, and determines that the block or the semiconductor storage device is defective when a count of errors in the read data exceeds a correction capability or a threshold. In the second mode, when error correction of read substantial data fails, the memory controller reads the substantial data which failed in the error correction using a read level shifted from the present read level.

Abstract: A self-repair device includes an ARE (array rupture electrical fuse) array block configured to store fail addresses; an ARE control block configured to control a repair operation of fuse sets according to the fail addresses, compare a plurality of the fail addresses, and determine a failed state; and a redundancy block configured to store fuse data of the fail addresses, compare an input address with the fail addresses, and control row and column redundancy operations.

Abstract: Address error detection including a method that receives a read address corresponding to a read location in a memory. Data is read from the read location in the memory. The data is transformed at a computer based on the data and the read address to produce read data. Error correction codes (ECC) bits associated the read data are read from the read location in the memory. The ECC bits were generated based on the write data. It is determined whether the read data has an address error responsive to the read data and the ECC bits associated with the write data. An error is generated in response to determining that the read address has an address error.

Abstract: In an embodiment, a plurality of memory dies is coupled as a memory block. The memory block has an access width defined as a system word length divided by a burst length associated with the plurality of memory dies. The burst length is greater than one. A single word having the system word length is written or read in a write operation or a read operation, respectively, through a write burst or a read burst, respectively, for random access memory operation with a granularity of the single word.

Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.

Abstract: A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller comprises a victim block setup unit suitable for setting a victim block for performing a merge operation, based on an error count, which is detected when a read operation of the nonvolatile memory device is performed, and for storing information of the victim block.

Abstract: A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes determining a decoding error associated with information stored at a page of a first block of the non-volatile memory. In response to the decoding error, a physical address is accessed from the management table. The physical address corresponds to a trial logical address. In response to the physical address corresponding to the page, the method further includes moving data from the page to a second block of the non-volatile memory.

Abstract: A wrapping burst read determination unit determines whether or not a read request is a request of a wrapping read. If the read request is the request of the wrapping read, a memory address conversion unit extracts a plurality of addresses that includes an address in which payload data requested by the read request is stored, and designates a read out order of data from the plurality of addresses extracted. If the read request is the request of the wrapping read, a first data holding unit inputs first data read out from an address to which a forefront position in the read out order has been designated among the plurality of addresses, and stores the first data. If the read request is the request of the wrapping read, a data alignment unit, inputs trailing data read out from an address to which an end position in the read out order has been designated, and extracts payload data and an ECC which are correlated with each other from the first data and the trailing data.

Abstract: A data storage device comprises a plurality of non-volatile memory devices configured to store a plurality of physical pages; a controller coupled to the plurality of memory devices that is configured to program data to and read data from the plurality of memory devices. A volatile memory may be coupled to the controller and may be configured to store a firmware table comprising a plurality of firmware table entries. The controller may be configured to maintain a plurality of firmware journals in the non-volatile memory devices. Each of the firmware journals may be associated with a firmware table entry and may comprise firmware table entry information. The controller may be configured to read the plurality of firmware journals upon startup and rebuild the firmware table using the firmware table entry information in each of the read plurality of firmware journals.

Abstract: Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.

Abstract: Address error detection including a method that receives write data and a write address, the write address corresponding to a location in a memory. Error correction code (ECC) bits are generated based on the received write data. The write data is transformed at a computer based on the write address and the write data, to produce transformed write data. The transforming is configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between either the write address or the read address and data read from the location. The transformed write data and the ECC bits are written to the location in memory.

Abstract: A method for data storage includes assigning in a memory that includes one or more storage devices a first storage area for storage of user data, and a second storage area, which is separate from the first storage area, for storage of redundancy information related to the user data. Input data is processed to produce redundancy data, and the input data is stored in the first storage area using at least one first write command. The redundancy data is stored in the second storage area using at least one second write command, separate from the first write command.

Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.

Abstract: A data storage system configured to efficiently search and update system data is disclosed. In one embodiment, the data storage system can attempt to correct errors in retrieved data configured to index system data. Metadata stored along with user data in a memory location can be configured to indicate a logical address associated in a logical-to-physical location mapping with a physical address at which user data and metadata are stored. The data storage system can generate modified versions of logical address indicated by the metadata and determine whether such modified versions match the physical address in the logical-to-physical mapping. Modified versions of the logical address can be generated by flipping one or more bits in the logical address indicated by the metadata. Efficiency can be increased and improved performance can be attained.

Abstract: A method and apparatus are described including determining address using an access point address and a multicast group address, transmitting a recovery request message to a recovery server to request recovery data using the address and receiving the recovery data from the recovery server. Also described are a method and apparatus including receiving a registration message, transmitting a reply to the registration message, receiving a recovery request message, transmitting recovery data responsive to the recovery request message and transmitting a message to a recovery multicast group to determine status of the recovery multicast group.

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Abstract: Error correction coding for streaming communication is provided. A streaming problem is modeled as a non-multicast network problem with a nested receiver structure. Each packet in the streaming problem corresponds to a link, and each deadline in the streaming problem corresponds to a receiver in the non-multicast network problem. For the non-multicast network problem, content to be transmitted in multiple packets to multiple receivers is obtained. Each of the receivers is required to decode specific independent messages from the content, at given time steps, and has access to a subset of the content received by another receiver. The content is allocated into multiple packets to be transmitted on multiple links. No coding occurs across information demanded by different receivers. A capacity region defines a set of information rate vectors that can be communicated to the receivers successfully. A rate vector is successfully communicated if it complies with various inequalities.

Abstract: A system and method for expeditious transfer of data from a source device to a destination device in error corrected manner are provided. The system and method avoid the substantial delay in utilizing an intermediate buffer, determining error, and remediating the detected errors before even initializing a transfer of an input data from the source device to the destination device. Upon completion of error correction, only those portions corrected are retransmitted to the destination memory rather than the complete corrected input data. A by-pass section is provided for copying input data to the destination memory with at least a degree of parallelism with the error detection of the input data delivered to a parallel buffer coupled with the correction section by a splitter section.