Abstract: A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.

Abstract: Adaptive endurance coding including a method for accessing memory that includes retrieving a codeword from a memory address. The codeword is multiplied by a metadata matrix to recover metadata for the codeword. The metadata includes a data location specification. The data in the codeword is identified in response to the metadata and the data is output as read data.

Abstract: An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the nonvolatile memory include an error beyond an error correcting capability of the error correcting device. When the determining unit has determined that an error beyond the error correcting capability exists, the error correcting device does not perform the correction of the error.

Abstract: A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes a storage for storing a resource discovery table, and programmed I/O (PIO) configuration registers corresponding to hardware resources. A system processor may allocate the plurality of hardware resources to one or more functions, and to populate each entry of the resource discovery table for each function. The processing units may execute one or more processes. Given processing units may further execute OS instructions to allocate space for an I/O mapping of a PIO configuration space in a system memory, and to assign a function to a respective process. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.

Abstract: Embodiments are disclosed herein that relate to multicast subscription based on forward error correction. One disclosed embodiment comprises a network-accessible server having a data-holding subsystem holding instructions executable by a logic subsystem to receive a content item, and form a first version of the content item having a first level of forward error correction and a second version of the content item having a second level of forward error correction. The instructions are further executable to stream the first version of the content item to a first multicast address, and while streaming the first version of the content item, stream the second version of the content item to a second multicast address.

Abstract: A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: Provided are an address generation apparatus and method of an interleaver/deinterleaver. By calculating coefficients of an address generator polynomial of an interleaver by determining exponents according to the number of prime factors forming a length of input data of the interleaver and generating an address of the deinterleaver using the calculated coefficients, errors generated when the address of the deinterleaver is generated can be removed, and right interleaver and deinterleaver addresses can be calculated.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: Techniques are presented for dynamically optimizing the performance of the controller-memory (or “back-end”) interface of a non-volatile memory system. Memory systems are usually designed to have a certain amount of error tolerance for error that can then be corrected by ECC. In may circumstances, such as when a device is new, the ECC capabilities of the system exceed what is needed to correct data storage errors. In these circumstances the memory system internally allots a non-zero portion of this error correction capacity to the back-end interface. This allows for the interface to operate at, for example, higher speed or lower power, even though this will likely lead to transmission path error. The system can also calibrate the back-end interface to determine that amount of error that result from various operating conditions, allowing the operating parameters of the back-end interface to be set according to amount of error that is allotted to the transfer process.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: A nonvolatile memory device includes a memory cell array configured to comprise memory cells coupled by bit lines and word lines, a page buffer unit configured to comprise page buffers and flag latches, wherein the page buffers, coupled to one or more of the bit lines, each are configured to comprise a plurality of latches for storing logic operation results for error correction and configured to store data read using a read voltage, and the flag latches each are configured to classify the page buffers into some page buffer groups each having a predetermined number and to store flag information indicating whether an error has occurred in each group, and an error detection code (EDC) checker configured to determine whether an error has occurred in each of the page buffer groups.

Abstract: Data is processed by obtaining data and redundant information from an expected position in a channel. Soft position information associated with the data is obtained and error correction decoding is performed using the data, the redundant information, and the soft position information to obtain a decoded position and decoded data. It is determined if the decoded position matches the expected position and the decoded data is output in the event the decoded position matches the expected position.

Abstract: Systems and methods are provided for storing data in a portion of a non-volatile memory (“NVM”) such that the status of the NVM portion can be determined with high probability on a subsequent read. An NVM interface, which may receive write commands to store user data in the NVM, can store a fixed predetermined sequence (“FPS”) with the user data. The FPS may ensure that a successful read operation on a NVM portion is not misinterpreted as a failed read operation or as an erased NVM portion. For example, if the NVM returns an all-zero vector when a read request fails, the FPS can include at least one “1” or one “0”, as appropriate, to differentiate between successful and unsuccessful read operations. In some embodiments, the FPS may also be used to differentiate between disturbed data, which passes an error correction check, and correct data.

Abstract: An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits.

Abstract: In various embodiments, the reference voltage used for read operations in a non-volatile memory may be adjusted up or down in an attempt to read data from an area that previously produced at least one uncorrectable error. The direction and amount of this adjustment may be based on the number and direction of correctable errors in surrounding data.

Abstract: A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.

Abstract: A method for data storage includes defining a set of scrambling sequences, each sequence including bits in respective bit positions having bit values, such that a distribution of the bit values in any give bit position satisfies a predefined statistical criterion. Each data word is scrambled using a respective scrambling sequence selected from the set. The scrambled data words are stored in the memory device.

Abstract: A method of partitioning a page of an electronic memory includes creating a first sub-page by interleaving a first user data section of the page with another section of a spare area of the page excluding a specified address in a section of the spare area that stores a bad block marker. The method also includes creating the sub-pages by interleaving the user data sections with sections of the spare area excluding the specified address until a last sub-page is to be created. Further, the method includes creating the last sub-page by interleaving a last user data section with the section of the spare area that includes the specified address in an interleaving sequence that retains the bad-block marker at the specified address.

Abstract: By using a processor to share certain burdens originally handled by a controller of a nonvolatile memory module, the controller is able to process more complicated procedures. The procedures include an error correction code generating procedure, a data scrambling procedure, a data recovery procedure, an address translation procedure configured to translate a logical address into a physical address, and a wear leveling procedure.

Abstract: A method for address generation checking including receiving a starting memory address for a data, an ending memory address for the data, a length value of the data, and an address wrap indicator value that indicates if the data wraps from an end of a memory block to a start of the memory block, determining whether the ending memory address is equal to a sum of the starting memory address added to a difference of the length value to the address wrap indicator value, and transmitting an error signal that indicates an error occurred in a generation of the starting memory address or the ending memory address if the ending memory address is not equal to the sum.

Abstract: The present invention is directed to a memory device with protection capability and a method of accessing data therein. A spreader encrypts input user data according to an entered password, and the encrypted data is then stored in a storage area. A despreader performs reverse process of the spreader on the stored data according to the entered password.

Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.

Abstract: A method for operating a memory includes encoding input data with an Error Correction Code (ECC) to produce input encoded data including first and second sections, such that the ECC is decodable based on the first section at a first redundancy, and based on both the first and the second sections at a second redundancy that is higher than the first redundancy. Output encoded data is read and a condition is evaluated. The input data is reconstructed using a decoding level selected, responsively to the condition, from a first level, at which a first part of the output encoded data corresponding to the first section is processed to decode the ECC at the first redundancy, and a second level, at which the first part and a second part of the output encoded data corresponding to the second section are processed jointly to decode the ECC at the second redundancy.

Abstract: An memory device including a data region storing a main data, a first index region storing a count data, and a second index region storing an inverted count data, where the data region, the first index region, and the second index region are included in one logical address.

Abstract: Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated.

Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.

Abstract: A method for generating error detection code is disclosed. Firstly, a first error detection code PEDC is derived by using 12-byte unknown sector data information including ID, IED, RSV and the 2048-byte main data while the main data is delivered from a host. Secondly, a second error detection code MEDC is obtained by using known 12-byte sector data information including ID, IED, RSV and the 2048-byte main data. Thereafter, the real error detection code EDC is obtained by applying an exclusive-OR operation to both the PEDC and MEDC.

Abstract: Systems for generating an identifying response pattern comprising a memory (120) used as a physically unclonable function configured for generating a response pattern dependent on physical, at least partially random characteristics of said memory may be vulnerable to freezing attacks and to aging. A memory-overwriting device (110) configured for overwriting at least a first portion of the plurality of memory locations to obscure the response pattern in the memory avoids freezing attacks. An anti-degradation device (160) configured to write to each respective location of a second portion of the plurality of memory locations an inverse of a response previously read from the memory reduces the effects of aging.

Abstract: Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.

Abstract: There is provided a data transmission device including a data information storage area including a plurality of areas for storing a first memory address of the first memory device of a data transmission source, a second memory address of the second memory device of a data transmission destination, an error signal indicating whether or not an error is detected in transmission data, and an validity signal indicating whether or not data stored in the second memory device are valid after completing the error correction; and a control unit that outputs a second memory validity address which is a memory address in which data are valid out of data stored in the second memory device, reads data from the second memory validity address of the second memory device, and transmits an address of the first memory device corresponding to the second memory validity address along with the read data.

Abstract: An apparatus for improving the reliability of host data stored on Fiber Channel attached storage subsystems by performing end-to-end data integrity checks. When a read or write operation is initiated, an initial checksum for data in the read/write operation is generated and associated with the data, wherein the association exists through a plurality of layers of software and attached storage subsystems. The initial checksum is passed with the data in the read/write path. When a layer of software in the read/write path receives the initial checksum and data, the layer performs an integrity check of the data, which includes generating another checksum and comparing it to the initial checksum. If the checksums do not match, the read/write operation fails and the error is logged. If the checksums match, the integrity check is repeated through each layer in the read/write path to enable detecting data corruption at the point of source.

Abstract: In a method of initializing a computer memory that receives data from a plurality of redrive buffers, a predetermined data pattern of a selected set of data patterns is stored in selected redrive buffers of the plurality of redrive buffers. Each of the selected set of data patterns includes a first initialization data pattern and an error correcting code pattern that is a product of a logical function that operates on the first initialization data pattern and an address in the computer memory. The selected set of data patterns includes each possible value of error correcting code pattern. A redrive buffer of the plurality of redrive buffers that has stored therein an error correcting code pattern that corresponds to the selected address is selected when sending a first initialization data pattern to a selected address. The selected redrive buffer is instructed to write to the selected address the first initialization data pattern and the error correcting code pattern that corresponds to the selected address.

Abstract: A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g.

Abstract: An example apparatus has an interface to a first memory and to a second memory. The example apparatus also has a control logic that functions to control the interface. The control logic can control the interface to write a data word to the first memory and to write an error checking and correcting (ECC) word associated with the data word to the second memory.

Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.

Abstract: An error detection control system for a nonvolatile memory comprises: a nonvolatile memory having data areas for a plurality of addresses each including a main data area and a redundant data area for one address; memory control means for controlling on the nonvolatile memory a batch erasing process on a data area group basis, a reading process on the data area basis, a programming process on the data area basis, and an overwriting process on a bit basis; error detecting means for executing the error detecting process based upon the corresponding redundant data; error detecting control means for controlling availability of execution of the error detecting process based upon data types to be classified depending on whether or not the data is subjected to the overwriting process or a storage state indicating whether or not the overwriting process has been executed.

Abstract: A decoder device includes: a decoder that decodes data stored in a storage medium by performing error correction on the data, the error correction being capable of correcting code error and code erasure included in the data; a memory that stores a history of an address in the storage medium of a code included in the data, the code being detected to have the code error by the decoding unit; and a controller that controls the decoder to change a detail of the error correction based on the history stored in the memory.

Abstract: According to one embodiment, an encoder/decoder apparatus includes an encoder module, a decoder module, and a transposing module. The encoder module is configured to generate a Hamming code from the input data, in accordance with a check matrix having a specific regularity. The decoder module is configured to detect an error position in the output data composed of the Hamming code, in accordance with the check matrix. The transposing module is configured to perform a transposing process of transposing some of the columns of the check matrix, while maintaining the regularity of the check matrix, and to change the error position in accordance with the transposing process, during the decoding process.

Abstract: A method, system, apparatus, and computer program product for decoding control information, wherein a total number of allocation blocks defining control channels to be allocated to users for at least one of uplink and downlink directions is determined. Then, a format which determines resource allocation within allocation blocks is selected, allocation blocks are decoded using the selected format, and an error checking is performed for the decoded allocation blocks. This selecting, coding and error checking is repeated for different available formats until no error is revealed in said error checking. Thereby, a blind estimation of a format chosen for the control channel information can be achieved, so that additional amount of control signalling can be reduced.

Abstract: The present invention is a method for accessing more than one block of correctable information at a time when it is most efficient to access more bits of information at a time on a given dimension, for example from a multiple bit per cell (MLC) memory element, than the error correction algorithm can correct. Since it may be more efficient to access more bits of information at a time on a given dimension than the error correction algorithm can correct, that access is performed in this most efficient way, but the information is divided into correctable blocks within this information such that the error correction algorithm can still compensate for a serious fault along a given dimension. Furthermore, the present invention can be employed even when the number of bits retrieved along a given dimension is less than the number of correctable bits when it is desired to protect against a given number of faults which could, in total, exceed the number of correctable bits.

Abstract: Provided are methods for error correction coding (ECC) for flash memory pages which have been erased but have not been programmed. In one method, each ECC code word is bitwise inverted before being programmed into a page, and bitwise inverted again after being read back from the page before entering the decoder. Thus an unwritten page, whose bits are all ones when random errors are absent, appears to the decoder as all zeros, which form a valid code word(s) in linear block codes. In another method, in both page programming and page read, the parity section of each ECC code word is bitwise XORed with the complement of a parity calculated from a message whose bits are all ones. Thus an unwritten page appears to the decoder as a valid ECC code word(s) when random errors are absent.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Abstract: A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in a register, the store data is written to the cache memory, the stored contents of the register are merged with the store data, and an error correction code is generated for a result of the merger.

Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.

Abstract: Systems and methods of storing error correction data are provided. A method may include storing data at a first memory having a first non-volatile memory type. The method may also include determining error correction data related to the stored data. The method may further include storing the error correction data at a second memory having a second non-volatile memory type. The first non-volatile memory may have a slower random access capability than the second non-volatile memory.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.

Abstract: A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.