Abstract: Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a response to a read request of contents of the particular partition may be delayed. In some embodiments, the contents of the particular partition may be indirectly read during the write process without delaying the response to the read request. The contents of the particular partition can be indirectly read by determining the contents of the particular partition based, at least in part, on an error correction code based, at least in part, on contents of memory partitions of the memory array.

Abstract: There is provided a memory control device, including a request determining unit that determines a type of a request, and a control unit that writes read data read from a memory cell array in the memory cell array in units of predetermined pages of the memory cell array when the request is a refresh request, and divides the page of write data into units of groups and writes the page of the write data in the memory cell array over twice or more when the request is a write request.

Abstract: A method and apparatus are described including determining address using an access point address and a multicast group address, transmitting a recovery request message to a recovery server to request recovery data using the address and receiving the recovery data from the recovery server. Also described are a method and apparatus including receiving a registration message, transmitting a reply to the registration message, receiving a recovery request message, transmitting recovery data responsive to the recovery request message and transmitting a message to a recovery multicast group to determine status of the recovery multicast group.

Abstract: A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.

Abstract: In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

Abstract: A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits whereby these address bits are transformed by transforming logic. This transforming logic may include adders. Transforming logic may alternately include comparators or exclusive-or circuits. Transforming logic comprising adders may include overflow carry bits that are discarded, ignored, or otherwise not used or the overflow logic may be omitted altogether.

Abstract: On chip redundancy repair for memory devices. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM. The system element includes a memory controller for control of the DRAM, and repair logic coupled with the memory controller, the repair logic to hold addresses identified as failing addresses for defective areas of the DRAM. The repair logic is configured to receive a memory operation request and to implement redundancy repair for an operation address for the request.

Abstract: Disclosed is a semiconductor device including an ECC circuit for improving error correction capability. A semiconductor device in accordance with an embodiment of the present invention includes a memory region configured to include a plurality of banks and a redundancy region within each of the banks and an error check and correction (ECC) region configured to detect an address of the memory region at which an error has occurred and correct a defect of the memory region by replacing the address at which the error has occurred with a redundancy line of the redundancy region based on address information.

Abstract: A packet switching system includes a forwarding processing unit determining a destination of an input packet by analyzing the input packet and outputting it as an output packet, the forwarding processing unit comprises an ingress interface card checking if the input packet has a sequential cyclic number and an egress interface card creating a sequential cyclic number and assigning it to the output packet.

Abstract: An error correction circuit 1 in accordance with an aspect of the invention includes an associative memory 20, a logic circuit 10 disposed in parallel with the associative memory 20, and selection unit 30 that receives an output signal from the associative memory 20 and an output signal from the logic circuit 10 as an input. The associative memory 20 includes a table that handles an input signal as a word and holds an output signal related to the word and an error correction code used to correct the output signal as data. The associative memory 20 further includes error correction unit that outputs a signal in which an error was corrected based on data related to a word corresponding to an input signal. The selection unit 30 selects and outputs one of an output signal from the associative memory 20 and an output signal from the logic circuit 10.

Abstract: Method and apparatus for writing data to be stored to a predetermined memory area, the method comprising: reading stored data from the predetermined memory area, the stored data comprising a stored data block and an associated stored error detection value, manipulating, after reading the stored data, at least one of the stored data block and the associated stored error detection value in the predetermined memory area, and writing, after manipulating, the data to be stored to the predetermined memory area.

Abstract: System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.

Abstract: Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the write data at the memory device associated with the memory address. In addition, the memory device can selectively perform error detection and correction for write accesses using the ECC checkbits. For example, the memory device can include an ECC control register that stores control information to selectively enable and disable error detection and correction for write accesses. In an embodiment, error detection and correction can be selectively enabled and disabled for different sizes of write data.

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

Abstract: A cache memory is operated in a write through system, and an operation to be performed when a cache mishit occurs is performed when corresponding data is not stored in the cache memory, or only when an error occurs although there is the data. Then, a bit indicating that a soft error has occurred before is set in the cache memory, and when the bit indicates “1” and if an error has occurred again, it is determined that a hardware error has occurred, and an interrupt is generated in the CPU. The bit is to be reset at time intervals sufficiently shorter than the frequency at which it is considered that a soft error occurs.

Abstract: A computer program product for performing input/output (I/O) processing is provided. The computer program product is configured to perform: obtaining information relating to an I/O operation at a channel subsystem; generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data check word generation field and/or a data check word save field; responsive to receiving an input data transfer request including at least one data check word, storing the at least one data check word in the data check word save field and performing a check of the data to determine whether the data has been corrupted; and responsive to receiving an output data transfer, generating at least one data check word based on the data check word generation field and appending the at least one data check word to the data.

Abstract: An input/output processing method includes generating and storing at least one address control word (ACW) including a data check word generation field and/or a data check word save field in local channel memory of a channel subsystem, and generating and forwarding to a network interface an address control structure specifying a location in the local channel memory of a corresponding ACW. The method also includes, responsive to a data transfer request, storing the at least one data check word in the data check word save field and routing the data to a host memory location specified by the corresponding ACW responsive to performing a check of the data and determining that the data has not been corrupted, or retrieving the data based on the corresponding ACW, generating and appending at least one data check word and routing the data and the at least one data check word to the interface.

Abstract: A method for data storage includes defining a set of scrambling sequences, each sequence including bits in respective bit positions having bit values, such that a distribution of the bit values in any give bit position satisfies a predefined statistical criterion. Each data word is scrambled using a respective scrambling sequence selected from the set. The scrambled data words are stored in the memory device.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the data and, in response to a read access at the memory address, are employed to check for errors in both the address and the data provided in response to the read access (the read data). The ECC checkbit generation process can result, for particular memory addresses, in checkbits that can incorrectly indicate whether errors are present in the read data. Accordingly, the checkbits can be selectively inverted based on the memory address so that the checkbit pattern will not result in an incorrect error detection or correction.

Abstract: A cache memory system includes a cache controller and a cache tag array. The cache tag array includes one or more ways, one or more indices, and a cache tag entry for each way and index combination. Each cache tag entry includes an error correction portion and an address portion. In response to an address request for data that includes a first index and a first address, the cache controller compares the first address to the cache tag entries of the cache tag array that correspond to the first index. When the comparison results in a miss, the cache controller corrects cache tag entries with an error that correspond to the first index using the corresponding error correction portions, and stores at least one of the corrected cache tag entries in a storage that is external to the cache tag array. The cache controller, for each corrected cache tag entry, replays the comparison using the least one of the externally stored corrected cache tag entries.

Abstract: A method includes, after data is stored at a data area of a memory device and error correction code (ECC) data corresponding to the data is stored at an ECC area corresponding to the data area, detecting a triggering condition. In response to detecting the triggering condition, the method also includes storing second ECC data in the ECC area, where the second ECC data includes redundant information for a first portion of the data area and storing third ECC data at the memory device. The third ECC data includes redundant information for a second portion of the data area.

Abstract: A memory controller comprises at least a memory control processing module and/or a distributed storage processing module. A method begins by the memory control processing module receiving a memory access request regarding a data segment. The method continues with the memory control processing module interpreting the memory access request to determine whether an error coding dispersal function of the data segment is applicable. The method continues with the memory control processing module sending the memory access request to the distributed storage processing module when the error coding dispersal function is applicable. The method continues with the distributed storage processing module performing the error coding dispersal function on the data segment to produce an error coded processed data segment. The method continues with the distributed storage processing module sending the error coded processed data segment to the memory control processing module.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.

Abstract: A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a “read disturb phenomenon” in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address.

Abstract: A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet.

Abstract: Adaptive endurance coding including a method for accessing memory that includes retrieving a codeword from a memory address. The codeword is multiplied by a metadata matrix to recover metadata for the codeword. The metadata includes a data location specification. The data in the codeword is identified in response to the metadata and the data is output as read data.

Abstract: Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

Abstract: A method, using a dispersed storage processing module, includes receiving media content determining social media metadata regarding the media content, encoding the media content in accordance with an error coding dispersal storage function to produce a plurality of sets of encoded data slices, identifying a plurality of memories to store the plurality of sets of encoded data slices, and sending the plurality of sets of encoded data slices to the plurality of memories when the social media metadata indicates that the media content is to be available for a local social network.

Abstract: A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length.

Abstract: According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory and a logic unit. The logic blocks are grouped into one or more partitions. The memory stores authentication and partition information uploaded to the programmable logic device prior to partition programming. The logic unit authenticates programming access to the one or more partitions based on the authentication information and controls programming of the one or more partitions based on the partition information.

Abstract: Methods and devices capable of erasing a flash memory evenly are provided, in which a flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks, and a controller retrieves a corresponding data with a check code from a first data block of the flash memory according to a read command from a host, performs a predetermined check to the corresponding data by the check code, determines whether an error is correctable when a check result of the predetermined check represents that the error has occurred, and increases an erase count of the first data block by a predetermined value when the error is correctable.

Abstract: The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program command received from a host to the at least one flash memory device. If the error correction code indicates there is an error in the data, the controller corrects the data and sends the destination address, the corrected data, and a program command to the at least one flash memory device. Additional embodiments relate to modifying data during the copy-back operation.

Abstract: An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.

Abstract: A storage system with a data recovery function and its method reduce errors in a storage medium to a recoverable range of a general ECC function by repeating a testing and recovery procedure for one or more times to assure the accuracy of reading data and enhance the data reliability effectively. The data recovery procedure includes the steps of providing test data by a test data generator of the storage system, writing the test data into a memory block where error data is found, finding an error bit by reading the test data, reducing the error to a recoverable range of the ECC technique by the recovery procedure. If the error bit cannot be found or reduced to a recoverable range of the ECC technique within an upper limit of the number of tests, the memory block is marked as bad.

Abstract: A programmable device employs an address and data corruption logic for data written to a first memory. A first signature is computed from the data stored in the first memory and stored in a second memory. When data is read from the first memory, the first signature stored in the second memory is read and compared with a second signature computed from the data read from the first memory. If the first and second signatures do not match, an error condition is indicated.

Abstract: A non-volatile semiconductor memory (NVSM) storage system includes a NVSM drive interface configured to receive host data sectors (HDSs) from a host interface. A buffer managing module is configured to store the HDSs in a buffer. A compression module is configured to compress the HDSs to generate compressed HDSs of different lengths. A drive data sector (DDS) generating module is configured to add nuisance data to the compressed HDSs to generate DDSs. The DDSs are stored in NVSM.

Abstract: An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal are accessed. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information.

Abstract: A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.

Abstract: The invention is directed to a method and apparatus for decoding encoded data symbols. The invention is also directed to corresponding encoding methods. The decoder arrangement comprises an input for receiving encoded data and an identifier associated with a coding scheme used to create said encoded data. A processor in the decoding arrangement determines from the identifier, a mapping between said encoded data and the original data. A decoder uses the mapping to extract the original data from the encoded data. The operation of the decoder is independent of the coding scheme used in the encoding process.

Abstract: A computer-implemented method for using cloud-based storage to optimize data-storage operations may include: 1) receiving a request from a client device for instructions or directions for storing a data object, 2) accessing a data-placement policy that contains criteria for identifying storage systems suitable for storing the data object, 3) identifying, based at least in part on the data-placement policy, a plurality of storage systems for storing the data object, at least one of the storage systems including a third-party Internet-based storage system, and then 4) directing the client device to store the data object on the identified storage systems.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of turbo decoding. For example, a device may include a turbo decoder to decode a turbo-encoded input according to a turbo code, the turbo-encoded input including a plurality of soft-decision information-bit values and a plurality of soft-decision parity-bit values corresponding to the soft-decision information bit values, wherein the turbo decoder is to output a plurality of extrinsic soft-decision parity-bit values corresponding to the plurality soft-decision parity-bit values. Other embodiments are described and claimed.

Abstract: Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.

Abstract: Systems and methods are disclosed for partitioning data for storage in a non-volatile memory (“NVM”), such as flash memory. In some embodiments, a priority may be assigned to data being stored, and the data may be logically partitioned based on the priority. For example, a file system may identify a logical address within a first predetermined range for higher priority data and within a second predetermined range for lower priority data, such using a union file system. Using the logical address, a NVM driver can determine the priority of data being stored and can process (e.g., encode) the data based on the priority. The NVM driver can store an identifier in the NVM along with the data, and the identifier can indicate the processing techniques used on the associated data.

Abstract: Exemplary method, system, and computer program product embodiments for data verification in a storage system are provided. A read of data is asynchronously submitted to nonvolatile storage media. A read of a first checksum signature is submitted to a solid state, sidefile memory location of a storage controller in the storage subsystem. The first checksum signature is representative of the data previously written to the nonvolatile storage media. A second checksum signature is calculated from the read of the data. The first and second checksum signatures are compared. If a match is not determined, a critical event is reported.

Abstract: A method includes reading data from a data area of a word line and reading first ECC data from an ECC area of the word line. The method also includes, in response to determining that an error indicator exceeds a threshold, storing second ECC data in the ECC area. The second ECC data corresponds to a subsection of the data area.

Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.