Abstract: An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.

Abstract: Disclosed is a transmission device in a communication system in which a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deleting the dummy bits from the results of the systematic encoding is transmitted and, on the receiving side, the dummy bits which had been deleted on the transmitting side are inserted into the received systematic code, and then decoding is performed. In this transmission device, a dummy bit insertion portion decides the size of the dummy bits to be inserted into the information bits based on a specified code rate or based on the physical channel transmission rate, and uniformly inserts dummy bits of this size into the information bits; a systematic code generation portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the systematic encoding to generate a systematic code, which is transmitted.

Abstract: A method for auto-correction of errors in an array of solid-state storage devices having a plurality of storage channels dedicated to storing parity data to provide fault tolerance for a loss of at least two of the plurality of storage channels. A read operation from the storage channels transfers data to a plurality of channel memories. The data in the channel memories is checked to confirm the data is valid. Responsive to detection of invalid data, the data may be tested to identify the storage channel in error, including sequentially excluding data read form a different one of the plurality of channel memories from a parity check and determining the validity of data from remaining channel memories. If valid data is obtained, the storage channel from which the data was excluded is identified as the storage channel in error.

Abstract: A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: A Redundant Array of Inexpensive Disks (RAID) controller comprises a RAID error correction code (ECC) encoder module that receives data for storage and that generates code words for data drives and one or more parity drives, which have physical locations. The code words are generated based on the data and a cyclic code generator polynomial. Logical locations correspond to index positions in the cyclic code generator polynomial. A mapping module maps the physical locations of the data and parity drives to the logical locations. The mapping module adds a new data drive to an unused one of the logical locations. A difference generating module generates a difference code word based on the new data drive. The RAID ECC encoder module encodes the difference code word and adds the encoded difference code word to an original code word generated before the new data drive is added.

Abstract: An apparatus and method to encode a block Low Density Parity Check (LDPC) code in a signal transmission apparatus is disclosed. The method includes generating a first block LDPC codeword by encoding an information vector using a first parity check matrix when a code rate to be used in the signal transmission apparatus is a first code rate as a code rate of the first parity check matrix, and generating a second block LDPC codeword by encoding the information vector using a second parity check matrix when the code rate to be used in the signal transmission apparatus is a second code rate as a code rate of the second parity check matrix.

Abstract: A low density parity check codes decoder decodes an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder enables decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix. It stores therein Mbmax×Nbmax validity/invalidity flags, shift amounts of valid permutation matrices, a permutation matrix size in a processing target code, and the number of rows of a base matrix in the processing target code, determined depending on a check matrix for the processing target LDPC code, and generates column addresses and a row address to be given to column processing calculation sections and a row processing calculation section that perform calculation in accordance with a BP algorithm by utilizing the stored information, so that it can process an LDPC code for a smaller base matrix than the aforementioned base matrix as well.

Abstract: A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.

Abstract: A method for writing data to a memory array includes receiving a write request including data from a processor, compressing the data, assigning a page strength to the compressed data, the page strength defined by a compression ratio used to compress the data, generating a parity data block associated with the compressed data, and saving the compressed data and the parity data block in a page of the memory array, the page of the memory array having a page strength corresponding to the assigned page strength of the compressed data.

Abstract: Provided are methods for error correction coding (ECC) for flash memory pages which have been erased but have not been programmed. In one method, each ECC code word is bitwise inverted before being programmed into a page, and bitwise inverted again after being read back from the page before entering the decoder. Thus an unwritten page, whose bits are all ones when random errors are absent, appears to the decoder as all zeros, which form a valid code word(s) in linear block codes. In another method, in both page programming and page read, the parity section of each ECC code word is bitwise XORed with the complement of a parity calculated from a message whose bits are all ones. Thus an unwritten page appears to the decoder as a valid ECC code word(s) when random errors are absent.

Abstract: Encoding and/or decoding of messages. On the encoding end, a composite encoder encodes message from an internal format that is used by internal system components into an external format. However, the composite encoder may encode the outgoing messages into different external formats on a per-message basis. For incoming message, a composite decoder decodes incoming messages from any one of a plurality of external formats into the internal format also on a per-message basis. A per-message report mechanism permits internal system components and the encoding/decoding components to communicate information regarding the encoding or decoding on a per message basis. This permits a higher level of collaboration and complexity in the encoding and decoding process.

Abstract: Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

Abstract: A data processing system for processing digital data with a low density parity check (LDPC) matrix includes: a storage device for storing a plurality of indices representing a plurality of shifting numbers, where the LDPC matrix comprises an array of elements, and at least one element of the LDPC matrix represents a cyclic permutation matrix that is produced by cyclically shifting columns of an identity matrix to the right according to one of the shifting numbers; and a processing circuit, coupled to the storage device, for retrieving at least one index to recover at least one element of the LDPC matrix according to the index and performing data processing according to the LDPC matrix.

Abstract: A coding system for digital data. The coding system includes a constrained encoder module configured to generate encoded data based on a first constrained code; a bit insertion module configured to insert at least one bit location in the encoded data; and an inner encoding module configured to (i) generate inner-code parity bits based on the encoded data, and (ii) program the inner-code parity bits into the at least one bit location.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.

Abstract: A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.

Abstract: Digital communication coding methods are shown, which generate certain types of low-density parity-check (LDPC) codes built from protographs. A first method creates protographs having the linear minimum distance property and comprising at least one variable node with degree less than 3. A second method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of certain variable nodes as transmitted or non-transmitted. A third method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of the status of certain variable nodes as non-transmitted or set to zero.

Abstract: Irregular LDPC codes have a construction which allows one to obtain a number of codes with different length from a single prototype code with a parity check matrix given by H=[Hz Hi], where Hz specifies the well-known zigzag pattern in the corresponding Tanner graph. The parity check matrices for longer codes are obtained as [Hz??diag(Hi, . . . , Hi)], where Hz? specifies a longer zigzag pattern depending on the number of matrices Hi used, and ? represents some permutation. This allows one to construct the decoder for a longer code by reusing hardware components developed for decoding the prototype code.

Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.

Abstract: An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

Abstract: The present invention relates to a signal processing device and a signal processing method that are capable of processing various types of signals. The signal processing device comprises a frequency detecting unit detecting a frequency of a data signal by checking synchronization between the data signal and a reference signal, an oscillation unit supplying the reference signal to the frequency detecting unit, a frame detecting unit detecting a frame organizing the data signal, and a control unit changing a frequency of the reference signal supplied by the oscillation unit to take frequency synchronization between the data signal and the reference signal in checking the synchronization by the frequency detecting unit, and setting information of the frequency, of which the frequency synchronization has been taken, in the frame detecting unit.

Abstract: Encoding of a low-density parity check code uses a block-circulant encoding matrix built from circulant matrices. Encoding can include partitioning data into a plurality of data segments. The data segments are each circularly rotated. A plurality of XOR summations are formed for each rotation of the data segments to produce output symbols. The XOR summations use data from the data segments defined by the circulant matrices. Output symbols are produced in parallel for each rotation of the data segments.

Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: Systems and methods are provided for encoding a stream of datawords based on a tensor product code to provide a stream of codewords, and detecting and decoding a stream of received data based on a tensor product code to provide a decoded stream of data. In one aspect, the tensor product code is based on two codes including an inner code and an outer parity hiding code, where the outer parity hiding code is an iterative code. In certain embodiments, the outer parity hiding code is a Turbo code or a low density parity check (LDPC) code.

Abstract: An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets of Galois Field engine circuits which are used in the XOR circuit, is one which can generate high efficient parity engine and high efficient flow data route and which at the same time correct the three or more failures during operation of the RAID device.

Abstract: A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.

Abstract: Decoder for low-density parity check convolutional codes. In at least some embodiments, a decoder (200) for arbitrary length blocks of low-density, parity-check codes includes a plurality of interconnected processors (202), which further include a plurality of interconnected nodes. A memory can be interconnected with the nodes to store intermediate log likelihood ratio (LLR) values based on channel LLR values. Thus, LLR values having successively improved accuracy relative to the channel LLR values can be output from each processor, and eventually used to decision information bits. In some embodiments, the memory is a random access memory (RAM) device that is adapted to store the intermediate LLR values in a circular buffer. Additionally, a storage device such as a read-only memory (ROM) device can be used to generate a predetermined plurality of addresses for reading and writing LLR values.

Abstract: A semiconductor memory device includes: a parity generating circuit for generating parity data corresponding to input data; a normal data latching section for latching the input data or data read out from the normal memory cell array; an input selection circuit for selectively outputting the input data or the parity data; a parity data latching section for latching and outputting the output from the input selection circuit or data read out from the parity memory cell array; and an error correction circuit for performing an error detection on the data latched by the normal data latching section by using the data latched by the parity data latching section, and performing an error correction if an error is detected, to output the obtained result. The parity data latching section outputs the data latched by itself externally of the semiconductor memory device.

Abstract: An improved error correction apparatus and method for a digital device are provided. An error correction apparatus includes at least one client module outputting an error detection signal, if an error is detected; and a controller for analyzing the error and controlling the client module to correct the error, if an error detection signal is received. An error correction apparatus and method of the present invention is provided with shadow registers or CRC registers for quickly detecting errors of status registers of a client module, whereby an error of the client module can be quickly detected and corrected.

Abstract: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For 1/3 rate, the relevant parameters are as follows: q=120, nldpc=64,800, kldpc=nBCH=21600, kBCH=21408 (12 bit error correcting BCH). For 1/4 rate, the LDPC code has the following relevant parameters: q=135, nldpc=64,800, kldpc=nBCH=16200, kBCH=16008 (12 bit error correcting BCH). For 2/5 rate, the following parameters exist: q=108, nldpc=64800, kldpc=nBCH=25920, kBCH=25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.

Abstract: The universal forward error-correction coding system provides adjustable code rates and coding gains to greatly benefit the design of many modern digital communications (data storage) systems. The channel encoding and decoding methods are universal such that a single encoder and a single decoder can be used to implement all the forward error-correction codes of different code rates. This universal forward error-correction coding system also includes a novel systematic code generation procedure that has the capability of generating many classes of codes that provide the best balance between coding gain performance and implementation complexity.

Abstract: System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix is partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning is performed in accordance with a rate allocation among the plurality of correlated data sources. A corresponding plurality of parity matrices are generated based respectively on the sub-matrices, where each parity matrix is useable to encode data from a respective one of the correlated data sources.

Abstract: An apparatus and method for transmitting and receiving a signal in a communication system are provided. The signal transmission apparatus generates a parity check matrix for an LDPC code in accordance with a code rate to be used and generates a codeword vector by encoding an information vector using the parity check matrix. When the code rate is a first code rate, the signal transmission apparatus generates a first parity check matrix as the parity check matrix for the LDPC code. When the code rate is the second code rate, the signal transmission apparatus generates a second parity check matrix supporting a second code rate lower than the first code rate by adding columns of a degree of 1 and columns of a degree of 2 to the first parity check matrix and generates the second parity check matrix as the parity check matrix for the LDPC code.

Abstract: Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.

Abstract: A memory element array includes plural memory elements capable of storing M-value data (M is a natural number not smaller than 2). Among first to M-th data, the first data gives a largest physical impact on memory elements. A data processing unit can execute a data process on an aggregate of program data stored in a data storing unit. It is determined that which of the first to the M-th data is least existing data, the number of pieces of which is the smallest in the aggregate of the program data. When the least existing data is other than the first data, the least existing data in the aggregate of program data is replaced with the first data, and the first data with the least existing data. When the least existing data is the first data, the aggregate of program data is maintained without any data replacement.

Abstract: A low density parity check codes decoder decodes an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder enables decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix. It stores therein Mbmax×Nbmax validity/invalidity flags, shift amounts of valid permutation matrices, a permutation matrix size in a processing target code, and the number of rows of a base matrix in the processing target code, determined depending on a check matrix for the processing target LDPC code, and generates column addresses and a row address to be given to column processing calculation sections and a row processing calculation section that perform calculation in accordance with a BP algorithm by utilizing the stored information, so that it can process an LDPC code for a smaller base matrix than the aforementioned base matrix as well.

Abstract: Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are not inserted, a dummy bit insertion portion inserts dummy bits into the information bits and shifts the decoding characteristic, so that the code rate assumes a value outside a specific range determined by the decoding characteristic after shifting. An encoding portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the encoding to generate a systematic code, and a rate matching portion, performs rate matching such that the size of the systematic code is equal to a size determined by the physical channel transmission rate, and transmits the systematic code.

Abstract: An encoder system includes a receive module that receives a data stream. A parity generation module generates parity bits based on the data stream and a tensor-product code. A parity insertion module combines the parity bits and the data stream to generate encoded bits.

Abstract: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of ? utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite.

Abstract: A bit adding part acquires RSSI as measured by an RSSI measuring part, and adds “1” to each bit of protected audio data of an audio vocoder, if the acquired RSSI is smaller than a predetermined threshold value. If the acquired RSSI is equal to or greater than the predetermined threshold value, the bit adding part adds the bits of additional data to the respective bits of the protected data of the audio vocoder. A frame recovery part separates upper and lower order bits of deinterleaved data, and determines, based on CRC, whether eight data parts as obtained by combining the lower order bits as separated are valid. If so, the frame recovery part combines the eight data parts as the additional data to recovery additional information. In this way, additional data can be efficiently transmitted, while error correction being performed in accordance with communication environment.

Abstract: An apparatus and method of encoding a block Low Density Parity Check (LDPC) code in a signal transmission apparatus is disclosed. The method includes generating a block LDPC codeword by encoding an information vector using a second parity check matrix when a code rate to be used in the signal transmission apparatus is a second code rate less than a code rate of a first parity check matrix as a first code rate.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: Apparatus and method for packet redundancy and recovery are disclosed. In a transmitter, parity packets are generated by executing exclusive OR between the corresponding data packets, and are transmitted along with the data packets to a receiver. In the receiver, lost data packets are found out and are recovered by executing exclusive OR between the corresponding data packets and the corresponding parity packets. This invention enhances the reliability of streaming data transmission using loss-recovery packets. Data packets are grouped and transmitted with redundant packets to allow the receiver to recover a lost packet within the group. This will minimize the need and therefore the time and delay to request a retransmission of the damaged or lost packets.

Abstract: A trellis encoding device includes a plurality of trellis encoders to perform trellis-encoding of a transport stream into which a supplementary reference signal (SRS) has been inserted, and performs a memory reset in a region that precedes an SRS; and a parity compensation unit to compensate for parities of the transport stream in accordance with values stored in memories included in the trellis encoders. The plurality of trellis encoders may be implemented in diverse types. The trellis encoding device can perform a memory reset selectively using the stored value of the memory and the inverted value thereof, or selectively using the stored value of the memory and a fixed value. By properly resetting the memory in processing the transport stream into which the SRS has been inserted, DC offset can be reduced.

Abstract: A transmitter includes a plurality of encoders configured to receive source bit streams from m information sources, each of the plurality encoders including identical (n,k) low-density parity check (LDPC) codes of code rate r=k/n, where k is a number of information bits and n is codeword length. An interleaver is configured to collect m row-wise codewords from the plurality of encoders, and a mapper is configured to receive m bits at a time column-wise from the interleaver and to determine an M-ary signal constellation point. A modulator is configured to modulate a light source in accordance with the output of the mapper at a transmission rate Rs/r (Rs—the symbol rate, r—-the code rate). A receiver and transmission and receiving methods are also disclosed.

Abstract: The embodiments of the invention provide a method, apparatus, etc. for a cache arrangement for improving RAID I/O operations. More specifically, a method begins by partitioning a data object into a plurality of data blocks and creating one or more parity data blocks from the data object. Next, the data blocks and the parity data blocks are stored within storage nodes. Following this, the method caches data blocks within a partitioned cache, wherein the partitioned cache includes a plurality of cache partitions. The cache partitions are located within the storage nodes, wherein each cache partition is smaller than the data object. Moreover, the caching within the partitioned cache only caches data blocks in parity storage nodes, wherein the parity storage nodes comprise a parity storage field. Thus, caching within the partitioned cache avoids caching data blocks within storage nodes lacking the parity storage field.

Abstract: It is an object of the present invention to provide a low density parity check codes decoder that can decode an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder according to the present invention is configured to enable decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix.