Abstract: Disclosed is an effective high-speed encoding method using a parity-check matrix proposed in an IEEE 802.1x standard for high-speed low-density parity-check encoding. In the prior art, encoding was performed by blocking and dividing the parity-check matrix of the LDPC code and through relevant matrix equations, or encoding was performed by an encoding apparatus that divides a matrix multiplication operation of a generated matrix acquired by using an arbitrary parity-check matrix of a quasi-cyclic (QC) LDPC code and information vectors into two sequential steps and implements each step as a cyclic shift-register.

Abstract: A cyclic comparison method for an LDPC decoder. The nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first level sequences. Next, pairs of two elements selected from the k elements are used to form k second level sequences. The preceding step is repeated k×?log2(k?1)? times to obtain k output results. Either of one first level sequences and one output results contains (k?1) elements. The first level sequences are compared with the output results to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new output results. The cyclic comparison method of the present invention needs only k×?log2(k?1)? comparisons to obtain output results. Thus, the present invention can reduce the number of basic operations and can apply to any input number.

Abstract: A method for generating a parity check matrix of a block LDPC code. The parity check matrix includes an information part corresponding to an information word and a first parity part and a second parity part each corresponding to a parity.

Abstract: Disclosed is an apparatus and method for transmitting/receiving a signal in a communication system, in which an MCS level or a modulation scheme to be used to an information vector to be transmitted is determined when the information vector is generated, and a codeword vector is generated by encoding the information vector in an encoding scheme corresponding to the determined MCS level or modulation scheme. Thus, a signal can be transmitted in such a manner as to have optimal performance for each MCS level or modulation scheme.

Abstract: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data.

Abstract: A method for error detection in a memory system. The method includes calculating one or more signatures associated with data that contains an error. It is determined if the error is a potential correctable error. If the error is a potential correctable error, then the calculated signatures are compared to one or more signatures in a trapping set. The trapping set includes signatures associated with uncorrectable errors. An uncorrectable error flag is set in response to determining that at least one of the calculated signatures is equal to a signature in the trapping set.

Abstract: A check matrix generating method of generating a check matrix (H) for decoding coded modulation data, which is encoded by a low-density parity check code and which is modulated by converting a-bit data (wherein a is a natural number) to b-bit data (wherein b is a natural number) wherein a is a modulation symbol unit, the method provided with: a check matrix generating process of generating the check matrix by determining each element such that the number of elements of 1 is less than or equal to one, out of a elements corresponding to data of the same modulation symbol in each of rows which constitute the check matrix.

Abstract: An apparatus and method of receiving a signal in a communication system are provided, in which a signal is received and decoded by a PPS scheme being an LDPC decoding scheme in which an order of performing a node operation is scheduled.

Abstract: A transmitting device of the present invention comprises an encoder (20), a transmitting unit (100) including a pulse generator (30) and a parallel-to-serial converter (50), a transmitting control unit (40), and an antenna (90). The pulse generator (30) comprises a first pulse train generator (31), a second pulse train generator (32), . . . and an n-th pulse train generator (33). A k-bit information bit train is inputted from the information signal source (10), The encoder (20) encodes the k-bit information bit train into an n-bit encoded bit train at a coded rate of (k/n). The pulse generator (30) generates n-piece repetitive pulse trains corresponding to the n-bit encoded bit train. The antenna (90) transmits the n-piece repetitive pulse trains as UWB-IR.

Abstract: A coding system for digital data includes a constrained encoder module that generates encoded data based on a first constrained code, a bit insertion module that inserts at least one bit location in the encoded data, an error correcting code (ECC) encoder module that generates ECC parity bits based on the at least one bit location and the encoded data, and an inner encoding module that generates inner-code parity bits based on the encoded data and programs the inner-code parity bits into the at least one bit location.

Abstract: In an encoding and/or decoding method utilizing a self-orthogonal Quasi-Cyclic (QC) code whose parity check matrix is expressed by at least one circulant matrix, a code sequence is generated which satisfies a check matrix. The check matrix is designed so that a column weight w of each circulant matrix is three or larger and a minimum hamming distance of the code is w+2 or larger.

Abstract: A variable code rate adaptive encoding/decoding method using LDDC code is disclosed, in which an input source data is encoded using the LDPC (low density parity check) code defined by a first parity check matrix configured with a plurality of submatrices. The present invention includes the steps of generating a second parity check matrix corresponding to a code rate by reducing a portion of a plurality of submatrices configuring a first parity check matrix according to the code rate to be applied to encoding an input source data and encoding the input source data using the second parity check matrix.

Abstract: A method for transmitting a signal in a signal transmission apparatus of a communications system including receiving an information vector, and encoding the information vector according to a zigzag B-LDPC encoding scheme to generate a zigzag B-LDPC codeword, thereby advantageously reducing the encoding complexity together with enhanced error correction capability.

Abstract: A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.

Abstract: A device adaptor that controls a disk, wherein a storage area is divided into a plurality of blocks, detects a block that includes a read error. Next, the device adaptor detects a write omission in blocks that are within a predetermined range from the block that includes the read error. To be specific, the device adaptor reads data from the blocks that are in the vicinity of the block that includes the unrecovered read error in a suspect disk. Next, the device adaptor reads from a redundant disk, data of a block that corresponds to the block that includes the unrecovered read error (data of block “B” in an example shown in FIG. 1) and compares the read data to the data read from the suspect disk to detect the write omission.

Abstract: Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the standard float-point sum-product algorithm (SPA), and can reduce the approximation error of min-sum algorithm (MSA) and have almost the same performance under 5 bits fix-point realization as the float-point sum-product algorithm (SPA).

Abstract: Integrated circuits, load boards and methods are disclosed, such as those associated with a memory testing system that includes an algorithmic pattern generator generating a pattern of command, address or write data digits according to an algorithm. In one such embodiment, the pattern of digits are applied to a frame generator that arranges the pattern of digits into a packet. The packet is then applied to a plurality of parallel-to-serial converters that convert the packet into a plurality of serial digits of a command/address packet or a write data packet, which are output through a plurality of bit lanes. The system might also include a plurality of serial-to-parallel converters receiving respective sets of digits of a read data packet through respective bit lanes. The read data packet is applied to a frame decomposer that extracts a pattern of read data digits from the packet. An error detecting circuit then determines if any of the received read data digits are erroneous.

Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

Abstract: A network communication device includes a host interface, which is coupled to communicate with a host processor, having a memory, so as to receive a work request to convey one or more data blocks over a network. The work request specifies a memory region of a given data size, and at least one data integrity field (DIF), having a given field size, is associated with the data blocks. Network interface circuitry is configured to execute an input/output (I/O) data transfer operation responsively to the work request so as to transfer to or from the memory a quantity of data that differs from the data size of the memory region by a multiple of the field size, while adding the at least one DIF to the transferred data or removing the at least one DIF from the transferred data.

Abstract: A method for error correction that includes receiving a bitstream, the bitstream comprising one or more bits, determining if the bitstream has one or more corrupt bits, determining one or more hypotheses representing an error pattern, and assigning a probability to each of the hypotheses, wherein the probability is determined based on one or more reference data.

Abstract: A method and apparatus are provided for a coding process of a communication signal. A 3-stripes parity-check matrix is generated from a parity-check matrix of a Gilbert low density parity-check code, where the parity-check matrix of the Gilbert low density parity-check code has a first stripe containing identity matrices and a second stripe containing cyclic permutation matrices. A third stripe is added to form a 3-stripes parity-check matrix, which may be applied to the coding process of information in a communication channel.

Abstract: Elements of a coding table which are error-free are found at S2. At S3, corresponding elements in an erasure information table are completed, indicating that the elements in the coding array are correct. A counter is initialized at Nmax, which is the maximum number of errors that can be corrected, at S4. At S5, the row of the erasure information table is scanned beginning from the first parity column for empty elements. Each empty parity date element of the erasure information table row is marked as incorrect at S7 For each such element, the counter is decremented at S8. At S9, the elements of the erasure information table are scanned from the first column of the application data and zero padding section for empty elements. At step S11, an empty element is marked as incorrect. At step S12, the counter is then decremented. It is determined at step S13 whether or not the counter is equal to zero.

Abstract: An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract: A module for transmitting sets of data bits to another module via a communication bus using dual-rail encoding is provided that has a reduced switching activity. The module comprises bus invert coding means adapted to compare a set of data bits with a preceding set of data bits to determine an indication of the number of transitions required to transmit the set of data bits; invert the set of data bits prior to transmission if it is determined that the number of transitions required to transmit the set of data bits is greater than half the total number of bits in the set of data bits; and provide an indication of whether the set of data bits has been inverted; the module also comprising means adapted to generate respective copies of the data bits in the set of data bits; and means adapted to transmit to the other module, via the communication bus, the set of data bits, their respective copies and the indication of whether the set of data bits has been inverted.

Abstract: Error detection using parity compensation in binary coded decimal (BCD) and densely packed decimal (DPD) conversions, including a computer program product having a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving formatted decimal data in a first format, the formatted decimal data consisting of a DPD format data or a BCD format data. One or more first parity bits are generated by converting the received data into a second format of the formatted decimal data, and by determining the parity of the data in the second format. One or more second parity bits are generated directly from the received data. An error flag is set to indicate an error in the data in the second format in response to the first parity bits not being equal to the second parity bits.

Abstract: A prepended parity data encoder is loaded with sets of data and constant data, which are used for parity calculation. A shift circuit shifts each of the plural sets of data and the constant data, one bit at a time in parallel. When the constant data is output from the shift circuit, a parity generator dynamically generates prepended parity data based on the constant data and the plural sets of data.

Abstract: A method and apparatus is described herein for tracking errors for one of a plurality of lanes in a link, tracking errors for the link, and in the case of a root complex, tracking error correction messages. This information is used to determine the suitability for use of a lane and to determine if correction action is needed. In one embodiment, this method and apparatus is used with PCI Express interconnects.

Abstract: A method implemented in a digital subscriber line (DSL) system is described for minimizing a misdetection probability at a far-end coded message receiver during transmission of a coded message. The method comprises jointly determining, at the far-end coded message receiver, a P matrix and a modulation scheme. The method further comprises encoding a message into a coded message with a systematic linear block code, the systematic linear block code having a generator matrix [I P], where I represents a linear block code component identity matrix and P represents the determined P matrix. The method also comprises modulating the encoded message to one or more tones forming a discrete multi-tone (DMT) symbol according to the determined modulation scheme.

Abstract: Embodiments of the present invention provide a method, system, and computer program product for optimizing I/O operations performed by a storage server operating on behalf of multiple clients to access data on a plurality of storage devices (disks). Embodiments of the present invention eliminate the need for selected read operations to write new data to physical data blocks by zeroing the physical data blocks to which new data will be written. Additionally, the need for reading old parity to compute new parity is eliminated. Instead, new parity is computed from the data to be written without the need of old parity or the storage server sends a command to a disk that stores parity. A module implemented at the disk that stores parity executes the command without reading, by the storage server, old parity. Eliminating the need for reading old data and for reading old parity eliminates some rotation latency and improves overall system's performance.

Abstract: Disclosed is a device and method for coding a block low density parity check (LDPC) code having a variable length. The a device and method include receiving an information word; and coding the information word into a block LDPC code according to a first parity check matrix or a second parity check matrix depending on a length to be applied when generating the information word into the block LDPC code.

Abstract: A communication channel including Reed-Solomon (RS) and single-parity-check (SPC) encoding/decoding. Multiple RS codewords are combined and then SPC encoded into an RS/SPC array. A soft-input soft-output (SISO) channel detector detects the RS/SPC encoded bits and provides soft (reliability) information on these bits. A combined RS and SPC error correction block provides a recovered user output. An iterative soft input decoding algorithm combines RS and SPC error correction.

Abstract: A RAID system is provided for detecting and correcting dropped writes in a storage system. Data and a checksum are written to a storage device, such as a RAID array. The state of the data is classified as being in a “new data, unconfirmed” state. The state of written data is periodically checked, such as with a timer. If the data is in the “new data, unconfirmed” state, it is checked for a dropped write. If a dropped write has occurred, the state of the data is changed to a “single dropped write confirmed” state and the dropped write error is preferably corrected. If no dropped write is detected, the state is changed to a “confirmed good” state. If the data was updated through a read-modified-write prior to being checked for a dropped write event, its state is changed to an “unquantifiable” state.

Abstract: A parity engine for use in a storage virtualization controller includes a control unit being a control kernel of the parity engine; a control unit buffer serving as a data buffer of the control unit and storing map tables required for operations; at least one XOR engine being started by the control unit and used to select data from a data stream according to the map tables stored in the control unit buffer for performing XOR operations; and at least one data buffer serving as the data buffer of the XOR engine in the operating process.

Abstract: Low density parity check (LDPC) codes (LDPCCs) have an identical code blocklength and different code rates. At least one of the rows of a higher-rate LDPC matrix is obtained by combining a plurality of rows of a lower-rate LDPC matrix with the identical code blocklength as the higher-rate LDPC matrix.

Abstract: A method of communicating over an H1 Fieldbus network is provided. The communication over the H1 Fieldbus network employs an advanced form of error correction. In one embodiment, the advanced form of error correction utilizes low-density parity check codes; while in another embodiment, the advanced error correction employs turbo codes. The use of the advanced error correction with the H1 foundation Fieldbus network allows for higher data transmission speeds than 31.25 kbps and/or lower signaling levels than used currently.

Abstract: A memory card including a word line control portion configured to perform control of applying intermediate voltages made up of a first intermediate voltage lower than a center voltage of four threshold voltage distributions and a second intermediate voltage higher than the center voltage to the memory cell, a logarithmic likelihood ratio table memory portion configured to store 9-level logarithmic likelihood ratios based on read voltages, and a decoder configured to perform decoding processing on the data read using the logarithmic likelihood ratio stored in the logarithmic likelihood ratio table memory portion.

Abstract: A parallel dynamical system for computing sparse representations of data, i.e., where the data can be fully represented in terms of a small number of non-zero code elements, and for reconstructing compressively sensed images. The system is based on the principles of thresholding and local competition that solves a family of sparse approximation problems corresponding to various sparsity metrics. The system utilizes Locally Competitive Algorithms (LCAs), nodes in a population continually compete with neighboring units using (usually one-way) lateral inhibition to calculate coefficients representing an input in an over complete dictionary.

Abstract: Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.

Abstract: System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix is partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning is performed in accordance with a rate allocation among the plurality of correlated data sources. A corresponding plurality of parity matrices are generated based respectively on the sub-matrices, where each parity matrix is useable to encode data from a respective one of the correlated data sources.

Abstract: A NAND flash memory device performing an error detecting and data reloading operation during a copy back program operation is provided. The device includes a cell array having a plurality of planes and a parity cell array having a plurality of parity planes. Each of the parity planes stores a parity of each of the planes. Additionally, the device includes a parity generating and parity column selecting circuit generating a new parity about reloaded data from an outside during a copy back program operation, and storing the new parity on a parity plane corresponding to a plane on which the reloaded data is stored.

Abstract: A MIMO transmitter comprises a scrambler; an encoder parser responsive to the scrambler; a forward error correction encoder responsive to the encoder parser, wherein the encoder applies a parity check matrix derived from a base matrix; an interleaver responsive to the forward error correction encoder; a QAM mapping module responsive to the interleaver; an inverse fast Fourier transform module responsive to the QAM mapping module; and an output module responsive to the inverse fast Fourier transform module.

Abstract: An apparatus and method for decoding a Low Density Parity Check (LDPC) code having a maximum error correction capability and an error detection capability. In the apparatus, a decoder receives a signal, and decodes the received signal according to a second parity check matrix having parity check expressions obtained by selecting a predetermined number of dependent parity check expressions among dependent parity check expressions generated by combining, with a predetermined scheme, parity check expressions representing rows of a first parity check matrix obtained by encoding information data into a block code having an optimum minimum distance considering a predetermined coding rate, and adding the selected dependent parity check expressions to the parity check expressions of the first parity check matrix. An error detector determines if there is an error in a signal output from the decoder.

Abstract: A semiconductor circuit includes a parity bit adding circuit configured to add a parity bit to a data to be read by a CPU; a register configured to hold the data with the parity bit; and a parity check circuit configured to execute a parity check of said data with said parity bit held in said register, and to issue a parity error interrupt when a parity error is detected. A parity bit inverting circuit inverts said parity bit held in said register in response to completion of said parity check.

Abstract: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For a rate 3/5 code, the approach provides a degree profile that yields reduced memory requirements for storage of the edge values without significantly affecting the performance with respect to an “unmodified” rate 3/5 code. The relevant parameters for the reduced memory LDPC codes are as follows: q=72, nldpc=64800, kldpc=nBCH=38880, kBCH=38688. The above approach has particular application in digital video broadcast services over satellite.

Abstract: A semiconductor memory device includes a parity generation circuit which generates a parity bit corresponding to a first number of data bits, a memory cell array including memory cells, and having first and second areas, the first area storing data, the second area storing the parity bit, a syndrome generation circuit which generates a syndrome bit for correcting an error in read data which are read from the first area, has the first number of data bits and corresponds to the parity bit read from the second area, based on the parity bit and the read data, and a parity correction circuit which corrects the parity bit generated by the parity generation circuit. The parity generation circuit generates the parity bit for data which includes input data and a part of the read data.

Abstract: A decoder may perform node data reordering for bit node processing and node data reordering for bit node to check node interconnections. The decoder may also utilize a single barrel shifting operation on data read from an edge memory for bit node processing or check node processing during a memory read operation. The decoder may also utilize a single format conversion on data read from an edge memory for bit node processing or check node processing. The decoder may also utilize a simplified check node process for check node processing.

Abstract: A method for generating a parity check matrix to decode a plurality of underdetermined nodes, includes the steps of: determining a plurality of specific nodes according to a predetermined parity check matrix; determining a plurality of weightings corresponding to the plurality of specific nodes; and sorting the plurality of specific nodes according to the plurality of weightings to generate the parity check matrix to store in a storage device.

Abstract: A decoder for decoding low-density parity-check codes includes a first calculator that calculates ??rRml, for each parity check equation, at iteration i?1. A second calculator calculates ??rQ?m, for each parity check equation, at iteration i. ??rQ?m represents information from bit node I to equation node m, one for each connection. ??rRml represents information from equation node m to bit node I, one for each connection. The first calculator is responsive to the second calculator.

Abstract: An embodiment of the present invention provides an apparatus, comprising a transceiver capable of a unified quasi-cyclic low-density parity-check structure for variable code rates and sizes using a unified base matrix definition. This base matrix definition may be a concatenation of multiple square matrices Sm×Rm=(Sm×mR|Sm×mR?1| . . . |Sm×m3|Sm×m2|Sm×m1) and the base matrix for rate (r?1)/r may be Sm×rm=(Sm×mr|Sm×mr?1| . . . |Sm×m3|Sm×m2|Sm×m1) for r=2, 3, . . . , R.