Abstract: In a decoder having an improved LLR (log-likelihood-ratio) update method is provided. The method comprising the steps of: providing a parity check matrix; and using merely a set of parameters on a row of the parity check matrix instead of data of the whole non-zero elements of the parity check matrix free from at least one shifting action after each row updating; thereby saving memory space and process time.

Abstract: An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.

Abstract: A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The expansion of the base matrix Hb uses identical submatrices for 1s in each column of the second part H?b2, and the expansion uses paired submatrices for an even number of 1s in hb.

Abstract: There is provided a parity check encoder (100) comprising a data memory (PROM) configured for storing input data, a calculation/parity result storage means (CPRSM), and a selector/serializer means (SSM). The CPRSM (104, 106) is coupled to the PPDM (102) and is configured to calculate parity bits in parallel using input data and information contained in a parity check matrix H. The SSM (108) is coupled to the PPDM and CPRSM. The SSM is configured to generate an encoded output sequence using the input data and parity bile. The matrix H is formed of a plurality of sub-matrices. Each sub-matrix of the sub-matrices is an all zero (0) matrix, an identity matrix, or a circular right shifted version of the identity matrix, A portion B of the matrix H includes a plurality of rows having two (2) ones (1), except for a first row which includes a single one (1).

Abstract: A method for decoding a noisy codeword (y) received from a communication channel as the result of a LDPC codeword (b) having a number (N) of codeword bits is disclosed. Each codeword bit consists of k information bits and M parity check bits. The product of the LDPC codeword b and a predetermined (M×N) parity check matrix H is zero (H*bT=0) wherein the parity check matrix H represents a bipartite graph comprising N variable nodes (V) connected to M check nodes (C) via edges according to matrix elements hij of the parity check matrix H.—The method comprises receiving the noisy LDPC codeword (y) via said communication channel and calculating for each codeword bit (V) of said transmitted LDPC codeword (b) an a-priori estimate (Qv) that the codeword bit has a predetermined value. The method also comprises calculating iteratively messages on all edges of said bipartite graph according to a serial schedule and a message passing computation rule.

Abstract: Techniques are described for detecting error events in codewords detected from data signals transmitted via a communication system. The error events are detected with an error detection code that corresponds to one or more dominant error events for the communication system. The invention develops a class of error detection codes to detect specific error events of known types. In some embodiments, the communication system comprises a recording system. The error detection coding method may be used in conjunction with error correction processing to provide substantial performance gain compared to conventional parity-based post processing methods. For example, the error correction processing may include one or more correlation filters that correspond to the one or more dominant error events for the communication system. A correction module may correct the codeword based on a type of the detected error event and a location of the detected error event in the codeword.

Abstract: The invention provides a channel coding method for encoding systematic data for transmission in a communication channel. The systematic data has a runlength constraint. In the method, data words are permuted. Error codes are generated based upon the permuted data words. The error codes are appended to original data words to form channel input for serial transmission in the communication channel. The number of error code bits is limited to ensure the channel input meets the runlength constraint. The error code can be a parity check bit.

Abstract: In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects nonconformity of the index table information in advance by using results in which the Galois field multiplying table is indexed from different directions constructed by the longitudinal direction and the transversal direction. Data and parity for making the multiplying calculation are decomposed into plural data and parities by using this table check circuit, and index table information different from each other are allocated to these data and parities. Thus, a longitudinal index table making circuit and a transversal index table making circuit themselves are checked.

Abstract: LDPC (Low Density Parity Check) decoder employing distributed check into variable node architecture. A means of decoding processing is presented in which at least one portion of the check node processing functionality is actually integrated into the variable/bit node processing functionality (e.g., distributed check node embodiment). In alternative embodiments, at least one portion of the variable/bit node processing functionality is actually integrated into the check node processing functionality (e.g., distributed variable/bit node embodiment). In even other embodiments, some check node processing functionality is moved and integrated into the variable/bit node processing functionality, and some variable/bit node processing functionality is also moved and integrated into the check node processing functionality (e.g., combined distributed embodiment).

Abstract: In a decoder having a predetermined decoder structure for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes is provided. An associated method is provided. The method comprises the steps of: providing a memory for the decoding with the memory size proportional to the number of circularly shifted-identity matrices I (t); and providing a number M for both row update unit numbers and column-update unit numbers. Whereby an improved architecture having an improved logic and the memory is provided such that an improved throughput, power consumption, and memory area are achieved.

Abstract: An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.

Abstract: An optical communication system includes a bit-interleaved coded modulation (BICM) coder; and a low-density parity-check (LDPC) coder coupled to the BICM coder to generate codes used as component codes and in combination with a coherent detector.

Abstract: Digital communication coding methods are shown, which generate certain types of low-density parity-check (LDPC) codes built from protographs. A first method creates protographs having the linear minimum distance property and comprising at least one variable node with degree less than 3. A second method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of certain variable nodes as transmitted or non-transmitted. A third method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of the status of certain variable nodes as non-transmitted or set to zero.

Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.

Abstract: A module for transmitting sets of data bits to another module via a communication bus using dual-rail encoding is provided that has a reduced switching activity. The module comprises bus invert coding means adapted to compare a set of data bits with a preceding set of data bits to determine an indication of the number of transitions required to transmit the set of data bits; invert the set of data bits prior to transmission if it is determined that the number of transitions required to transmit the set of data bits is greater than half the total number of bits in the set of data bits; and provide an indication of whether the set of data bits has been inverted; the module also comprising means adapted to generate respective copies of the data bits in the set of data bits; and means adapted to transmit to the other module, via the communication bus, the set of data bits, their respective copies and the indication of whether the set of data bits has been inverted.

Abstract: A decoder for decoding low-density parity-check codes comprises a first calculator to calculate LLrRml, for each parity check equation, at iteration i?1. A detector detects LLrRml, at iteration i, in response to the first calculator. A second calculator calculates LLrQLm, for each parity check equation, at iteration i in response to the detector. LLrQLm represents information from bit node l to equation node m, one for each connection. LLrRml represents information from equation node m to bit node l, one for each connection. The first calculator is responsive to the second calculator.

Abstract: In order to generate a parity of output data from a priority encoder without increasing processing time or making the circuitry complex, the present invention a first level generator having a plurality of first component circuits arranged in parallel, into each of which one of a plurality of sets of a specific number of bits of the binary data in sequence from the most significant bit is input and each of which generates and outputs a first signal for parity generation of bit data of the specific number of bits and a second signal representing whether or not the entire bit data of the specific number of bits is “0s” or “1s”; and a second level generator generating the parity of the binary data based on the first signal and the second signal from each of said first component circuits of said first level generator.

Abstract: A circuit outputs, upon receipt of data and a parity of the data, count information on the number of bits in the data represented as a base-n number (n: a natural number equal to or larger than 2) and the parity of the count information. The circuit includes a determining unit and an inverting unit. The determining unit determines that the number of bits in the data represented as a base-n number is a specific value. The inverting unit outputs, as the parity of the count information, any one of a value of the parity of the data and an inverted value of the parity depending on a result of determination by the determining unit.

Abstract: LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until a sufficient degree of precision is achieved. The symbol node updating of the bit edge messages involves using symbol metrics corresponding to the symbol being decoded as well as the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages involves using the bit edge messages most recently updated by symbol node updating. The symbol node updating also involves computing possible soft symbol estimates for the symbol during each decoding iteration.

Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Abstract: Efficient design to implement min**/min**? or max**/max**? functions in LDPC (Low Density Parity Check) decoders. When compared to prior art approaches, the novel and efficient implementation presented herein allows for the use of substantially less hardware and surface area within an actual communication device implemented to perform these calculations. In certain embodiments, the min** processing (and/or max** processing) is implemented to assist in the computationally intensive calculations required to decoded LDPC coded signals. In one instance, this is operable to assist in check node processing when decoding LDPC coded signals. However, the efficient principles and architectures presented herein may be implemented within other communication device types to decode other types of coded signals as well.

Abstract: A method of encoding and decoding using an LDPC code is disclosed, by which a memory for storing a parity check matrix necessary for the encoding or decoding using the LDPC code and calculation amount and complexity necessary for the encoding or decoding can be reduced. The present invention includes a step of encoding an input data using a parity check matrix H having a configuration of H=[Hd|Hp] (Hd is (n?k)×k dimensional, Hp is (n?k)×(n?k) dimensional, k is a bit number of the input data, and n is a bit number of a codeword), wherein if the Hd comprises a plurality of sub-matrices, each of the sub-matrices has predetermined regularity in a row or column weight.

Abstract: An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates.

Abstract: An apparatus and method for transmitting and receiving a signal in a communication system are provided. The signal transmission apparatus generates a parity check matrix for an LDPC code in accordance with a code rate to be used and generates a codeword vector by encoding an information vector using the parity check matrix. When the code rate is a first code rate, the signal transmission apparatus generates a first parity check matrix as the parity check matrix for the LDPC code. When the code rate is the second code rate, the signal transmission apparatus generates a second parity check matrix supporting a second code rate lower than the first code rate by adding columns of a degree of 1 and columns of a degree of 2 to the first parity check matrix and generates the second parity check matrix as the parity check matrix for the LDPC code.

Abstract: An apparatus, system, and method are disclosed for a front-end, distributed redundant array of independent drives (“RAID”). A storage request receiver module receives a storage request to store object or file data in a set of autonomous storage devices forming a RAID group. The storage devices independently receive storage requests from a client over a network, and one or more of the storage devices are designated as parity-mirror storage devices for a stripe. The striping association module calculates a stripe pattern for the data. Each stripe includes N data segments, each associated with N storage devices. The parity-mirror association module associates a set of the N data segments with one or more parity-mirror storage devices. The storage request transmitter module transmits storage requests to each storage device. Each storage request is sufficient to store onto the storage device the associated data segments. The storage requests are substantially free of data.

Abstract: A generic RAID engine system accepts an access request, accepts a metadata input comprising a layout description and, optionally, a plurality of resource optimization objectives, accepts a dynamic input comprising a dynamic state of an I/O stack comprising the generic RAID engine and a fault configuration of a plurality of storage devices in the I/O stack, and accepts RAID code input comprising information about the RAID code used by the I/O stack. The metadata input, the dynamic input, and the RAID code input are utilized to transform the access request into individual device reads and individual device writes such that RAID code relationships for the storage devices are maintained at all times. An optional optimizer module selects strategies that meet the resource optimization objectives.

Abstract: A variable code rate adaptive encoding/decoding method using LDDC code is disclosed, in which an input source data is encoded using the LDPC (low density parity check) code defined by a first parity check matrix configured with a plurality of submatrices. The present invention includes the steps of generating a second parity check matrix corresponding to a code rate by reducing a portion of a plurality of submatrices configuring a first parity check matrix according to the code rate to be applied to encoding an input source data and encoding the input source data using the second parity check matrix.

Abstract: In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects nonconformity of the index table information in advance by using results in which the Galois field multiplying table is indexed from different directions constructed by the longitudinal direction and the transversal direction. Data and parity for making the multiplying calculation are decomposed into plural data and parities by using this table check circuit, and index table information different from each other are allocated to these data and parities. Thus, a longitudinal index table making circuit and a transversal index table making circuit themselves are checked.

Abstract: A coding circuit for generating an error correction code from digital data to be recorded in a record medium, includes a temporal storage memory which stores the digital data, a buffer manager which successively reads the digital data m bytes at a time from said temporal storage memory in a main scan direction and in a sub-scan direction, a PI parity unit which processes the digital data m bytes at a time as the m bytes are supplied from said buffer manager so as to generate a PI sequence parity based on the digital data for one row extending in the main scan direction, and a PI parity unit which includes m operation units, each of which processes a corresponding one byte of the digital data as m bytes of the digital data are supplied from said buffer manager so as to generate a PO sequence parity based on the digital data for one column extending in the sub-scan direction.

Abstract: Code shortening techniques are used to achieve a variety of code lengths and code rates for Euclidean geometry low density parity check (EG-LDPC) codes.

Abstract: A method for generating a non-binary Low Density Parity Check (LDPC) code. The method includes generating non-binary identity matrixes so as to satisfy at least one condition, wherein the non-binary LDPC code is defined by a parity check matrix, and the parity check matrix includes a plurality of sub-matrixes, which are divided into zero matrixes and the non-binary identity matrixes.

Abstract: A system comprising a plurality of channel detectors (CDs) receiving quantized and equalized ISI channel information indicative of an LDPC codeword. The channel information is split for input to the CDs, such that each CD receives channel information indicative of a portion of the LDPC codeword. Each CD outputs at least first soft information for bits of the codeword portion of that CD. The first soft information for the codeword is received by an LDPC decoder, which uses the soft information to produce a user bit sequence and second soft information about the user bit sequence. The system can cause the second soft information to be input to the plurality of CDs, such that iterative processing can occur for the codeword. Other aspects include a system providing clocking of one or more CDs at a frequency selected to balance codeword throughput of the CDs with codeword throughput of an LDPC decoder clocked by a second clock, and methods according to each system.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

Abstract: The present invention discloses a cyclic comparison method for an LDPC decoder, which applies to the comparators used in an LDPC decoder. According to the cyclic comparison algorithm of the present invention, the nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first series. Next, pairs of two elements selected from the k elements are used to form k second series. The preceding step is repeated k×log2(k?1) times to obtain k completion series. Either of one first series and one completion series contains (k?1) elements. The first series are compared with the completion series to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new completion series. The cyclic comparison method of the present invention needs only k×log2(k?1) comparisons to obtain completion series.

Abstract: Methods, apparatuses and systems for physical link error data capture and analysis.

Abstract: According to an aspect of an embodiment, a method of storing user data (UD) with parity data (PD) for correcting the UD in a storage apparatus comprising disk units, each of the disk units storing data in data blocks(DBs), each of the DBs storing the UD or associated PD and position information(PI) indicative of the location of the DBs, comprising: obtaining the UD, dividing the UD into UD blocks (UDBs) which are adapted to be stored in the DBs, and determining which UDBs are to be stored into which DBs, respectively; determining PI of the DBs for storing the UDBs; generating PD for a group of UDBs and associated PI by parity operation using a weighting function to the UDBs and the PI; determining PI for the PD for said group by modifying a part of the PD; and storing the group of the UDBs, associated PI, and the PD.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.

Abstract: Provided are an apparatus and method for receiving a signal in a communication system, in which a signal is received and decoded by setting an offset indicating a start position of a node operation for each block column of a parity check matrix of a Low Density Parity Check (LDPC) code and scheduling an order of performing the node operation on a Partial Parallel Scheduling (PPS) group basis. Here, the parity check matrix includes p×L rows and q×L columns, the p×L rows are grouped into p block rows, the q×L columns are grouped into q block columns, and each PPS group includes one column from each of the q block columns.

Abstract: A coding circuit for generating an error correction code from digital data to be recorded in a record medium, includes a buffer manager which successively reads the digital data m bytes at a time from a temporal storage memory in a main scan direction and in a sub-scan direction, a PI parity unit which processes the data m bytes at a time, as the m bytes are supplied from the buffer manager, and generates a PI sequence parity based on the data for one row extending in the main scan direction, and a PO parity unit which includes in operation units, each of which processes a corresponding byte of the data, as m bytes of the digital data are supplied from the buffer manager, and generates a PO sequence parity based on the data for one column extending in the sub-scan direction.

Abstract: Provided are methods for encoding and decoding low-density parity-check (LDPC) codes and a method for forming an LDPC parity check matrix. The method for forming the LDPC parity check matrix, includes the steps of: preparing a plurality of parity check matrixes; and selecting a parity check matrix having maximum performance from the prepared parity check matrixes, wherein the parity check matrix has a degree distribution G(x) that meets an equation, G ? ( x ) = ? k = 2 d i - 1 ? a k ? x k + ? k = d i d max ? C ? ? k - ? ? x k ? ? or ? ? G ? ( x ) = ? ? k = 2 d max ? C ? ( k + ? ) - ? ? x k , where, ak is a parameter that corresponds to the probability that nodes of the graph have a degree k, C is a parameter that is determined by a normalization condition, G(1)=1, and ?, ? are parameters that is optimized through numerical calculations.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. In an aspect, LDPC encoding and decoding of packets of varying sizes may be supported with a set of base parity check matrices of different dimensions and a set of lifting values of different powers of two. A base parity check matrix G of dimension mB×nB may be used to encode a packet of kB=nB?mB information bits to obtain a codeword of nB code bits. This base parity check matrix may be “lifted” by a lifting value of L to obtain a lifted parity check matrix H of dimension L·mB×L·nB. The lifted parity check matrix may be used to encode a packet of up to L·kB information bits to obtain a codeword of L·nB code bits. A wide range of packet sizes may be supported with the set of base parity check matrices and the set of lifting values.

Abstract: Basic matrix based on irregular LDPC codes, codec and generation method thereof. The codec includes an encoding/decoding operation module and a basic matrix storage module. In the stored basic matrix Hb, for all girths with length of 4, any element of i, j, k or l constituting the girths in anti-clockwise or clockwise always satisfies inequality: mod(i?j+k?l, z)?0, wherein z is the extension factor. When generating the basic matrix, firstly the number of rows M, number of columns N, and weight vectors of the rows and columns are determined, an irregularly original basic matrix is constructed; then the position of ‘1’ is filled by a value chosen from set {0, 1, 2, . . . , z?1} to obtain the basic matrix Hb, which is made to satisfy the above-mentioned inequality. The basic matrix Hb obtained by storing, which is configured with corresponding encoding/decoding operation module, constitutes the desired encoder/decoder.

Abstract: An LDPC code encoding apparatus includes: a code matrix generator for generating and transmitting a parity-check matrix comprising a combination of square matrices having a unique value on each row and column thereof; an encoding means encoding block LDPC codes according to the parity-check matrix received from the code matrix generator; and a codeword selector for puncturing the encoded result of the encoding means to generate an LDPC codeword. The code matrix generator divides an information word to be encoded into block matrices having a predetermined length to generate a vector information word. The encoding means encodes the block LDPC codes using the parity-check matrix divided into the block matrices and a Tanner graph divided into smaller graphs in correspondence to the parity-check matrix.

Abstract: Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**? (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†? (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.

Abstract: An apparatus and method to encode a block Low Density Parity Check (LDPC) code in a signal transmission apparatus is disclosed. The method includes generating a first block LDPC codeword by encoding an information vector using a first parity check matrix when a code rate to be used in the signal transmission apparatus is a first code rate as a code rate of the first parity check matrix, and generating a second block LDPC codeword by encoding the information vector using a second parity check matrix when the code rate to be used in the signal transmission apparatus is a second code rate as a code rate of the second parity check matrix.

Abstract: Disclosed is a transmission device in a communication system in which a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deleting the dummy bits from the results of the systematic encoding is transmitted and, on the receiving side, the dummy bits which had been deleted on the transmitting side are inserted into the received systematic code, and then decoding is performed. In this transmission device, a dummy bit insertion portion decides the size of the dummy bits to be inserted into the information bits based on a specified code rate or based on the physical channel transmission rate, and uniformly inserts dummy bits of this size into the information bits; a systematic code generation portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the systematic encoding to generate a systematic code, which is transmitted.

Abstract: The present invention provides an LDPC encoder, a channel encoder of a portable internet system including the LDPC encoder, and an encoding method thereof. The LDPC encoder according to the present invention generates a Costas array, shifts it, generates an analogous circulation parity check matrix having a repeated pattern from the shifted Costas array, and performs encoding by using the parity check matrix. With this LDPC encoder, complexity of encoding system may be reduced.

Abstract: Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are not inserted, a dummy bit insertion portion inserts dummy bits into the information bits and shifts the decoding characteristic, so that the code rate assumes a value outside a specific range determined by the decoding characteristic after shifting. An encoding portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the encoding to generate a systematic code, and a rate matching portion, performs rate matching such that the size of the systematic code is equal to a size determined by the physical channel transmission rate, and transmits the systematic code.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and precoding the encoded information. The precoding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

Abstract: A method for storing streaming media data packets in a cache includes receiving a first streaming media data packet from a streaming media server, the first streaming media data packet comprising first header data and first payload data, pre-determining a first payload checksum in response to at least a portion of the first payload data, storing at least a portion of the first header data and the first payload checksum as first packet meta data in a first data object in the cache memory, and storing the first payload data in the first data object in the cache memory, wherein the first data object is directly addressable in the cache memory via an associated object handle.