Abstract: Disclosed is a density evolution algorithm based on a refined definition of node and edge densities for different parts of the code. In particular, density functions ƒV(1)(i) and ƒV(2)(i) of the output edges of the variable nodes with degree i within different codeword regions w1 and we, respectively, are defined and then calculated. Further, density functions ƒC(1)(j) and ƒC(2)(j) of the output edges for check nodes with degree j within codeword regions w1 and we, respectively, are defined and then calculated. Mixture density functions of output check edges connecting variable nodes in the first codeword region and the second codeword region are then calculated to determine an LDPC code design.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and preceding the encoded information. The preceding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

Abstract: A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.

Abstract: A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.

Abstract: A method of generating structured irregular LDPC codes for a wireless network such as a wireless local area network (WLAN) system, allowing systematic generation of improved code ensembles using density evolution, and providing essentially the best tradeoff between decoding threshold and decoding complexity. Such an LDPC code has a higher diversity order for MIMO systems, with better built-in interleaving capability. Further, the code dimension can be tailored to 802.11n system parameters such as the number of sub-carriers and delay. The code also provides an improved girth control scheme, provides flexible length with different expanding factors, and supports simple encoding and shortening for multiple rates.

Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

Abstract: Method and apparatus for generating codewords with variable length and redundancy from a single Low-Density Parity-Check (LDPC) code with variable length input words. A mother code for encoding data words is generated based on a parity-check matrix, wherein the mother code is adjusted to reflect the size of the data word to be encoded. A generator matrix applies the mother code to data words to produce codewords for transmission. In one embodiment, a reduction criteria is determined and the size of the generator matrix reduced in response. The corresponding parity-check matrix is applied at the receiver for decoding the received codeword.

Abstract: A computer system including: at least one host computer, a storage system for storing data used in the host computer, and a managing computer for managing storing the data in the storage system which are connected to each other with a network. The managing computer monitors the journal volume which is a storing destinations of the journal, in a case that the journal is stored in the journal volume in parallel, when it is detected that the storing destination of the journal changes from one of the groups into which the journal is just stored to another group, transmits an instruction to the storage system to change the storing destination of the journal to another group.

Abstract: A dual parity hardware architecture that enables data to be read from each sector only once and performs both the P parity and Q parity from the single data source. The Q parity calculator provides parallel processing capabilities so that multiple parity operations are performed on the same sector simultaneously. The dual parity hardware architecture provides flexibility in restoring data, generating parity, and updating parity for differing data sector sizes.

Abstract: An architecture and method for executing write commands in a storage array is disclosed. The data strips of the data stripes of the storage array each include a parity check bit. The parity strip of each stripe includes a plurality of parity check bits, each of which is uniquely associated with one of the data strips of the stripes. The inclusion within each data stripe of parity bits associated with each data strip and the party strip provides a method for identifying a corrupted or degraded data condition that occurs as a result of a server failing fails during a write command.

Abstract: An on-the-fly error checking and correcting system and method of supporting a non-volatile memory processes data using an on-the-fly error correction method to be performed between a temporary memory and a flash memory. The flash memory stores actual data read from the temporary memory and parity generated on-the-fly in a write mode, and transmits the stored data to the temporary memory, computes a syndrome from the stored data on-the-fly, and generates an error correction information signal according to the result of computing in a read mode. Thus, error correction may only be selectively performed.

Abstract: An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets of Galois Field engine circuits which are used in the XOR circuit, is one which can generate high efficient parity engine and high efficient flow data route and which at the same time correct the three or more failures during operation of the RAID device.

Abstract: In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects nonconformity of the index table information in advance by using results in which the Galois field multiplying table is indexed from different directions constructed by the longitudinal direction and the transversal direction. Data and parity for making the multiplying calculation are decomposed into plural data and parities by using this table check circuit, and index table information different from each other are allocated to these data and parities. Thus, a longitudinal index table making circuit and a transversal index table making circuit themselves are checked.

Abstract: Data communication, with improved error detection, of a signal having a plurality of data blocks, by: error checking a received data block in a first sequence using a first polynomial, beginning with a first predetermined initial error checking state, producing a first CSUM; error checking the received data block in a second sequence using a second polynomial, using the first CSUM as a second predetermined initial error checking state, producing a second CSUM; comparing the second CSUM to the first predetermined initial error checking state to detect errors in the data communication; and repeating the above steps for sequential data blocks of the data communication, wherein the first polynomial is an inverse of the second polynomial.

Abstract: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of ? utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite.

Abstract: Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is disclosed. Error correction coding according to a fixed-block size code, such as low density parity check (LDPC) coding, is implemented. A specific LDPC code with excellent error rate performance is disclosed.

Abstract: A system (e.g., Fiber Channel Error Detecting Code (FC-EDC)) that maps the “standard” Hamming codes onto the bits of a 33-bit control block is provided. The system employs a “rotation” of the check positions in a two-dimensional parity-check matrix for the FC-EDC. The specification discloses a computer-implemented program to test further modifications and permutations of the “standard” distance-4 parity-check matrix to yield an FC-EDC with enhanced error-detecting properties, designed to detect the most likely errors in the known physical environment. By using a parity-check matrix with the “rotation” property, certain error-detecting properties of the parity-check matrix are ensured, and the computation time for searching for a matrix with enhanced error-detecting properties becomes much shorter.

Abstract: A subject of the invention is to propose a storage subsystem assuring high reliability and not impairing processing performance. The invention is a storage subsystem which includes a storage device including a hard disk drive and a controller for controlling an access to the storage device in response to a predetermined access command transmitted from a host computer. The storage subsystem stores, in response to a write request transmitted from the host computer, data associated with the write request together with its parity in the storage device as well as verifies the validity of the data stored in the storage device independently of a response to the write request and, when there is an abnormality in the data, repairs the abnormal data.

Abstract: A system, an apparatus and a method for transmitting/receiving data coded by a low density parity check matrix code are provided. The apparatus for transmitting data coded by a low density parity check code includes: a low density parity check encoder for encoding input data based on the low density parity check code; and a bit puncturer for puncturing columns in an order of columns which least degrade a performance caused by puncturing in the low density check code according to a code rate of an output data. Accordingly, the low density parity check code having superior performance can be implemented to the next generation mobile communication system supporting various code rates.

Abstract: A system for checking and correcting BIOS errors is provided. The system includes a program loading module (1001) for loading main programs from a BIOS ROM into a RAM; a checksum calculating module (1002) for reading the original checksum, and for calculating a new checksum for the main programs loaded in the RAM; an error checking module (1003) determining if the new checksum equals the original checksum; an error checking module for comparing the new checksum with the original checksum to identify errors in the main programs; and an error correcting module (1004) for correcting the errors in the main programs loaded in the RAM. A related method is also disclosed.

Abstract: A triple parity (TP) technique reduces overhead of computing diagonal and anti-diagonal parity for a storage array adapted to enable efficient recovery from the concurrent failure of three storage devices in the array. The diagonal parity is computed along diagonal parity sets that collectively span all data disks and a row parity disk of the array. The parity for all of the diagonal parity sets except one is stored on the diagonal parity disk. Similarly, the anti-diagonal parity is computed along anti-diagonal parity sets that collectively span all data disks and a row parity disk of the array. The parity for all of the anti-diagonal parity sets except one is stored on the anti-diagonal parity disk. The TP technique provides a uniform stripe depth and an optimal amount of parity information.

Abstract: An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

Abstract: A parity check matrix construction method for constructing a non-binary parity check matrix defining a non-binary LDPC code. In particular, a parity check matrix construction method for setting codewords able to stably give a superior decoding performance is provided. For this reason, the non-binary non-zero elements are selected so that the determinants of the partial matrices corresponding to the cycles in the parity check matrix do not become 0. Due to this, a non-binary parity check matrix able to give large weight codewords is constructed.

Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.

Abstract: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and/or variable modulation signals whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.

Abstract: A retransmission control method comprising: generating N parity check matrices; generating a generator matrix containing a check symbol generator matrix contained in the first parity check matrix; transmitting the codeword generated by using the generator matrix to another communications device; generating, when the communications device receives a NAK in response to the codeword, a first additional parity by using the second parity check matrix; and retransmitting the first additional parity to the another communications device.

Abstract: The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device.

Abstract: A method for creating cyclic permutation matrices P (810), with an arbitrary size Z×Z set by a parameter Z5 and which are used to create one or more LDPC related matrices in OFDMA systems, comprising: defining an integer value Z; creating an initial matrix (810); creating a matrix (810) by using cyclic shifts to each Encoder row; repeating stage 3, up to Z?2 times as required, thus creating up to Z?2 matrices: P(o) . . . P(Z?I); creating an additional stairs matrix P(st). A method for using cyclic per-mutation matrixes P (840), with a fixed size Z×Z set by a parameter Z, and which are used to create one or more LDPC related matrices (820) in OFDMA systems, comprising: defining an integer value Z; storing in memory means an initial matrix (810) and its cyclic shifts permutations (840), thus keeping memory means matrices: P(o) . . . P(Z?I); storing an additional stairs matrix P(st) (840); using these matrices (810) to create LDPC related matrices (840) or LDPC operations.

Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits, wherein the H-matrix is capable of being partitioned into a first matrix and a second matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1, wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint, and outputting the sequence of encoded bits.

Abstract: A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.

Abstract: The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.

Abstract: Irregular LDPC codes have a construction which allows one to obtain a number of codes with different length from a single prototype code with a parity check matrix given by H=[Hz Hi], where Hz specifies the well-known zigzag pattern in the corresponding Tanner graph. The parity check matrices for longer codes are obtained as [Hz? ? diag(Hi, . . . , Hi)], where Hz? specifies a longer zigzag pattern depending on the number of matrices Hi used, and ? represents some permutation. This allows one to construct the decoder for a longer code by reusing hardware components developed for decoding the prototype code.

Abstract: Method, apparatus, and computer readable medium for forward error correction (FEC) in a content distribution system is described. One aspect of the invention relates to encoding frames of content. In one example, each frame is set partitioned into un-coded bits and bits to be encoded. For each frame, parity bits are computed for the bits to be encoded using low density parity check (LDPC) coding to generate a codeword having information bits and the parity bits. Groups of interleaved bits from the information bits in the codeword are generated. Symbols formed from the bit groups and the un-coded bits are pseudorandomly interleaved. The symbols are then mapped to points in a quadrature amplitude modulation (QAM) constellation.

Abstract: A regular qc matrix is generated in which cyclic permutation matrices with specific regularity are arranged in row and column directions. A mask matrix supporting multiple encoding rates is generated for making the regular qc matrix into irregular. A specific cyclic permutation matrix in the regular qc matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking qc matrix. An irregular parity check matrix with a LDGM structure is generated, in which the masking qc matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.

Abstract: In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level identified as a reset state is increased than the case where the drivability is set equal. Thus, the time required to output a syndrome from a plurality of stages of XOR gates can be reduced to allow execution of error correction processing at high speed.

Abstract: To provide a turbo decoding method capable of significantly improving efficiency of a determination as to whether or not to end decoding. If the decoding by a turbo decoder is started, a soft decision value of an element decoder is derived, and an ECR of a current frame is estimated from the soft decision value by an ECR criterion deriving portion. If determined to be an end as a result of an end determination of the decoding by the turbo decoder from a result of comparison with a last ECR value and the maximum number of times of repetition of decoding, a hard decision result and a decoding result are outputted, and if not determined to be the end, the number of times of repetition is counted up so as to repeat the above process.

Abstract: A method of encoding data into a chain reaction code includes generating a set of input symbols from input data. Subsequently, one or more non-systematic output symbols is generated from the set of input symbols, each of the one or more non-systematic output symbols being selected from an alphabet of non-systematic output symbols, and each non-systematic output symbol generated as a function of one or more of the input symbols. As a result of this encoding process, any subset of the set of input symbols is recoverable from (i) a predetermined number of non-systematic output symbols, or (ii) a combination of (a) input symbols which are not included in the subset of input symbols that are to be recovered, and (b) one or more of the non-systematic output symbols.

Abstract: Embodiments of the present invention provide techniques for generating MTR codes with ECC without the use of a second MTR code, while still satisfying the specified constraint.

Abstract: The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

Abstract: The invention relates to a base matrix, a encoder/decoder of Low Density Parity Check (LDPC) codes and a generation method thereof. The encoder/decoder is determined uniquely by the parity check matrix of the LDPC codes. With different code sizes, said parity check matrix can be obtained by expanding different base matrixes, and also can be obtained by expanding a unique base matrix after correction. Elements of said base matrix must meet an inequation in which the girth value is up to the standard, e.g. when girth ?6, for any element i, j, k, l in the matrix which forms the short loop having a length of 4 in anticlockwise, there are always mod(i?j+k?l, z) unequal to 0.

Abstract: An accumulative repeat encoder can facilitate encoding data written to memory, such that parity data can be generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data can be stored in memory. During a read operation, a decoder component can utilize the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component can be iterative and can provide one or more decoding results based on certain probability calculations as to the values of the read data. The decoder component can analyze a decoding result and reference a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result can be representation of the original data and can be provided as an output.

Abstract: A method of decoding linear block code uses an iterative message passing algorithm with a binary image of a parity check matrix of the linear block code, wherein the parity check matrix is adapted from one iteration to another based on the reliabilities of bits in the linear block code. The adaptation involves reducing a submatrix corresponding to the less reliable bits in the linear block code to a sparse nature before applying the message passing algorithm in each iteration. An apparatus that performs the method is also provided and several variations of the algorithm are also provided.

Abstract: A method of generating check matrixes for LDPC codes includes analyzing a “Sum-Product Algorithm” for Low-Density Parity-Check codes, on the assumption that a Log Likelihood Ratio between input/output data at a decoder can be approximated in a Gaussian distribution; fixing a coding rate; obtaining an optimal ensemble, which is an ensemble that minimizes the threshold of SNR, of row and column weights in one linear programming to maximize a Gaussian noise; and generating a check matrix for LDPC codes in accordance with the ensemble obtained.

Abstract: The encoder chip of the present invention uses LDPC codes to encode input message data at a transmitting end, thereby generating a series of codewords. The encoder chip implements two low-density parity-check (LDPC) codes. The first LDPC code is a (4088,3360) code (4K) which is shortened from a (4095,3367) cyclic code. The second LDPC code is a quasi-cyclic (8158,7136) code (8K). The message data and the generated codewords are transmitted to a receiving end where the received codewords are decoded and checked for errors. To generate the codewords, the encoder applies a generator matrix G to the input message data. The G matrix is generated by first defining an H matrix. An H matrix is initially defined as 16×2 array of right-circulant sub-matrices. The G matrix is formed by manipulating the H matrix according to a 4-step algorithm. A randomizer and a synchronization marker are also included within the encoder.

Abstract: A decoder and method for iteratively decoding of low-density parity check codes (LDPC) includes, in a code graph, performing check node decoding by determining messages from check nodes to variable nodes. In the code graph, variable node decoding is performed by determining messages from the variable nodes to the check nodes. The variable node decoding is independent from degree information regarding the variable nodes. Decoded results are output.

Abstract: A data-packing device, such as a direct memory access controller (DMA), aligns data at a granularity smaller than an error protected unit (EPU) encoded by an error correction code (ECC) in the memory. For example, the data alignment is at a double-word level or a byte level. The data-packing device reads data from the memory, shifting the data, and marks a good data unit as corrupted if the data unit constitutes a fractional portion of a corrupted EPU. The marking of the data unit is performed by inverting a parity bit of the data unit.

Abstract: A de-interleaver has a TTI frame buffer storing a TTI frame before de-interleaving, a P bit information table storing P bit information containing the size and added position of P bits to be added to the TTI frame before de-interleaving, and a permutation rule table storing permutation rules of de-interleaving. The de-interleaver performs de-interleaving on the data stored in the TTI frame buffer based on the P bit information stored in the P bit information table and the permutation rules stored in the permutation rule table.

Abstract: A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: A CRC generation unit includes a number of CRC calculation assemblies to be selectively employed to incrementally calculate a CRC value for a first sequence of N data bytes. The calculation is iteratively performed, one iteration at a time. Further, the selection of the CRC calculation assemblies is made in accordance with the group size of each of a number of data word groups of the N data bytes. In one embodiment, the CRC calculation assemblies include a first assembly for incrementally calculate the CRC value for an iteration, whenever the group size is n/2 bytes or less for the iteration, and a second assembly for incrementally calculate the CRC value for an iteration, whenever the group size is more than n/2 bytes for the iteration. In one embodiment, the CRC generation unit is a shared resource to multiple network traffic flow processing units of a network traffic routing IC.