Abstract: Aspects of the present disclosure are directed toward methods and systems which generate a plurality of Read-Only Memory (ROM) codes. In response to generating the ROM codes, an image is generated for each of the plurality of ROM codes. The images for each of the plurality of ROM codes are mapped on a single reticle, and a wafer is provided, which includes a plurality of individual devices. The reticle is utilized, which includes an image for each of the plurality of ROM codes, to print a respective one of the images onto a respective one of the plurality of individual devices.

Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

Abstract: Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.

Abstract: A reconfigurable circuit generation device comprises: a netlist generation unit that generates as a shared netlist a netlist that can be shared among a plurality of netlists having a common portion, and a resource reduction unit that reduces resources of the reconfigurable circuit where the plurality of netlists are to be implemented, in a range in which the shared netlist can be implemented.

Abstract: A method of manufacturing an electronic circuit employing a flexible ramptime limit and an electronic circuit are disclosed. In one embodiment, the method includes: (1) physically synthesizing a logical representation of an electronic circuit employing flexible ramptime limits, (2) performing a timing test on the physically synthesized electronic circuit employing the flexible ramptime limits and a processor and (3) determining if there is a violation of the flexible ramptime limits.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Abstract: Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness.

Abstract: Some aspects of the present disclosure provide for a system and method to discover which parts of a design a formal test suite can detect faults in, and thus how much of a design structure is covered by a property set. A mutatable RTL design is defined which allows for modification of a part of an RTL design from its intended behavior to a non-intended behavior, thus introducing unwanted effects. The mutatable RTL design can then be synthesized to produce a functional representation of the design. The property set can be re-run on the synthesized design to see whether the functional representation of the design is sensitive to the unwanted effect and thus whether formal verification can detect the modification.

Abstract: Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.

Abstract: Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.

Abstract: One embodiment sets forth a technique for on-chip satisfying timing requirements of on-chip source-synchronous, CMOS-repeater-based interconnect. Each channel of the on-chip interconnect may include one or more redundant wires. Calibration logic is configured to apply transition patterns to wires comprising each channel and calibration patterns that are generated in response to the transition patterns are captured. Based on the calibration patterns, wires that best satisfy the timing requirements of the on-chip interconnect are selected for use to transmit data. The calibration logic also trims the delays of the clock and selected data wires based on captured calibration patterns to improve the timing margin of the on-chip interconnect. Improving the timing margin of the on-chip interconnect improves chip yields.

Abstract: A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Abstract: In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner.

Abstract: Provided are a fin transistor including a plurality of fins and a semiconductor integrated circuit including a plurality of fin transistors. A width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on the electrical characteristics of the fin transistor.

Abstract: Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.

Abstract: A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

Abstract: A system and method for providing schematic reviews is provided. The method includes providing a schematic design, selecting a signal, where the signal is a graphical representation, previewing the signal, obtaining relevant information on components constituting the signal, and controlling the signal to obtain relevant information on the components. Controlling the signal comprises activating a link to a data compilation related to the signal component, and activating the data compilation comprises creating a link to a datasheet. The graphic representation of the signal comprises providing a block diagram overview of connectivity of the signal components and the graphical representation comprises a graphical three dimensional model, and providing a log database that includes review information provided by multiple reviewers and is accessible by the reviewers. A notation medium is provided for the reviewers for communication between the reviewers.

Abstract: A verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition is greater than the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group.

Abstract: Techniques for determining and a computing device configured to determine a quantum Karnaugh map through decomposing a quantum circuit into a multiple number of sub-circuits are provided. Also, techniques for obtaining and a computing device configured to obtain a quantum circuit which includes the minimum number of gates among possible quantum circuits corresponding to a quantum Karnaugh map are also provided.

Abstract: Designing a photonics switching system is provided. A photonic switch diode is designed to attain each performance metric in a plurality of performance metrics associated with a photonic switching system based on a weighted value corresponding to each of the plurality of performance metrics. A switch driver circuit is selected from a plurality of switch driver circuits for the photonic switching system. It is determined whether each performance metric associated with the photonic switching system meets or exceeds a threshold value corresponding to each of the plurality of performance metrics based on the photonic switch diode designed and the switch driver circuit selected. In response to determining that each performance metric associated with the photonic switching system meets or exceeds the threshold value corresponding to each of the performance metrics, the photonic switching system is designed using the photonic switch diode designed and the switch driver circuit selected.

Abstract: The present disclosure relates to methods and systems for designing and fabricating an integrated circuit. In particular, a method includes electronically searching a virtual layout of an integrated circuit to locate a dummy polysilicon structure positioned between adjacent terminals of first and second MOSFET devices that are connected to different nodes of the integrated circuit. The method includes changing a configuration of the dummy polysilicon structure of the virtual layout to extend an active silicon region adjacent to the dummy polysilicon structure and to form an electrical connection between the dummy polysilicon structure and one of a supply voltage node and a ground node of the integrated circuit.

Abstract: A method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. Designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern. Generating the second, updated DSA directing pattern includes linearizing a self-consistent field theory equation.

Abstract: A method, computer program storage device and system are provided for determination and selection of optimized circuit components. The method includes performing a timing analysis on at least a portion of an electronic circuit and determining a path in the at least a portion of an electronic circuit, where the path comprises at least one storage element and an operational attribute associated with the path. The method also includes determining an optimized storage element adapted to utilize the operational attribute. The system includes a processing device and at least one of a synthesis tool, a timing tool or a place and route tool communicatively connected to the processing device. The synthesis tool, the timing tool and the place and route tool are adapted to process or analyze an electrical circuit.

Abstract: A method for calculating leakage current associated with an integrated circuit, includes selecting a sampling point at which an input signal for the integrated circuit is in a quiescent state and determining the leakage current associated with the integrated circuit using the selected sampling point.

Abstract: In an exemplary embodiment, a method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. The step of designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern.

Abstract: A calibration method for a device using TCAD to emulation SOI field effect transistor, where process emulation MOS device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; the process emulation MOS device structures are calibrated according to a TEM test result, a SIMS test result, a CV test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor. Thereby, providing effective guidance for research, development and optimization of a new process flow are realized.

Abstract: A design tool provides interactive graphical pin assignment. In one embodiment, the design tool identifies layout restrictions of a configurable processing device that includes a plurality of pins. The design tool further provides an interactive visual representation of a pin assignment that accommodates the layout restrictions and a user input.

Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.

Abstract: Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.

Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias.

Abstract: Soft error modeling of circuits. Soft error upset (SEU) specification and design information is received from a design entry. The SEU specification comprises expected SEU behavior of a node. A logical simulation model is created based on the SEU specification and the design information. A logical verification is performed based on the logical simulation model to produce a first result. The logical verification comprises selecting a first node for injection, injecting an SEU into the first node to produce a first result, and responsive to the first result not agreeing with the SEU specification, providing the first result to the design entry. A netlist based on the SEU specification and the design information is created. The netlist comprises a specification-based-logic-derating derived from the SEU specification. A physical design verification based on the netlist, a logic derating, and clock information is performed.

Abstract: Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described.

Abstract: In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.

Abstract: A method, implemented in a processor, of determining a likelihood of failure of a circuit to be made in accordance with a circuit design, and a computer-readable storage medium storing instructions to the processor for carrying out the method. A sensitivity of a figure of merit to each variable of a plurality of variables is determined by simulating operation of the circuit using the processor. Determining the sensitivity is based on a departure of each of the variables from a respective mean value, where the variables include at least one variable derived from measurements of a fabricated component or component combination to be included in the circuit. Results from the simulation are used to predict a failure probability of the circuit to be made in accordance with the circuit design.

Abstract: A system, such as a computer aided design (CAD) system, is configured to abstract at least a portion of an integrated circuit (IC) design provided thereto. The system selects two signals of the IC and determines the respective sub-circuits ending at each of the signals, excluding the other sub-circuit when two sub-circuits intersect. It then identifies an intersection of the two sub-circuits and therefore establishes an abstraction therefrom. The abstraction replaces the circuit for verification purposes of the IC design. The process can repeat as may be necessary or until no two signals have sub-circuits that intersect. The process described for two signals is equally applicable to a plurality of signals for which the intersection is defined as the intersection of all the sub-circuits defined by the plurality signals. The abstraction allows for effective verification of portions of ICs as may be necessary.

Abstract: An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value.

Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.

Abstract: A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, using feedback from the event monitors the test generator patterns may be manipulated to preferentially generate patterns that may exercise signal paths that are being monitored in subsequent simulations.

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Abstract: Computer-implemented methods are disclosed for providing an elastic modulus map of an integrated circuit (IC) chip of a chip/device package, for identifying a probable failure site of the chip/device package from the elastic modulus map of the IC chip, for modifying a connector footprint of the chip/device package based on identifying a probable failure site from the elastic modulus map of the IC chip, and for modifying the IC chip based on identifying a probable failure from the elastic modulus map of the IC chip. Each layer of the IC chip may be mapped, and each grid shape of the mapped layers may comprise a metal area and a dielectric area. Grid shapes from each layer of the IC are vertically aligned to provide a combined spring constant for each grid shape, which are then mapped onto the elastic modulus map to identify possible failure sites in the chip/device package.

Abstract: In a method for creating an equivalent circuit for a three-terminal capacitor including first, second, third and fourth electrodes, a first capacitor conductor connected between the first and second electrodes, and a second capacitor conductor connected between the third and fourth electrodes, the equivalent circuit includes a first line connecting the first electrode to the second electrode; a second line connecting the third electrode to the fourth electrode; a third line that includes a first capacitor component and that connects the first line to the second line; a first circuit component including a first inductor component and a first resistor component provided between a connection portion between the second line and the third line and the third electrode; and a second circuit component including a second inductor component and a second resistor component provided between the connection portion and the fourth electrode.

Abstract: A circuit design system generates a circuit variant by relocating one or more circuit elements through a user move action on a user interface. When the user move action results in the circuit element traversing a circuit domain boundary, the design system performs one or more operations to form the circuit variant having its initial connectivity with the relocated circuit element without any other user action on the user interface than the user move action. Further, in response to no other action on the user interface than the user move action, analysis tools and reports are initiated so that rapid evaluation of circuit variants may be implemented.

Abstract: An integrated circuit (IC) design verification system includes a memory for storing an IC design and a processor in communication with the memory. The IC design includes multiple IP cores and the design verification apparatus includes multiple verification modules. The processor configures a first set of connections between the IP cores and the verification modules based on a first connection database and verifies each IP core independently using the first set of connections. Thereafter, the processor configures a second set of connections between the IP cores and the verification modules based on a second connection database generated based on the first connection database, and verifies the multiple IP cores together using the second set of connections.

Abstract: In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.

Abstract: A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (?{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 ?m2).

Abstract: A method of circuit design includes receiving a user input selecting a first interface of a circuit block of a circuit design as a source interface in creating a connection within the circuit design and selecting a second interface of the circuit design as a candidate destination interface for the connection using a processor. The method further includes determining compatibility between the second interface and the first interface and indicating compatibility of the second interface with the first interface for the connection.