Abstract: A system, method, and computer program product for automatically providing circuit designers with verification coverage information for analog/mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to assemble a schematic representation of a lower-level circuit design from pre-defined building blocks and various types of connections. Embodiments convert the schematic representation into a behavioral model for rapid simulation. Building blocks in the behavioral circuit have coverage-related terms defined either by the designer or by default, such as input and output value ranges, internal state changes, and state timers and timing-related constraints. Embodiments simulate the behavioral circuit, and determine and tangibly output coverage-related information. Manual and automatic behavioral circuit and stimulus modification can maximize coverage for improved behavioral circuit verification.

Abstract: A method for the automatic design of an electronic circuit includes operations for evaluation of the thermal effects in the electronic circuit. The method generates a layout of the electronic circuit. Abstract data at the substrate level associated to the layout of the electronic circuit is then generated. A grid of partitioning is generated with respect to a view regarding the aforesaid abstract into meshes and nodes. The grid is applied to the substrate. On the basis of the grid (TG), a list of nodes or netlist representing a thermal network that represents the thermal behavior of the substrate or of its portions or elements is extracted. The netlist is useful in simulation operations, in particular of a SPICE type, for making an evaluation of thermal effects in the electronic circuit.

Abstract: A simulation instructing unit instructs a simulation unit, which generates signal characteristics, to generate the signal characteristics. A characteristic value extracting unit extracts, from the signal characteristics, characteristic values for distinguishing between a signal characteristic generated by setting a first simulation parameter and a signal characteristic generated by a second simulation parameter. A simulation parameter determining unit determines a first mapping relationship from the characteristic values to the simulation parameters with the characteristic values obtained by setting a plurality of set values in the simulation parameters and with the set values.

Abstract: A printed substrate design system includes: an EMI condition determination unit that compares an EMI characteristic derived by an EMI characteristic derivation unit with an EMI allowable condition, and determines whether the EMI characteristic of a printed substrate satisfies the EMI allowable condition; a substrate configuration change unit that changes an internal configuration of the printed substrate to obtain a changed configuration of the printed substrate in a case where the EMI condition determination unit has determined that the EMI allowable condition is not satisfied, and sets design information of the changed configuration of the printed substrate to design information for deriving the EMI characteristic in the EMI characteristic derivation unit; and an output unit that outputs a printed substrate configuration in a case where the EMI condition determination unit has determined the EMI allowable condition is satisfied.

Abstract: A region of congestion is detected at a set of layers. The region occupies the same area of each layer in the set. A routing blockage is defined as a tuple corresponding to the region. The tuple includes a set of coordinates to describe an area of the region, a first and a second layer coordinates of a first and a second layer in the set of layers. The routing blockage is applied during an iteration of rough routing. Before an iteration of detailed routing, the routing blockage is removed. Detailed routing is performed using a g-cell in the region. The detailed routing uses a routing capacity saved in the g-cell during the iteration of rough routing due to the routing blockage. A revised IC design is produced where a revised congestion in an area corresponding to the region is reduced.

Abstract: A computer-implemented method to debug testbench code of a testbench associated with a circuit design by recording a trace of call frames along with activities of the circuit design. By correlating and displaying the recorded trace of call frames, the method enables users to easily trace as execution history of subroutines executed by the testbench thereby to debug the testbench code. In addition, users can trace source code of the testbench code by using the recorded trace of call frames. Furthermore, users can debug the testbench code utilizing a virtual simulation, which is done by post-processing records of the virtual simulation stored in a database.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Methodologies and an apparatus enabling a selection of design rules to improve a density of features of an IC design are disclosed. Embodiments include: determining a feature overlapping a grating pattern of an IC design, the grating pattern including a plurality of grating structures; determining a shape of a cut pattern overlapping the grating pattern; and selecting one of a plurality of rules for the feature based on the determined shape.

Abstract: A method is provided for verification of a logic design for a processor execution unit which includes an instruction pipeline with one or more pipeline stages. The method includes: creating a design under test using at least a first and a second instance of the logic design; initializing the instruction pipeline using the first instance of the design under test with the same value in each instruction pipeline stage and the second instance with random values in its pipeline stages; selecting an instruction of the processor execution unit out of a plurality of instructions and simultaneously issuing the instruction to each instance of the design under test; providing a comparison between the outputs of the instruction pipeline executing the instruction for each instance; and if the instruction is verifiable by formal model checking, approving the correctness of the logic design if the comparison result is true.

Abstract: A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster.

Abstract: Systems and techniques for creating a circuit abstraction are described. During operation, an embodiment can identify a set of side loads based on a set of timing paths. According to one definition, a side load of a timing path is a circuit element that is not on the timing path (i.e., the timing path does not pass through the circuit element), but whose input is electrically connected to an output of at least one circuit element that is on the timing path. Next, the embodiment can creating the circuit abstraction by retaining circuit elements and nets on each timing path in the set of timing paths, and retaining an identifier for each side load in the set of side loads. The circuit abstraction can then be used to update timing information during one or more stages of an electronic design automation flow.

Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.

Abstract: A method, system and product for explaining illegal combinations in combinatorial models. The method comprising obtaining a combinatorial model and an illegal combination that is excluded from the model by one or more restrictions, utilizing a Satisfiability solver on a satisfiability formula that encodes the legal test space and that assigns values to attributes as defined by the illegal combination, whereby the satisfiability solver provides an indication of unsatisfiability of the satisfiability formula and an UNSAT core comprising a subset of clauses defined by the satisfiability formula which are unsatisfiable; and identifying the one or more restrictions by mapping the clauses of the UNSAT core with clauses encoding the set of restrictions.

Abstract: A method, computer-readable medium and apparatus for creating a platform-specific logic design from an input design are disclosed. For example, a method includes receiving an input design and an identification of a target device. The method next determines an unconnected external interface of the input design and detects an unconnected external interface of the target device. The method then generates an updated design from the input design. The updated design includes the input design and further includes a connection between the unconnected external interface of the input design and the unconnected external interface of the target device.

Abstract: The subject system and method are generally directed to the user-friendly insertion of at least one device, and optionally chains of devices, into at least one pre-existing chain of interconnected devices within a graphical representation of a circuit design such as a circuit layout, circuit mask, or a schematic. The system and method provide for discerning the intended insertion points and performing remedial transformations of the devices within the chains to ensure compliance with both structural and operational requirements of the circuit design.

Abstract: A method is described that involves solving a family of equations for a circuit being designed over a subset of operational scenarios, thereby producing numeric values for design parameters of the circuit. The family of equations is enhanced with the numeric values are solved over a second subset of the operational scenarios. A design for the circuit that includes the numeric values is produced.

Abstract: A capacitor arrangement assisting method wherein data entered by a user, such as the width w of a power supply wiring, the thickness h of a dielectric between the power supply wiring and a ground plane, the ESLcap of a capacitor, and a target frequency fT and a target impedance ZT of an IC, are received, the maximum allowable wiring length lmax of the power supply wiring is calculated on the basis of the received width w of the power supply wiring, the thickness h of the dielectric, the ESLcap of the capacitor, and the target impedance ZT of the IC at the target frequency fT, and the calculated maximum allowable wiring length lmax is displayed.

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract: A method comprising placing elements in a layout, performing clock tree synthesis, and performing routing. The method further comprising, in parallel with one of the clock tree synthesis or the routing, performing a footprint based optimization, substituting a footprint equivalent element in a path based on a timing slack of the path.

Abstract: A computer-implemented method for modeling Spatially Correlated Variation (SCV) in a design of an Integrated Circuit (IC) is disclosed. In one embodiment, the method includes: generating a set of coefficient values for a position dependent SCV function, the set of coefficient values being selected from a set of random variables; obtaining a set of coordinates defining a position of each of a plurality of devices in a defined field; evaluating the position dependent SCV function to determine a device attribute variation for each of the plurality of devices based upon the coordinates of each of the plurality of devices; modifying at least one model parameter based upon the evaluation of the position dependent SCV function; and running a circuit simulation using the at least one modified model parameter.

Abstract: A method for modeling jitter includes generating a first delay-impacting parameter function for a first signal and a second delay-impacting parameter function for a second signal. A first delay per element function is generated from the first delay-impacting parameter function and a second delay per element function from the second delay-impacting parameter function. A difference in path delay from the first delay per element function and the second delay per element function is identified.

Abstract: In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

Abstract: Aspects of the invention provide for the maintenance of user modified portions of a map between a test bench and a test set generator during an iterative electronic design process. Various implementations of the invention provide for matching sections within a design for an electronic device with corresponding sections in a map between the elements in the design to elements in a graph representation of the design. The matched sections are then compared to determine if any discrepancies exists, such as, for example, if the design has been recently changed. If any discrepancies do exist, then it is determined whether the section of the map can be updated or must be replaced entirely to resolve the discrepancies. Various implementations of the invention provide that the process can be repeated during an iterative design flow such that as the design is modified during the iterative design flow, the map can be updated to reflect the changes.

Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, using at least one computing device, an electronic design and associating, using the at least one computing device, one or more identifiers with each constraint solver call utilized in a simulation of the electronic design. The method may further include automatically generating, using the at least one computing device, a coverage model for one of more constraints associated with the electronic design, the coverage model being based upon, at least in part, the one or more identifiers.

Abstract: A detecting device includes an input device, a display, and a computer system. The computer system includes a setting module, a storing module, a detecting module, and a control module. The storing module stores a PCB layout file. The setting module receives detecting parameters inputted by the input device. The detecting module detects the PCB layout file according to the detecting parameters to obtain detecting data corresponding to the detecting parameters. The control module displays a “fail” message on the display if the detecting data does not match standard data.

Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file.

Abstract: A receiving unit receives specification of two parts to be connected by wirings and the number of wirings connecting the two parts. A generating unit generates a schematic route connecting the two parts on a substrate with a width in accordance with the number of wirings received by the receiving unit. A derivation unit derives the number of arrangeable wirings by checking interference whether the schematic route generated by the generating unit is capable of being arranged on the substrate.

Abstract: A method for processing signals in a system includes deriving a signal activity for a signal from a timing requirement assignment for the signal.

Abstract: A method for using a breadboard involves receiving a circuit wiring connection layout, in which the circuit wiring connection layout includes a visual representation of circuit elements. The method further involves sending, to the breadboard, the circuit wiring connection layout, receiving a selection of a circuit element from the circuit elements to obtain a selected circuit element, sending, to the breadboard and based on the selected circuit element, a signal to activate an alert device on the breadboard indicating where a user should place the selected circuit element on the breadboard, receiving a circuit characteristic to measure from the selected circuit element, sending, to the breadboard, the circuit characteristic to measure from the selected circuit element, receiving, from the breadboard, a measurement of the circuit characteristic to obtain a measured circuit characteristic, and displaying the measured circuit characteristic.

Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.

Abstract: A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m<N) and wherein the masked test data are compacted by a compactor with N data inputs and n data outputs and m<N applies is provided.

Abstract: Techniques generating a simulation model for a circuit design are disclosed. One of the techniques includes extracting a plurality design properties associated with the circuit design. The design properties are extracted from a netlist of the circuit design and may include an input/output (I/O) buffer setting extracted from a first netlist of the circuit design or an environmental condition associated with the circuit design. A second netlist for the circuit design is generated based on the design properties and is simulated based on the design properties. A simulation model for the circuit design is generated. In an exemplary embodiment, the simulation model reflects the I/O buffer setting or the environmental condition associated with the circuit design.

Abstract: In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: Disclosed are a system and a method for determining merged resistance values of same-type terminals of multiple electrically connected multi-terminal semiconductor devices (e.g., field effect transistors) in a complex semiconductor structure, wherein all first terminals are connected to a first node, all second terminals are connected to a second node, and all third terminals are connected to a third node. Modified resistor networks are generated from a full resistor network including, but not limited to, a first modified resistor network with shorted second terminals and a second node; a second modified resistor network with shorted first terminals and a first node; and a third modified resistor network with first terminals and first node shorted and with the second terminals and second node shorted. Simulations are performed using the modified resistor networks and, based on the results, merged resistance values for the first, second, and third terminals are determined.

Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

Abstract: A control section of a circuit verification apparatus acquires waveform data of output in a transient state of a verification target circuit by a circuit simulation and stores the waveform data in a storage section. When the control section detects input to a functional model of the verification target circuit during functional verification performed by the use of the functional model, the control section generates an output signal of the functional model by the use of the waveform data stored in the storage section.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: A computer-implemented method, computerized apparatus, and computer program product for test validation planning. The computer-implemented method, performed by a processor, comprising: having a test validation activity to be performed to validate results of two or more tests of a test suite; and automatically determining, by a processor, a subset of the two or more tests for which to perform the test validation activity; whereby avoiding performing duplicate validation activities. Optionally, for each test of the test suite a valuation of a set of functional attributes is available, and a subset of the functional attributes is deemed as relevant functional attributes with respect to the test validation activity. In such an embodiment, said determining is based on the valuation of the relevant functional attributes.

Abstract: A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.

Abstract: A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.

Abstract: An embodiment of a method of high-level synthesis of a dataflow pipeline is disclosed. This embodiment includes obtaining processes from the high-level synthesis of the dataflow pipeline. A schedule for read operations and write operations for first-in, first-out data channels of the processes is determined. A dataflow through the dataflow pipeline for the schedule is determined. An edge-weighted directed acyclic graph for the processes and the dataflow is generated. A longest path in the edge-weighted directed acyclic graph is located. A weight for the longest path is output as an estimate, such as a latency estimate for example, for the dataflow.

Abstract: An assertion-based verification tool for circuit designs includes an effective measurement of assertion density for any given generated set of assertions. A register-transfer level (RTL) description of an integrated circuit (IC) is used to compute a set of predicates. Then, determination is made as to the number of predicates that are satisfiable on the given set of assertions received respective of the RTL description. Thereafter, simulation traces for the RTL are received and the number of predicates satisfiable on the simulation traces is computed. A figure of merit of assertion density is determined from the ratio of the respective numbers of predicates. The set of assertions may be modified as required to satisfy a predetermined threshold value of assertion density, to assure that a circuit is rigorously tested by the verification tool.

Abstract: A computer-implemented method for simulating an electrical circuit. The method includes (a) setting a first temperature distribution in the electrical circuit, (b) performing an electrical simulation across the electrical circuit taking into consideration the first temperature distribution, (c) performing a thermal simulation across the electrical circuit taking into consideration a result of the electrical simulation, to obtain a second temperature distribution, and (d) determining whether a criterion for termination the simulation is met. If the criterion is met, terminate the simulation. If the criterion is not met, assign the second temperature distribution to the first temperature distribution, and repeat steps (b), (c), and (d).

Abstract: A method is provided for identifying use of a proprietary circuit layout. A representation of a layout of a circuit is input and the locations of a set of predetermined physical features of the circuit are identified. This set of locations is then compared with a previously generated characteristic pattern file, the characteristic pattern file comprising a representation of relative locations of a set of these predetermined physical features in the proprietary circuit layout. If the set of locations matches the relative locations of the characteristic pattern file, then an output is generated indicating that use of the proprietary circuit design has been found.

Abstract: A plurality of diagnosis methods are provided for enabling hardware debugging. A first diagnosis method enables hardware debugging by means of time abstraction. A second-diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide.

Abstract: A wiring inspection apparatus includes a first calculating unit, a second calculating unit, and an output unit. The first calculating unit calculates the number of components arranged along two sides, one of which extends in a first direction and the other one of which extends in a second direction, of a minimum rectangle including a transmission component and a reception component. The second calculating unit calculates the number of the components arranged along the two sides at a predetermined arrangement density of relay components. When the number of the relay components is greater than the number of the components calculated by the second calculating unit, the output unit outputs information indicating the presence of a wiring extending in a direction opposite to a direction from the transmission component to the reception component among wirings connecting the transmission component, the reception component, and the relay components.

Abstract: A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is created. In the degraded netlist, the first transistor is degraded by a device degradation for the first transistor. The second transistor is degraded by a device degradation for the second transistor. The circuit is re-simulated with the first degraded transistor and the second degraded transistor in place of the first MOS transistor.

Abstract: A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation system are also included.