Abstract: A method for operating a data processing system to simulate a circuit that includes a plurality of circuit devices connected by interconnects. A layout description of the circuit is provided in which the devices are connected by interconnects. Each interconnect is associated with a line definition that includes a physical description of an interconnect between two of the circuit devices and a simulation model to be used in simulating the interconnect during simulations of the circuit. The line definitions are user selectable from a list of available line definitions. A circuit netlist is generated by reading physical interconnects from the layout. At least one of the interconnects is replaced by a plurality of transmission line devices, each device being associated with the simulation model included in the line definition. The circuit is then simulated using the netlist.

Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.

Abstract: A method is provided for simulating oilfield operations. The method may include receiving two or more reservoir models to be simulated and receiving two or more surface models to be simulated. The method may further include automatically generating a communication file to couple the two or more reservoir models with the two or more surface models. Additionally, the method may include simulating the coupled reservoir models and surface models.

Abstract: A method and system to route connections of sub-networks in a design of an integrated circuit and a computer program product are described. The method includes determining a baseline route for each of the connections of each of the sub-networks, identifying noise critical sub-networks in the design of the integrated circuit based on congestion, and setting a mean threshold length (MTL), the MTL indicating a maximum length of each segment of each connection. Each segment includes a wirecode which is different from a wirecode of an adjacent segment, each wirecode defining a width, a metal layer, and a spacing for each segment. The method also includes segmenting the connections of the noise critical sub-networks based on the MTL, and re-routing the baseline route based on the segmenting.

Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.

Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Abstract: Contactless determination of electrical parameters. The examples describe a method and apparatus for determining electrical parameters of assemblies (printed circuit boards and as well as passive components) by the contactless determination of the spatial distribution of material. The spatial distribution of material (two-dimensional or three dimensional), is determined for example by measurement by radiographic technology with an X-ray machine or a computer tomography or by an optical instrument. The electrical parameter is determined in each volume element whose size is determined by the resolution of the method used for determining the material distribution, or a partial structure of the conductive structure.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems for performing power analysis during the design and verification of a circuit. Certain exemplary embodiments include user interfaces and software infrastructures that provide a flexible and powerful environment for performing power analysis. For example, embodiments of the disclosed technology can be used to construct complex and targeted power queries that quickly provide a designer with power information during a circuit design process. The disclosed methods can be implemented by a software tool (e.g., a power analysis tool or other EDA tool) that computes and reports power characteristics in a circuit design (e.g., a system-on-a-chip design or other integrated design).

Abstract: A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a circuit, produce computed cross-talk noise pulses potentially contributing to a maximum noise for the victim net. The MILP is solved to determine the maximum noise at the victim net. Responsive to the maximum noise meeting one or more criteria, at least an indication of the victim net is output. Forming may include forming a linear problem using overlapping timing windows for which noise pulses contribute to the maximum noise and converting the linear problem to the mixed integer linear problem by introducing into the linear problem binary variables that determine whether individual ones of overlapping or non-overlapping noise pulses from the one or more aggressor nets contribute to the maximum noise. Apparatus and program products are also disclosed.

Abstract: A layout method for a printed circuit board (PCB) is provided. A memory type of a dynamic random access memory (DRAM) to be mounted on the PCB is obtained. A module group is obtained from a database according to the memory type of the DRAM, wherein the module group includes a plurality of routing modules. A plurality of PCB parameters are obtained. A specific routing module is selected from the module group according to the PCB parameters. The specific routing module is implemented into a layout design of the PCB. The specific routing module includes layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

Abstract: A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit.

Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract: A capacitor arrangement assisting method wherein data entered by a user, such as the width w of a power supply wiring, the thickness h of a dielectric between the power supply wiring and a ground plane, the ESLcap of a capacitor, and a target frequency fT and a target impedance ZT of an IC, are received, the maximum allowable wiring length lmax of the power supply wiring is calculated on the basis of the received width w of the power supply wiring, the thickness h of the dielectric, the ESLcap of the capacitor, and the target impedance ZT of the IC at the target frequency fT, and the calculated maximum allowable wiring length lmax is displayed.

Abstract: A system and method are provided for using a class H amplifier in a tester for testing protective relaying equipment, particularly useful in conducting end to end testing. The class H amplifier is configured to provide separation between the amplifier and the power supply of the tester using a DSP which also offers flexibility for programming algorithms to realize efficiencies in matching the waveform to the output rail. End to end testing is also improved by including expected results for the test case used by the tester to enable the tester to determine how close the results are to what is expected. This offers time savings and is less prone to error in that the expected results can be predetermined by a qualified/experienced professional.

Abstract: A method of wire routing is provided. The method comprises obtaining data of cell layouts, generating a first database for the cell layouts, identifying, for each cell in the first database, whether the cell and another cell in the first database are routable in a pin layer, and generating a second database for routable cells.

Abstract: Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.

Abstract: For one or more geometric elements partitioned into a plurality of geometric element portions, the expected current directions through each geometric element portion are determined. Using the expected current directions, each expected current path through the geometric element portions is determined. Based upon the expected current paths, and the physical characteristics represented by the geometric element portions in those expected current paths, the electromigration features corresponding to the geometric element or elements are determined. For example, the length of the longest expected current path through the geometric element or elements can be identified based upon the lengths of the geometric element portions and the directions of their currents, and this length can then be compared with the Blech length for the geometric element or elements.

Abstract: Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values.

Abstract: The systems and methods of the present disclosure calibrate impedance loss model parameters associated with an electrosurgical system having no external cabling or having external cabling with a fixed or known reactance, and obtain accurate electrical measurements of a tissue site by compensating for impedance losses associated with the transmission line of an electrosurgical device using the calibrated impedance loss model parameters. A computer system stores voltage and current sensor data for a range of different test loads and calculates sensed impedance values for each test load. The computer system then predicts a phase value for each load using each respective load impedance value. The computer system back calculates impedance loss model parameters including a source impedance parameter and a leakage impedance parameter based upon the voltage and current sensor data, the predicted phase values, and the impedance values of the test loads.

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.

Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

Abstract: A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

Abstract: An object of the present invention is to provide wiring board design system and wiring board design method to determine a component and a wiring pattern in real-time when designing a wiring on a circuit board. The wiring board design system provides a cloud service for a terminal which is used by users via a network. When to arrange components on the circuit board, while pushing out automatically wirings which are overlapped with the components on the arranging position, the wiring board design system secures a space on that can arrange the component. The wiring processing is performed automatically and the fine adjustment such as rotation, movement of arranged components is performed automatically if necessary. The processing for equalization is performed so as to be the equal wiring density on the circuit board.

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract: Disclosed is a method for design validity verification of an electronic circuit board with regard to power supply noise, wherein with regard to an i-th LSI (i=1 to n) on the electronic circuit board, an input voltage Vin[i] to the LSI from the printed circuit board is given by Vin[i]=VDD?Z1si[i]×VDD/(Z1si[i]+Z11[i]), where Z1si[i] is an input impedance characteristic and Z11[i] is a reflected impedance characteristic viewed from a position at which the i-th LSI is mounted, being a characteristic with the i-th LSI omitted from the whole of the electronic circuit board and a judgment is made as to whether or not a reflected voltage Vr[i]=Vin[i]×(Z1si[i]+Z11[i])/(Z1si[i]?Z11[i]) satisfies |Vr[i]|?? V (power supply variation tolerance range).

Abstract: Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a congestion metric, a latency metric, a crosstalk metric, an electromigration metric, and a clock tree level. Next, the embodiments can generate the set of non-default routing rules for routing the net based on one or more metrics. A routing rule can specify how wide the wires are supposed to be and how far apart adjacent wires are to be placed. A non-default routing rule can specify a wire width that is different from the default width and/or specify a spacing (i.e., the distance between two wires) that is different from the default spacing.

Abstract: A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.

Abstract: In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

Abstract: The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated.

Abstract: A method for automatic design of an electronic circuit, includes: generating (100) a layout (L) of the aforesaid electronic circuit; generating (200) abstract data (A) at the substrate level associated to the layout (L) of the aforesaid electronic circuit; generating (300) a grid (TG) of subdivision into meshes and nodes with respect to a view pertaining to the aforesaid abstract (A) and applying it to the aforesaid substrate (SBS); and extracting (400), on the basis of the aforesaid subdivision grid (TG), a full electrical netlist (NC) pertaining to the substrate (SBS). The method further includes performing an evaluation (500, 600) of the interactions between devices (DV) of the electronic circuit at the substrate level according to the aforesaid full electrical netlist (NC) pertaining to the substrate (SBS).

Abstract: An electronic apparatus may include a circuit board, a processor disposed on an upper surface of the circuit board, and a memory disposed on a lower surface of the circuit board, such that the lower surface of the circuit board where the processor is arranged overlaps an area corresponding to where the memory is disposed.

Abstract: A method and system to control crosstalk among qubits on a chip are described. The method includes placing two or more components symmetrically on the chip, the chip including the qubits, and driving two or more ports symmetrically to control the crosstalk based on controlling coupling of chip mode frequencies and qubit frequencies.

Abstract: A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.

Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Abstract: A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a circuit, produce computed cross-talk noise pulses potentially contributing to a maximum noise for the victim net. The MILP is solved to determine the maximum noise at the victim net. Responsive to the maximum noise meeting one or more criteria, at least an indication of the victim net is output. Forming may include forming a linear problem using overlapping timing windows for which noise pulses contribute to the maximum noise and converting the linear problem to the mixed integer linear problem by introducing into the linear problem binary variables that determine whether individual ones of overlapping or non-overlapping noise pulses from the one or more aggressor nets contribute to the maximum noise. Apparatus and program products are also disclosed.

Abstract: A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a circuit, produce computed cross-talk noise pulses potentially contributing to a maximum noise for the victim net. The MILP is solved to determine the maximum noise at the victim net. Responsive to the maximum noise meeting one or more criteria, at least an indication of the victim net is output. Forming may include forming a linear problem using overlapping timing windows for which noise pulses contribute to the maximum noise and converting the linear problem to the mixed integer linear problem by introducing into the linear problem binary variables that determine whether individual ones of overlapping or non-overlapping noise pulses from the one or more aggressor nets contribute to the maximum noise. Apparatus and program products are also disclosed.

Abstract: A circuit analysis device includes: a processor configured to execute a procedure by: calculating, for power supply noise included in a power supply voltage supplied to a semiconductor memory device, variation characteristics of an electric potential relative to the power supply voltage in a specific memory cell included in a memory cell array; calculating power supply noise of a power supply system that occurs when a current is supplied to an equivalent circuit of the power supply system under a predetermined condition, the power supply system including a power supply line and an element for supplying a power supply voltage from a voltage source to a semiconductor device; calculating, from the variation characteristics, the electric potential obtained when the power supply noise is equal to a specific magnitude; and determining, by comparing the calculated electric potential with a threshold, whether memory latch-up will occur in the specific memory cell.

Abstract: On-chip decoupling capacitors and methods for placing the same are disclosed in which designated spaces are created between the active circuits to insert designated capacitor cells. The designated capacitor cells may be placed in designated areas of the integrated circuit that are not simply spaces left empty by cell placement or frontier areas in or around the route, and the dimensions (e.g., height) of the designated capacitor cells may be selected to optimize (increase) capacitance efficiency. The capacitor cells may also be placed to target and reduce the interference between a digital core (aggressor) circuit and a victim analog circuit.

Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.

Abstract: A mechanism is provided in a data processing system for timing-driven routing for noise reduction in integrated circuit design. Responsive to performing timing driving routing on an integrated circuit design, the mechanism identifies a set of noise-critical nets in the integrated circuit design. The mechanism performs timing driven routing on the integrated circuit design with noise constraints based on the set of noise-critical nets.

Abstract: A printed substrate design system includes: an EMI condition determination unit that compares an EMI characteristic derived by an EMI characteristic derivation unit with an EMI allowable condition, and determines whether the EMI characteristic of a printed substrate satisfies the EMI allowable condition; a substrate configuration change unit that changes an internal configuration of the printed substrate to obtain a changed configuration of the printed substrate in a case where the EMI condition determination unit has determined that the EMI allowable condition is not satisfied, and sets design information of the changed configuration of the printed substrate to design information for deriving the EMI characteristic in the EMI characteristic derivation unit; and an output unit that outputs a printed substrate configuration in a case where the EMI condition determination unit has determined the EMI allowable condition is satisfied.

Abstract: A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.

Abstract: A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.

Abstract: A capacitor arrangement assisting method wherein data entered by a user, such as the width w of a power supply wiring, the thickness h of a dielectric between the power supply wiring and a ground plane, the ESLcap of a capacitor, and a target frequency fT and a target impedance ZT of an IC, are received, the maximum allowable wiring length lmax of the power supply wiring is calculated on the basis of the received width w of the power supply wiring, the thickness h of the dielectric, the ESLcap of the capacitor, and the target impedance ZT of the IC at the target frequency fT, and the calculated maximum allowable wiring length lmax is displayed.

Abstract: A method for modeling jitter includes generating a first delay-impacting parameter function for a first signal and a second delay-impacting parameter function for a second signal. A first delay per element function is generated from the first delay-impacting parameter function and a second delay per element function from the second delay-impacting parameter function. A difference in path delay from the first delay per element function and the second delay per element function is identified.

Abstract: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.

Abstract: Disclosed are a system and a method for determining merged resistance values of same-type terminals of multiple electrically connected multi-terminal semiconductor devices (e.g., field effect transistors) in a complex semiconductor structure, wherein all first terminals are connected to a first node, all second terminals are connected to a second node, and all third terminals are connected to a third node. Modified resistor networks are generated from a full resistor network including, but not limited to, a first modified resistor network with shorted second terminals and a second node; a second modified resistor network with shorted first terminals and a first node; and a third modified resistor network with first terminals and first node shorted and with the second terminals and second node shorted. Simulations are performed using the modified resistor networks and, based on the results, merged resistance values for the first, second, and third terminals are determined.