Abstract: A computer-executed method for designing dummy metal object locations in an integrated circuit design. The method comprises the steps of: a) receiving an integrated circuit design as input; b) finding areas of the integrated circuit design that do not meet a minimum metal density requirement; c) finding areas of the integrated circuit design having a critical timing path; d) blocking empty routing tracks that are adjacent to critical nets of the critical timing paths located in step (c), for prospective dummy metal object placement for the areas commonly located in both of steps (b) and (c); and e) placing a minimum number of dummy metal objects in empty tracks such that the minimum metal density requirement is met for the areas that were found in step (b), but were not blocked in step (d).

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.

Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Abstract: A method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor integrated circuit; carrying out calculation for a transferred image in the physical layout; carrying out calculation for a signal delay based on the physical layout, and obtaining a wiring not meeting a specification having the signal delay previously set therein; and setting a portion into which a repeater is to be inserted based on at least one result of results obtained from the information on the graphic and calculation for the transferred image, respectively, with respect to the wiring not meeting the specification.

Abstract: A recording medium stores a verification program that causes a computer to execute detecting from a model circuit, a first circuit representing junction of a source region and a substrate region and including a junction resistance and a junction capacitance, a second circuit parallel to the first circuit, representing junction of a drain region and the substrate region, and including a junction resistance and a junction capacitance equivalent to the junction resistance and capacitance of the first circuit, and a connection resistance connecting the circuits and a substrate electrode; calculating, using the junction resistances and connection resistance, a first coefficient indicating impact of the junction resistances and connection resistance on amplitude variation; calculating, using the junction capacitances and connection resistance, a second coefficient indicating impact of the junction capacitances and connection resistance on phase variation; correcting the junction capacitances using a sum of the coef

Abstract: A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Abstract: A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is routable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.

Abstract: In one embodiment, a method for reducing power supply noise within an electronic system that includes an integrated circuit (IC), a package, and a printed circuit board (PCB) connected by a plurality of power delivery networks (PDN) is disclosed. Power supply noise within the system is reduced by defining a voltage compression limit for each PDN of the electronic system; determining a voltage compression for each PDN of the electronic system during a plurality of switching events; comparing the voltage compression of each PDN of the electronic system to the voltage compression limit for each switching event; and in response to the voltage compression of each PDN of the electronic system exceeding the limit, modifying the electronic system to reduce the voltage compression below the limit.

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.

Abstract: A pin placement determining method includes calculating a waveform deterioration amount of wires from a noise amount of the wires and wiring loss of the wires, the wires being coupled to a connector on a printed board, comparing the calculated waveform deterioration amount of the wires to an evaluation criteria, evaluating the wires in which the waveform deterioration amount exceeds the evaluation criteria, and replacing corresponding pins of the connectors to which the wires that have been evaluated as exceeding the evaluation criteria are coupled with replacement pins of connectors that have a low noise amount.

Abstract: Disclosed are embodiments of a method, system and program storage device for accurately modeling parasitic capacitance(s) associated with a diffusion region of a silicon-on-insulator (SOI) device and doing so based, at least in part, on proximity to adjacent conductive structures. In these embodiments, the layout of an integrated circuit design can be analyzed to determine, for the diffusion region, shape, dimension and proximity information. Then, a formula can be developed and used for determining the parasitic capacitance between the diffusion region and the substrate below (CD-S). This formula can have a perimeter component, including a side edge component and, if applicable, a corner component, both of which account for the fact that CD-S is generally dependent on the distances between the diffusion region and any adjacent conductive structures. Additionally, the parasitic capacitance between the diffusion region and any adjacent conductive structure (CD-D) can be determined based on such distances.

Abstract: A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

Abstract: A method implemented in a computer infrastructure having computer executable code having programming instructions tangibly embodied on a computer readable storage medium. The programming instructions are operable to receive a current waveform of a communication between a plurality of participants. Additionally, the programming instructions are operable to create a voiceprint from the current waveform if the current waveform is of a human voice. Furthermore, the programming instructions are operable to determine one of whether a match exists between the voiceprint and one library waveform of one or more library waveforms, whether a correlation exists between the voiceprint and a number of library waveforms of the one or more library waveforms and whether the voiceprint is unique.

Abstract: An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic.

Abstract: An operation analyzing apparatus (100) for semiconductor integrated circuits according to this exemplary embodiment includes a simulation analyzing unit (140), and the simulation analyzing unit (140) includes: a semiconductor characteristics extracting unit (110) that extracts the inductances L, resistances R, and capacitances C of a board, a package, and a semiconductor integrated circuit, from the semiconductor integrated circuit mounted on the board via the package; an individual network generating unit (111) that generates individual networks of the extracted inductance L, resistance R, and capacitance C with respect to each of said semiconductor substrate, said package, and said semiconductor integrated circuit; an integrated network generating unit (112) that generates an integrated network by integrating all of the generated individual networks; and an operation simulation running unit (113) that performs an operation simulation of the semiconductor integrated circuit by inserting a test noise pattern

Abstract: This is a method of designing a semiconductor device.

Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to calculate the total time delay in a signal path due to crosstalk from a group of crosstalk aggressors that are associated with a group of signal paths. In order to properly account for statistical behaviors in the switching times and directions of the switching patterns in the group of signal paths, the time-delay contribution from each of these crosstalk aggressors may be modeled as a corresponding statistical random variable. Because the number of crosstalk aggressors are usually much larger than the number of stages in the signal path, the calculated total path delay may be less pessimistic. Furthermore, in order to detect potential timing violations, the time-delay contributions from additional dominant crosstalk aggressors can be modeled using non-statistical worst-case deterministic values.

Abstract: In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time.

Abstract: A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X?1 and at least one other matrix, with first equation including X?1Y, X?1A, and X?1P, and the second equation including X?1A and X?1P.

Abstract: A computer-implemented method of generating a library object for an integrated circuit design is disclosed. In one embodiment, the method includes: analyzing a pair of integrated circuit design objects for fringe capacitance effects between the pair of integrated circuit design objects; and generating the library object accounting for the fringe capacitance effects prior to completion of a layout design for the integrated circuit design.

Abstract: Systems and techniques for performing parasitic extraction on a via array are described. If the via array is a single row or column via array, the system identifies a first via and a last via in the via array, and merges a set of vias between the first via and the last via into a center via. If the via array is a M×N (M?2, N?2) via array, the system merges the vias as follows: the first row and the last row of vias in the via array into a first row via and a last row via, respectively; the first column and the last column of vias in the via array into a first column via and a last column via, respectively; and a set of vias between the first and last rows and the first and last columns into a center via.

Abstract: The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, along a first direction, from the integrated circuit. A first set of capacitive elements is closer to the integrated circuit than a second set of capacitive elements. The first set has a smaller capacitance than the second set.

Abstract: A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is also determined. Reduction information on the logic design is gathered based on the initial transient behavior. The netlist is then modified based on the reduction information.

Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

Abstract: According to one embodiment, a design support method includes generating first layout data when first electronic components and first positions of the first electronic components on a printed circuit board are specified, computing temperature distribution data showing a temperature distribution on a surface of the board, acquiring a maximum thermal resistance temperature of the second electronic component when the second electronic component is specified, calculating a first temperature on the surface at a second position based on the temperature distribution data when the second position is specified, determining whether the second electronic component can be arranged at the second position based on the first temperature and the maximum thermal resistance temperature, and prohibiting generation of a second layout data when it is determined that the second electronic component can be arranged at the second position, the second layout data showing the first positions and the second position.

Abstract: A method for modeling bond wires in an IC package for predicting noise effects generated by electromagnetic coupling in complex bond wire configurations. A look-up table of equivalent LC circuit models for the bond wires is generated that accurately predicts the effects of the bond wire circuitry of a signal transmission system. Switch and mirror techniques are applied to reduce the bond wire configurations necessary to simulate.

Abstract: The invention concerns a method for verifying, prior to fabrication, the proper operation of integrated circuit electronic systems using analog signals. It comprises the following steps: identifying (22) the noise-sensitive circuits, setting an acceptable sensitivity template for these noise-sensitive circuits, identifying (34) the noise-generating circuits, modeling the noise, determining (50) the function for transferring noise to the sensitive circuits, and comparing (58) the level of noise reaching the sensitive circuits to an acceptable sensitivity threshold template for the sensitive circuits.

Abstract: A method of manufacturing an integrated circuit having minimized electromigration effect, wherein the integrated circuit comprises one or more interconnect, said the or each interconnect comprising a dielectric layer having an intrinsic parameter at a first defined value, characterized in that said method comprises: identifying one or more characteristics of the or each interconnect; determining a minimal process distance from the or each interconnect for the application of one or more first metal elements; calculating a required correction parameter which can correct the intrinsic parameter at said first defined value; calculating a required number of the first metal elements which have the intrinsic parameter at a second defined value, such that the second defined value provides the required correction parameter for the first defined value; applying a plurality of said first metal elements around the interconnect at said minimum process distance to overcome the problem of electromigration caused by the intr

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: A semiconductor device design support apparatus includes an input unit which inputs layout information, LSI design information, switching information, a primitive library, an electrical current waveform computation unit which obtains an electrical current waveform in instance units, an electrical current dispersion value computation unit which obtains electrical current dispersion values of each segment, a segment dividing unit which judges whether or not the electrical current dispersion value of a segment is not less than a permitted value and divides the segment in cases in which the electrical current dispersion value is not less than the permitted value, a macro-model creation unit which creates a macro-model for each segment; a substrate netlist extraction unit which extracts a substrate netlist, and a substrate noise analysis netlist creation unit which creates a substrate noise analysis netlist from a macro-model of each segment and the substrate netlist.

Abstract: A wiring design assisting apparatus includes an input part that has attribute information of a wiring pattern input thereto; a degradation degree process part that obtains a degradation degree in signal characteristics of a wiring pattern corresponding to attribute information that is input to the input part, based on position information of the wiring pattern corresponding to the attribute information input to the input part, position information and size information of a pattern removed area, and the degradation degree information; and an extracting process part that extracts, for re-wiring, wiring patterns that have degradation degrees equal to or more than a predetermined degree, from wiring patterns for which degradation degrees have been obtained by the degradation degree process part.

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.

Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

Abstract: A system and method is provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.

Abstract: A simulation method includes determining a relationship between stress time and a degradation rate of drain current on a basis of a table in which data of a lifetime of a transistor, or the degradation rate of the transistor, is written, and calculating an amount of change in drain current accordance with the degradation rate, using a table in which information indicating a change in the drain current, being dependent on voltage, is written, based on actually measured data of drain current of the transistor after degradation, drain current in an initial state of a particular transistor model, and the relationship between stress time and the degradation rate of drain current.

Abstract: A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.

Abstract: A computer implemented method, system, and/or computer program product reduce noise in a circuit. A level of noise imposed by an aggressor line on a victim line is determined. The aggressor line and the victim line are an aggressor/victim line pair from multiple aggressor/victim line pairs in a circuit. Determination of the noise level is conducted during a predetermined window of time during which a signal is being transmitted along the aggressor line. Each of the multiple aggressor/victim line pairs are ranked according to a level of noise being imposed by each aggressor line on each victim line. The spacing between a highest ranked aggressor/victim line pair is then expanded.

Abstract: A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.

Abstract: Provided is a method of exactly calculating the delay of a gate in a digital integrated circuit (IC) that drives a capacitive load and a noise current source based on a crosstalk effect due to capacitive coupling between adjacent conductive lines, the method calculates the delay of the gate by using an output waveform that sums an output waveform of a linear time-varying output resistance model generated by using a gate output resistance library generated by using input and output voltage values of the digital IC and an output waveform of a modified Thevenin equivalent model of the gate.

Abstract: Techniques are presented for accounting for parasitics in the automated design of integrated circuits. In one set of techniques, model values for parasitic models are received on a schematic environment from a user, the parasitic models are evaluated from the schematic using the received model values, the parasitic models are transferred to a layout environment, and the transferred parasitic models are evaluated on the layout environment. In other techniques, model values are received for parasitic models from a user, the parasitic models are evaluated on the layout environment, and the process then backannotates the parasitic models evaluated on the layout environment and corresponding parameter values to a schematic environment.

Abstract: According to an aspect of the present invention, statistical timing analysis is applied with respect to a stress degradation that occurs in fabricated integrated circuits (IC) when used for a long duration. The circuit design may be suitably modified to account for the degradations (e.g., those caused by NBTI and CHC for transistors, those caused due to electromigration in case of interconnects). As a result, the fabricated ICs may be less susceptible to such degradations. The features are extended to model complex circuit blocks and also account for different degrees of stress that different circuit blocks are subjected to, in a same age of operation.

Abstract: A system and method for storing power utilization information in an integrated circuit and utilizing such information. Various aspects of the present invention provide an integrated circuit that comprises a first module, which stores power utilization information for at least a portion of the integrated circuit. A second module of the integrated circuit may communicate the power utilization information with an electrical device external to the integrated circuit. Various aspects of the present invention provide a method for storing power utilization information in an integrated circuit. For example, a performance characteristic and/or a power supply characteristic may be monitored as the integrated circuit is utilized. Power utilization information may be determined from the monitored characteristic(s), and the power utilization information may be stored in the integrated circuit.

Abstract: A designing apparatus includes an initial estimating portion, a general power supply noise analyzing portion, a layout designing portion, a detail estimating portion, a detail power supply noise analyzing portion, and a layout adjusting portion. The initial estimating portion estimates general values of an entire consumed current and an entire on-chip capacitance. Based on the estimated general values, the general power supply noise analyzing portion creates a lumped constant circuit model so as to conduct a power supply noise analysis, for computing a current-capacitance ratio. Based on the current-capacitance ratio, the layout designing portion performs placement of cells for each of predetermined regions obtained by dividing a placement region. The detail estimating portion creates a lumped constant circuit model for each of the predetermined regions so as to estimate detail values of the consumed current and the on-chip capacitance for each of the predetermined regions.

Abstract: A method is provided to evaluate crosstalk effect of aggressor switching upon victim net signal transition time within an integrated circuit comprising: combining a first probability density function (PDF) of first aggressor switching time in response to a first input signal to an aggressor net driver and a second aggressor switching time in response to a second input signal to the aggressor net driver; determining a delay change curve that represents a relationship between delay change of arrival time of a victim net signal transition and relative alignment of the aggressor net driver switching time and a victim net driver switching time; and determining a third PDF of delay change of a transition of the victim net signal based upon the combination and the delay change curve.

Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.