Abstract: A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.

Abstract: A method for matching building floor plans with specifications for blocks of land wherein the building floor plans comprise image files; the method comprising: storing specifications for each of a plurality of blocks of land in a database the specifications including lengths of block sides; processing the image files of each of the building floor plans to thereby store specifications for each of said plans in the database the processing including: converting text in each plan into parseable text and identifying numerical values in the string to extract length and width values for external dimensions of the floor plan, and identifying one or more orientation critical words from the text string and its position on the plan; and querying the database to determine compatible matches between a selected one of the building floor plans and the blocks of land, or vice-versa, taking into account the specifications including the extracted length and width values and the orientation critical words.

Abstract: In an example implementation, a method of compensating for dimensional variation in 3D printing includes receiving a 3D object model that represents a 3D part to be printed. The method also includes receiving a build material type and a position for printing the 3D part within a build volume. The method includes determining from the position, target subvolumes of the build volume into which the 3D part is to be printed, retrieving a dimensional compensation factor associated with each target subvolume, and then applying each dimensional compensation factor to the 3D object model to scale the 3D part according to the position of the 3D part within the build volume.

Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.

Abstract: One example method of operation may include creating a force approximation of a number of nodes in a defined space at an initial time (t0), the force approximation being based on a data realization simulation model of an n-body simulation, where n is an integer greater than one. The method may also include determining initial displacement changes of one or more of the nodes within the defined space has occurred in the force approximation, summing the initial displacement changes of the one or more of the nodes to create a summed total displacement, creating an initial displacement threshold (Td) based on the summed total displacement.

Abstract: A circuit board component layout determination method includes the steps of: (1) simulating the placement of components by a circuit board layout software program; (2) performing a circuit board component layout density analysis to obtain a circuit board component layout density percentage; (3) determining whether or not the simulated placement of components is feasible according to the circuit board component layout density percentage, and if yes, carrying out step (4); and (4) placing the components into the circuit board. The method uses a circuit board layout software program and a spreadsheet or a database to calculate the statistics of an area of a circuit board that can be laid and an area of the circuit board that cannot be laid, so as to analyze and determine the implementability of a component layout, and improve the control, efficiency and cost-effective of the component layout of the circuit board.

Abstract: An integrated circuit, comprising a transistor-based cell comprising a set of fin field effect transistors (Fin FETs) chained together in a first direction, wherein the set of Fin FETs include fins extending longitudinally along the first direction and equally-spaced apart in a second direction orthogonal to the first direction by a fin pitch, and a set of polysilicon gates extending longitudinally along the second direction and equally-spaced apart in the first direction by a poly pitch, wherein a first dimension of the transistor-based cell along the first direction is substantially a first integer multiplied by the poly pitch, and wherein a second dimension of the transistor-based cell along the second direction is substantially a second integer multiplied by the fin pitch. The integrated circuit may include other non-transistor-based cells (e.g., passive cells), such as thin-film resistor or capacitor cells, which are arranged in a two-dimensional array with the transistor-based cell.

Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.

Abstract: In general, embodiments of the present invention provide systems, methods and computer readable media for generating a tiling for a physical placement of a plurality of circuits. The method includes generating a tiling including a plurality of tiles, where each tile identifies a tile geometric area, and a list of one or more of the circuits to be placed in the tile geometric area. The tiling is based on a description of one or more user constraints, where each user constraint identifies a constraint geometric area, and a characteristic of circuits to be placed in the constraint geometric area.

Abstract: A positioning method of rectangular pin element based on vertex points includes the steps of: obtaining component information and classifying components of a model into two classes; extracting feature descriptors of each vertex point of pin element of the model; obtaining a real image of the component and extracting feature points and an angle between two straight lines where the feature points are located and the positive direction of the X-axis respectively; obtaining a rotation angle and an precise feature point position; determining an precise feature point position corresponding to all the vertex points; obtaining feature descriptor of the vertex points of the actual component pin, a weight value of the vertex points of the component in the model, the vertex points of the actual component corresponding to feature point; and determining the final position of the center of the chip and a precise rotation angle of the chip.

Abstract: A SoC interconnect network topology is represented. The corresponding SoC floorplan is divided into windows, which are contiguous and non-overlapping. Within each window a subnetwork of the SoC interconnect network topology is defined that includes links or communication paths between IP blocks in the window as well as links or communication paths that traverse the window. At the shared boundaries of the windows, ports are added and defined as virtual ports. The overall SoC topology can be optimized and synthesized by optimizing each window independently and then incrementally optimizing all links, from end-to-end, that traverse two or more windows. The SoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of elements within the floorplan is automatically computed and recommended. Locations can also be edited. Statistical metrics are calculated, including wire length, switch area, SoC area, and maximum signal propagation rate.

Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.

Abstract: The present disclosure is directed to associating computing devices with each other based on computer network activity for selection of content items as part of an online content item placement campaign. A first linking factor is identified based on a connection between a first device and the computer network via a first IP address during a first time period, and based on a connection between a second device and the computer network via the first IP address during the first time period. A number of devices that connect with the computer network via the first IP address is determined. A positive match probability is generated. A second and third linking factors are monitored. A negative match probability is determined based on the second and third linking factors. The first device is linked with the second device based on the positive and negative match probabilities.

Abstract: Devices, methods, computer readable media, and other embodiments are described for design and verification of safety critical electronic systems. Some embodiments integrate functional safety (FS) data with circuit design data for use in electronic design automation (EDA) operations. One embodiment involves a device accessing FS and circuit design data; automatically analyzing register transfer level (RTL) design data using the FS data to perform one or more FS quality checks; and placing and routing the circuit design using the RTL design data and the set of FS data to perform FS-aware placement and routing. In some embodiments, failure modes and associated safety mechanisms to improve safety metrics associated with failure modes are automatically added to the circuit design during EDA operations. In other embodiments, additional FS-aware operations are performed. In some embodiments, the FS data is structured as a single Unified Safety Format (USF) file.

Abstract: A device configured to authenticate an integrated circuit includes an integrated circuit on a substrate, and at least one security circuit segmented into at least two security parts. The two security parts are located at separate locations on the substrate with respect to one another. At least one of the security parts includes a memory element having a key code programmed therein that authenticates the integrated circuit.

Abstract: A processor-implemented method for automatically generating a layout of a cell of a semiconductor circuit is provided herein. The processor-implemented method includes reading a netlist of the cell. The netlist includes a description of internal electrical nets connecting electrical components of the cell with each other. The processor-implemented method assigning a weight to an internal net of the internal electrical nets and placing the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: Disclosed is an approach to implement snapping techniques that aid the interactive, assisted, or automatic placement of layout instances or groups of layout instances for generating a legal placement layout while reducing or entirely eliminating any subsequent or separate performance of design rule checking with respect to the relevant design rules, constraints, or requirements governing the legality of the instances or groups of instances placed in the placement layout.

Abstract: A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. A layout pattern including at least two adjacent rectangular sub patterns is provided. The layout pattern is then input into a computer system. An optical proximity correction including a bevel correction is then performed. The bevel correction includes forming a bevel at a corner of at least one of the two adjacent rectangular sub patterns, wherein the bevel is formed by chopping the corner, and moving the bevel toward an interaction of two neighboring segments of the bevel if a distance between the bevel and the other rectangular sub pattern is larger than a minimum value. The angle between a surface of the bevel and a surface of the rectangular sub pattern is not rectangular. The layout pattern is output to a mask after the optical proximity correction.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: Disclosed are techniques for implementing placement using row templates for an electronic design using row templates. These techniques identify or create a row region in a layout of an electronic design. A row template is applied to the row region to create one or more placement rows in the row region. One or more layout circuit components may then be placed into one or more rows or at one or more locations to create a legal placement layout by guiding placement of the one or more layout circuit components with the row template.

Abstract: A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: Embodiments of the invention provide an approach for creating, evolving and using a weighted semantic graph to manage and potentially identify certain information assets within an enterprise. The semantic graph may be generated by monitoring users navigating through search results which provide a set of information assets responsive to a search query. By recording the navigation path taken by many users, relationships between information assets may be identified. Further, once generated, the semantic graph may be used to present users with an indication of related information assets as part of the search results. Further still, the semantic graph may also be used to identify information assets “hubs” as well as information assets that may provide low utility to individuals within the enterprise.

Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.

Abstract: The present disclosure relates to methods, processing systems and computer program products of global routing of integrated circuits based on localized routing optimization. In certain embodiments, the method may include one or more of: defining one or more regions, one or more netgroups, and combinations thereof of an integrated circuit, associating at least one optimization objective with each region and/or each netgroup defined, generating one or more constraints for each region and/or each netgroup based on the associated optimization objectives, and performing global routing of the integrated circuit according to the one or more constraints.

Abstract: A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.

Abstract: An example method is disclosed that includes identifying a training set of images, wherein each image in the training set has an identified bounding box that comprises an object class and an object location for an object in the image. The method also includes segmenting each image of the training set, wherein segments comprise sets of pixels that share visual characteristics, and wherein each segment is associated with an object class. The method further includes clustering the segments that are associated with the same object class, and generating a data structure based on the clustering, wherein entries in the data structure comprise visual characteristics for prototypical segments of objects having the object class and further comprise one or more potential bounding boxes for the objects, wherein the data structure is usable to predict bounding boxes of additional images that include an object having the object class.

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: The invention provides a method of designing an integrated circuit. The method includes providing a physical layout group including a first layout corresponding to a first die having a first function. A second layout corresponds to an interposer configured for the first die connected thereon. The first physical layout group is partitioned into a first physical layout partition according to the first function. A first automatic place-and-route (APR) process is performed to obtain a first hierarchical layout according to the first physical layout partition. A first verification is performed on the first hierarchical layout.

Abstract: Various implementations described herein are directed to systems and methods for mitigating contact resistance. In one implementation, a method may include analyzing operating conditions for cells of an integrated circuit. The method may include selectively marking instances of the cells having timing degradation along a critical path of the integrated circuit. The method may include reducing contact resistance for the selectively marked instances of the cells having timing degradation.

Abstract: A layout of a cell grid comprises a plurality of polycrystalline silicon (POLY) lines in the cell gird, wherein the POLY lines are arranged horizontally and evenly spaced with a pitch X, and a plurality of fin-shaped oxide diffused (OD) regions in the cell gird, wherein the fin-shaped OD regions are arranged vertically and evenly spaced with a pitch Y, wherein the pitch Y of the fin-shaped OD regions defines width of the cell grid. The layout of the cell grid further comprises a plurality of PMOS transistors and NMOS transistors in the cell grid, wherein the PMOS transistors and NMOS transistors have their source nodes and drain nodes formed in the fin-shaped OD regions and their gates connected to the POLY lines, wherein the plurality of PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell grid.

Abstract: A system, method, and computer program product are provided for generating a view of an area for positioning resources, based on parameters of the resources. In operation, one or more planned resources to be located in an area are identified. Additionally, at least one parameter of each of the one or more planned resources is determined. Furthermore, a view of the area is generated including possible locations to position the one or more planned resources, based on the at least one parameter.

Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.

Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.

Abstract: A system for parallelizing software in computer-aided design (CAD) software for circuit design includes a computer. The computer is configured to form or optimize a plurality of clusters in parallel. Each cluster in the plurality of clusters includes a set of nodes in a netlist in a design. The computer is configured to determine placements for blocks in a netlist in parallel, based on iterative improvement, partitioning, or analytic techniques.

Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units.

Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.

Abstract: A computing device segments an image into a plurality of segments, wherein each segment of the plurality of segments has a segment location and a set of pixels that share visual characteristics. The computing device determines an initial set of bounding boxes for the image based on the plurality of segments. The computing device determines a reduced set of bounding boxes based on combining bounding boxes of the initial set of bounding boxes, the reduced set of bounding boxes corresponding to one or more objects in the image, each of the one or more objects having an object class and an object location.

Abstract: An integrated circuit layout structure and method thereof establishes cell rows with different cell heights for accommodating cells with corresponding heights, such that an area of an integrated circuit can be fully utilized. Therefore, it reduces an area wasted by an unnecessary uniform cell height, so as to improve integration of the integrated circuit.

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

Abstract: A particular three-dimensional integrated circuit stack includes a first die including a first bonding interface and a first plurality of interconnect layers arranged according to a first Manhattan wiring scheme. The three-dimensional integrated circuit stack also includes a second die including a second bonding interface and a second plurality of interconnect layers arranged according to a second Manhattan wiring scheme. The first die and the second die stacked with the first bonding interface coupled to the second bonding interface such that the first Manhattan wiring scheme and the second Manhattan wiring scheme are non-Manhattan with respect to each other.

Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.

Abstract: A design-support-apparatus includes a storage unit that stores mounting information on an order of manufacturing processes, first-region-information indicating a region to be secured in mounting of each component on the substrate, second-region-information indicating a region occupied when each component is mounted on the substrate, a discrimination unit configured to determine a before-and-after relationship between manufacturing processes of mounting a first-component and a second-component that are arranged on the substrate, an acquisition unit configured to acquire the first-region-information for the component of which the manufacturing process is determined to be later by the discrimination unit between the first component and the second-component and acquire the second-region-information for the component of which the manufacturing process is determined to be earlier, and a determination unit configured to compare the first-region-information and the second-region-information so as to determine presenc