Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

Abstract: A method and system for generating a physical layout for a grating coupler integrated in a photonically-enabled circuit are disclosed herein. In some embodiments, the method receives a parametrized wavelength, a parametrized first refractive index, a parametrized second refractive index, a parametrized taper length, a parametrized width, a parametrized grating length, and a parametrized incident angle of the optical beam incident onto the grating coupler and generates a physical layout for the grating coupler based on the received parametrized inputs, the generating of the physical layout is according to a predefined model, and outputs the physical layout of the grating coupler for manufacturing under a semiconductor fabrication process.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a plurality of first logic cells having a first cell height, a plurality of second logic cells having a second cell height, and a plurality of metal lines parallel to each other in a metal layer. The second cell height is different than the first cell height. The first logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array. The metal lines covering the first and second logic cells are wider than the metal lines inside the first logic cells, and the metal lines inside the first logic cells are wider than the metal lines inside the second logic cells.

Abstract: Various embodiments provide for context-aware circuit design layout construct, which may be part of electronic design automation (EDA). In particular, some embodiments enable use of a circuit design layout construct with a layout of a circuit design (hereafter, a circuit design layout), where a programmable pattern of layout shapes of the circuit design layout construct can be inserted into a circuit design layout and can be adapted based on context information associated with the location of its placement within the circuit design layout.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: The disclosure discloses a layout design method, chip and terminal of power device, wherein the non-top metal layout design: the metal is routed along the first direction and several metal wires that fully occupy the available area of the die unit are thereby obtained, and the wiring properties of the metal wires are sequentially changed at intervals, making the source ends and the drain ends of the device are alternately distributed at intervals, and the metal routing in two or more layers of non-top metal are arranged vertically; the top metal layout design: the source end region and drain end region in the top metal are formed into sheets independently and the pad is arranged in the top metal region; eventually realize the interconnection of metal layers and complete the layout design.

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, a plurality of n-type wells that each extend from the upper surface into the semiconductor body, first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body at least as deep as the p-type wells, and second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body at least as deep as the n-type wells, wherein the p-type wells and the n-type wells alternate with one another a first direction, and wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.

Abstract: A method of driving design on gate electrodes includes steps of: determining position information of a gate-on-array (GOA) device in an available drawing space according to a size design information and a resolution design information of a display panel, based on user configuration; determining target GOA design strategy information used for a current gate electrode driving design among a plurality of preset GOA design strategies; and drawing a GOA device pattern in the available drawing space of the GOA device, based on the target GOA design strategy information.

Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: generating a first embedding for a semiconductor element to be placed in a canvas based on feature information and logical design information of the semiconductor element by using a first neural network; and generating a probability distribution for placing the semiconductor element based on the first embedding and a second embedding for semiconductor elements already placed in the canvas by using a second neural network.

Abstract: A semiconductor device including a cell region which includes components representing a circuit arranged such that a rectangular virtual perimeter is drawable around substantially all of the components and includes first and second virtual side boundaries, the components including: a first conductor which is an intra-cell conductor of a first signal that is internal to the circuit, a first end of the intra-cell conductor being substantially a minimum virtual boundary offset inside the first virtual side boundary; and a second conductor of a second signal of the circuit; a portion of the second conductor having a first end which extends outside the first virtual side boundary by a protrusion length substantially greater than the minimum virtual boundary offset; and a second end of the second conductor being receded inside the second virtual side boundary by a first gap substantially greater than the minimum virtual boundary offset.

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Abstract: A method of manufacturing an integrated circuit includes adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first and second pair of conductive patterns on the corresponding first and second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and a second set of conductive structures based on the second pair of conductive patterns. A first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. One spacing of a first set of spacings is different from another spacing of the first set of spacings.

Abstract: Automated circuit and layout generation is disclosed. Various embodiments may include a computer system and/or method for generating a circuit layout comprising specifying a circuit schematic to be converted to a circuit layout, receiving a layout script associated with the circuit schematic, the layout script configured to position a plurality of layout instances generated from the circuit schematic, converting the circuit schematic into the plurality of layout instances; and positioning the plurality of layout instances based on the layout script to produce the circuit layout. A circuit may be produced by fabricating a circuit using the layout.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: A method for the development of a compilation process for a quantum circuit on a quantum processor, includes an implementation step of the compilation method including an iteration loop successively including: a step of simulation of a given implementation of the logical qubits on the physical qubits of the quantum processor; a step of detecting, in the quantum circuit, ineffective quantum gate(s); a step of estimating the number of quantum swap gates to be inserted into the quantum circuit so that all of the quantum gates of the quantum circuit are effective; and a retroaction step, by way of a simulated annealing, involving a new step of simulation, until attaining, whereupon all the quantum gates are effective: either a minimum threshold of the number of estimated quantum value swap gates between two physical qubits, or a maximum threshold of iterations in the loop.

Abstract: Disclosed is an artificial intelligence-based semiconductor design method performed by a computing device. The artificial intelligence-based semiconductor design method includes: inputting state map information related to a connection relationship between semiconductor devices to a Convolutional Neural Network (CNN) of a semiconductor placement model; placing the semiconductor device based on an output of the convolutional neural network; and training the semiconductor placement model based on the placement of the semiconductor devices.

Abstract: A method for assigning connections between IO pad pins and connectors on an integrated circuit (IC) die. A pattern (300) including a physical layout of connectors (302) and pad pins (304) is associated with a mapping of connections between the connectors (302) and the pad pins (304). A processor (204) identifies instances (402, 404) of the pattern (300) within a design image (400) of an integrated circuit (IC) die using a machine learning model. The design image (400) includes a physical layout of connectors (414) and pad pins (416). For each identified instance (402, 404) of the pattern (300) within the design image (400), the mapping of connections is assigned to respective connectors (414) and pad pins (416) in the identified instance (402, 404).

Abstract: Methods for iteratively optimizing a two-dimensioned tiled area such as a lithographic mask include determining a halo area around each tile in the tiled area. An extended tile is made of a tile and a halo area. Each extended tile in the tiled area is iterated until a criterion is satisfied or a maximum number of iterations is met. Optimizing the extended tile produces a pattern for the tile such that at a perimeter of the tile, the pattern matches adjacent patterns that are calculated at perimeters of adjacent tiles.

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Abstract: The apparatus according to various embodiments includes one or more processors, and one or more memories operatively connected to the one or more processors. The one or more memories may store instructions that, when executed, cause the one or more processors to acquire a plurality of first position offsets of a plurality of first components respectively mounted on a plurality of first substrates with respect to a plurality of pads of the plurality of first substrates corresponding to the plurality of first components from the optical measurement device, set a range of a normal state for a component position offset based on the plurality of first position offsets, generate a control signal for adjusting at least one control parameter of the component mounting device associated with a component mounting position based on the range of the normal state, and transmit the control signal to the component mounting device.

Abstract: Disclosed is a semiconductor device comprising an active region that protrudes upwardly from a substrate, a plurality of channel patterns that are spaced apart from each other in a first direction on the active region, and a gate electrode that extends in the first direction on the active region and covers the plurality of channel patterns. Each of the plurality of channel patterns includes a plurality of semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the active region. The gate electrode covers the top surface of the active region between the plurality of channel patterns.

Abstract: A simulation-based framework for optimizing resource allocation and layout design is disclosed.

Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

Abstract: A method (of generating a layout diagram) includes: generating a shell including wiring patterns in a first layer of metallization, the wiring patterns having long axes which are substantially aligned with corresponding tracks that extend in a first direction, the wiring patterns having a default arrangement which has, relative to the corresponding tracks, a first amount of free space; and refining the shell into a cell, the refining including selectively shrinking, in the first direction, one or more of the wiring patterns resulting in a second amount of free space, the second amount being greater than the first amount, increasing, in the first direction, one or more chosen ones of the wiring patterns (chosen patterns), and backfilling the second amount of free space with one or more of at least one dummy pattern or at least one wiring pattern.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Abstract: A chip layout method based on a minimum total wire length, includes: initializing a total wire length to a preset value, initializing a number of iterations, randomly generating a sequence pair to represent a positional relationship between rectangular circuit modules, inputting the sequence pair to a model, and solving to obtain a sequence pair having a minimum wire length within the number of iterations; changing a field operator of the sequence pair to obtain a new one, inputting the new sequence pair to the model, retaining, if an obtained total wire length is less than the original total wire length, the new sequence pair, or otherwise, abandoning the new sequence pair; repeating the above operation till the number of iterations is reached; and outputting a minimum total wire length, and coordinates of each rectangular circuit module to obtain the chip layout based on the minimum total wire length.

Abstract: A method of manufacturing an integrated circuit includes generating a layout of a first and a second cell, adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first pair of conductive patterns on the first set of routing tracks, placing a second pair of conductive patterns on the second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and forming a second set of conductive structures based on the second pair of conductive patterns. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with efficient cell cloning. A cell instance corresponding to multiple similar cell instances in a view of an electronic design may be identified, where the cell instance is instantiated from a master parameterized cell. An analysis engine may be configured at least by associating a parameter of the master parameterized cell with multiple different parameter values respectively corresponding to the multiple similar cell instances. An analysis result including respective metric values corresponding to the multiple similar cell instances may be generated at least by performing an analysis that sweeps across the multiple different parameter values.

Abstract: An integrated circuit includes at least one first area including logic circuitry. The logic circuitry includes library blocks selected from a logic circuit library. A first one of the library blocks is provided with at least two symmetry mirror edges perpendicular to a height of the library blocks. Two adjacent ones of the library blocks are joined at a common symmetry mirror edge.

Abstract: Disclosed herein is a method of facilitating creating a computer application based on a natural language. Accordingly, the method may include receiving, using a communication device, a request from a builder device. Further, the method may include transmitting, using the communication device, a user interface on the builder device. Further, the method may include receiving, using the communication device, the workflow from the builder device. Further, the method may include analyzing, using a processing device, the workflow. Further, the method may include generating, using the processing device, an application file based on the analyzing. Further, the method may include deploying, using the processing device, the application file on at least one end-user device.

Abstract: A method of designing a layout of a semiconductor device includes determining from among a plurality of integrated circuit (IC) blocks in the semiconductor device a selection IC block for which a layout is to be changed, changing an spacing interval at which fin structures included in the selection IC block are spaced apart from each other in a first direction from a first spacing interval to a second spacing interval, and determining in the selection IC block locations of source/drain regions connected to the fin structures spaced apart from each other in the first direction at the second spacing interval.

Abstract: A discrete multi-row height cell in a hybrid row-height system with a plurality of rows of at least two different row-heights is disclosed. The discrete multi-row height cell includes: a first sub-cell deployed on a first row with a first row-height; a second sub-cell deployed on a second row with a second row-height, wherein the second row and the first row is separated by a third row with a third row-height, wherein the third row-height is different from the first row-height, wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire.

Abstract: Static random access memory (SRAM) and its forming method are provided. The forming method includes: providing a semiconductor substrate including memory cell regions, each memory cell region including a transmission region, a pull-down region and a pull-up region including a pull-up fin cutting region; forming first fins on the transmission region and the pull-down region; forming second initial fins on the pull-up region; forming initial gate structures across the first fins and the second initial fins; forming a dielectric layer on the semiconductor substrate, the first fins and the second initial fins; forming a mask layer on the dielectric layer and the initial gate structures; forming a first cutting layer in the initial gate structures at a bottom of the mask opening; and forming a second cutting layer on the pull-up fin cutting region in the dielectric layer at the bottom of the mask opening and in the second initial fins.

Abstract: In one embodiment, an integrated circuit includes a first pattern metal layer, a second pattern metal layer formed over the first pattern metal layer, wherein the second pattern metal layer comprises a second plurality of metal tracks extending in a first direction and less than 9, a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including, a first metal track segment, a second metal track segment shifted in a second direction from the first metal track segment, and a third metal track segment shifted in the second direction from the second metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment, the second metal track segment, and the third metal track segment are within a double cell height in the second direction.

Abstract: A method of updating a boundary space configuration of an IC layout cell includes identifying a pin in the IC layout cell as a boundary pin, determining that a boundary spacing of the boundary pin is capable of being increased, and based on the determination that the boundary spacing of the boundary pin is capable of being increased, modifying the IC layout cell by increasing the boundary spacing of the boundary pin. At least one of the identifying, determining, or modifying is executed by a processor of a computer.

Abstract: A method (of generating a layout diagram) includes: generating one or more first conductive patterns representing corresponding conductive material in the first metallization layer, long axes of the first conductive patterns extending substantially in a first direction; generating a first deep via pattern representing corresponding conductive material in each of the second via layer, the first metallization layer, and the first via layer; relative to the first direction and a second direction substantially perpendicular to the first direction, aligning the first deep via pattern to overlap a corresponding component pattern representing conductive material included in an electrical path of a terminal of a corresponding transistor in the transistor layer; and configuring a size of the first deep via pattern in the first direction to be substantially less than a permissible minimum length of a conductive pattern in the first metallization layer.

Abstract: A protection method for protecting an FPGA against natural radiation, the method comprising the steps of: defining at least one category of constraining signals defined so that a predetermined placement and routing tool cannot route more than a determined maximum number of different constraining signals to any one zone of the surface of the FPGA; replicating an initial logic module in order to obtain a plurality of replicated logic modules forming a replicated logic cell; and associating constraining signals with the replicated logic modules in such a manner that the number of constraining signals associated with the replicated logic cell is greater than a determined maximum number in order to force the placement and routing tool to place the replicated logic modules of the replicated logic cell in distinct zones of the surface of the FPGA.

Abstract: A method for enhancing routability in a cell-based design includes: obtaining a layout corresponding to a placement of cells in the cell-based design; identifying one or more areas of the layout where routability is predicted to be constrained; selectively adding white spaces to the identified one or more areas of the layout where routability is predicted to be constrained to thereby generate a modified layout; legalizing placement of the modified layout; and running a detailed routing on the modified layout.

Abstract: A computing device translates each of a group of structured language graphical process flow element representations, that each represents within a structured language one node of a captured graphical process flow diagram of a first business process, into one of a group of numerical strings that each represents within a set of data fields the respective node and connections to and from the respective node. The group of numerical strings is sequenced in accordance with values of the respective data fields within each numerical string that represents the respective node and the connections to and from each represented node of the captured graphical process flow diagram of the first business process.

Abstract: An interference determination apparatus includes: an acquisition unit that acquires region information indicating regions set in a configuration space in which the angles of rotation of two or three specific joints of an articulated robot are indicated by coordinate axes, the regions including an interference region in which the robot is determined to interfere with itself or an obstacle based on the magnitudes of the angles of rotation of the specific joints, and a non-interference region in which the robot is determined to not interfere with itself or an obstacle based on the magnitudes of the angles of rotation of specific joints; and a determination unit that determines whether the robot interferes with itself or an obstacle, by determining whether coordinates indicating a posture determined by the angles of rotation of the specific joints belong to the interference region or the non-interference region indicated by the acquired region information.

Abstract: A semiconductor memory device of an embodiment has stacked semiconductor memories, each semiconductor memory including first lines intersecting with second lines, and resistive change elements each disposed between one of the first lines and one of the second lines. In two of the semiconductor memories adjacent to each other in the stacking direction, either two of the first lines or two of the second lines are disposed along and in contact with each other. A first contact electrically connected to the second line of the uppermost semiconductor memory passes through a region between the second lines of each of the semiconductor memories located below the uppermost semiconductor memory, and a second contact electrically connected to the second line of each of the semiconductor memories located at an intermediate level passes through a region between the second lines of each of the semiconductor memories located below the intermediate level.

Abstract: Methods, systems and computer program products for avoiding Boolean DRC failures during cell placement are provided. Aspects include generating a semiconductor layout by filling a plurality of rows within a macro block with cells including functional cells and fill cells. Aspects also include modifying the semiconductor layout by removing one or more fill cells from the macro block to create a gap. Aspects also include examining a set of cells that border edges of the gap to identify one or more predicted rule violations. Based on the identified one or more predicted rule violations, aspects also include modifying the semiconductor layout to change a shape of the gap to avoid the one or more predicted rule violations.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.

Abstract: Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.

Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

Abstract: A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the first active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.