Abstract: A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

Abstract: A region of congestion is detected at a set of layers. The region occupies the same area of each layer in the set. A routing blockage is defined as a tuple corresponding to the region. The tuple includes a set of coordinates to describe an area of the region, a first and a second layer coordinates of a first and a second layer in the set of layers. The routing blockage is applied during an iteration of rough routing. Before an iteration of detailed routing, the routing blockage is removed. Detailed routing is performed using a g-cell in the region. The detailed routing uses a routing capacity saved in the g-cell during the iteration of rough routing due to the routing blockage. A revised IC design is produced where a revised congestion in an area corresponding to the region is reduced.

Abstract: Optimized buffer placement is provided based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. An estimated slack is calculated for each branch, the branches are arranged according to the calculated slack, decoupling buffers are inserted in all branches except the most critical branch(es), the most critical branch(es) are globally routed and slew conditions are fixed within this branch, and at least one next branch is globally routed and slew conditions are fixed therein.

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another.

Abstract: A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.

Abstract: A method of assisting in the design of a logic circuit enabling the placement and wiring of cells (logic operation elements) to be optimized on an IC substrate in a short period of time even when the logic circuit has multiple levels, to provide a device assisting in the design of a logic circuit using this method, and to provide a computer program executable by this device. The cells of all levels are placed in a placement area formed on a grid, and a port enabling connection to a cell in another level is placed in a boundary portion between the placement area having cells already placed and a placement area enabling placement of new cells. Cells in the same level are wired between cells and cells in another level are wired between a cell and a port so that the sum total of the wiring lengths may be minimized.

Abstract: A receiving unit receives specification of two parts to be connected by wirings and the number of wirings connecting the two parts. A generating unit generates a schematic route connecting the two parts on a substrate with a width in accordance with the number of wirings received by the receiving unit. A derivation unit derives the number of arrangeable wirings by checking interference whether the schematic route generated by the generating unit is capable of being arranged on the substrate.

Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.

Abstract: In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.

Abstract: In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.

Abstract: An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.

Abstract: A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: A flip-flop operating with standard threshold voltage MOS devices as compared with high threshold voltage MOS devices may have improved speed performance, but greater leakage current. Likewise, a flip-flop operating with high threshold voltage MOS devices may reduce the leakage current and have better power efficiency, but decreased speed and performance. An optimized flip-flop may include a combination of standard threshold voltage MOS devices and high threshold voltage MOS devices. The optimized flip-flop may have less leakage during stand-by mode as compared to a flip-flop with standard threshold voltage MOS devices. In addition, the optimized flip-flop may have better performance and speed as compared to a flip-flop with high threshold voltage MOS devices.

Abstract: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.

Abstract: Dual-structure clock tree synthesis (CTS) is described. Some embodiments can construct a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree. Each upper-level clock tree can be optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew. Next, for each leaf of each upper-level clock tree, the embodiments can construct a lower-level clock tree to distribute a clock signal from the leaf of the upper-level clock tree to a set of clock sinks. The lower-level clock tree can be optimized to reduce latency, power consumption, and/or area.

Abstract: An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a shape with a perimeter; offsetting at least a part of a segment of the perimeter of the shape from the perimeter to generate an offset segment; forming a route segment in response to the offset segment; generating at least a part of a route with the route segment; and routing a net in the layout of the integrated circuit using the part of the route. Nets for integrated circuits may be routed using such techniques.

Abstract: An assignment method of terminals of a semiconductor package executed by an assignment supporting apparatus includes: deciding a maximum allowable distance to be a constraint condition regarding a relative distance between each of the pads and a terminal to be assigned to the pad, and extracting one or a plurality of assigned terminal candidates for each of the pads so that the relative distance between each of the pads and a terminal selected for the pad falls within a range of the maximum allowable distance; and deciding one of the terminals as a assigned terminal based on the assigned terminal candidates and assigning the one of the terminals to one of the pads. The process is a process to assign one of the terminals with priority to a pad having a smallest number of assigned terminal candidates in a not-assigned condition based on the assigned terminal candidates.

Abstract: A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending horizontally on the substrate and placed on one of a plurality of equally spaced vertical positions; comparing a region of the layer extending vertically between a first set of the plurality of routes and extending horizontally between a second set of the plurality of the routes with one or more threshold values, the region being adjacent to the first via and being separated from the plurality of routes; and inserting a second via based on the comparison.

Abstract: A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.

Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design logic configured to analyze a design of an integrated circuit to identify open tracks on each layer by determining a location of structures in each layer of the design. The open tracks are spaces on each layer of the design that are free from structures that obstruct routing the plurality of pillar metals. The system also includes routing logic configured to successively route the plurality of pillar metals in each of the layers of the design based, at least in part, on the parameters and the location of the structures. The routing logic routes pillars of the plurality of pillar metals that are in adjacent layers to be perpendicular and pillar metals that are within a same layer of the design to be parallel.

Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.

Abstract: Example implementations described herein are directed to a floor plan for a Network on Chip (NoC) topology that can include a plurality of on chip blocks of substantially non-uniform shapes and dimensions. An interconnection network is synthesized along with a plan for a physical layout of the interconnection network based on physical dimensions of the plurality of on chip blocks, the physical dimensions of the floorplan and relative placement information for placing the plurality of on chip blocks on the floorplan. Porosity information for the plurality of on chip blocks on the floorplan and required chip functionality may also be taken into consideration.

Abstract: Example implementations described herein are directed to a system on chip (SoC) that can include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality of routers, and a plurality of links between routers. The plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip (NoC) architecture with a sparse mesh topology. The sparse mesh topology involves a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed. The plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.

Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Abstract: Embodiments of the disclosure relate to methods for facilitating the design of a clock grid in an integrated circuit. The method includes propagating a chip level virtual grid across a multi-level hierarchy of the integrated circuit and customizing the grid at each macro to create a customized virtual grid for each macro. The method further includes propagating the customized virtual grid for each of the plurality of macros to one of a plurality of units and customizing the chip level virtual grid at each of the plurality of units to create the customized virtual grid for each of the plurality of units. The method also includes propagating the customized virtual grid for each of the plurality of units to the chip level and combining the plurality of customized virtual grids to form the clock grid for the integrated circuit.

Abstract: Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes determining fanout of a driving component in a representation of an integrated circuit (IC) being designed, determining for the driving component, the loads in the representation of the IC driven by the driving component, and determining use of existing wiring resources used to connect the loads to the driving component. The method further includes optimizing, based on the use of existing wiring resources, the fanout of the driving component, and the loads being driven by the driving component, a design of the IC.

Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree.

Abstract: A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.

Abstract: A computer implemented method for routing a net includes generating, using one or more computer systems, a first wire associated with the net in accordance with data associated with the net including a multitude of pins and partitioning, using the one or more computer systems, the multitude of pins into at least a first group of pins in accordance with a first cost function. The method further includes connecting, using the one or more computer systems, a second wire associated with the first group of pins to the first wire, and connecting, using the one or more computer systems, a third wire from a pin of the first group of pins to the second wire.

Abstract: Disclosed are a method, apparatus, and program product for routing an electronic design using double patterning that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patterning, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.

Abstract: The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re-assigned and new data routings established.

Abstract: A method of implementing timing ECO in a circuit includes the steps of performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit, decomposing the timing violating path into at least one violating path segment, determining a smooth curve from each timing violating path and determining a plurality of reference points along the smooth curve, computing a fixability parameter of each gate on the violating path segment, extracting at least one gate according to the fixability parameters, and selecting one spare cell and disposing the selected spare cell on the violating path segment.

Abstract: A variable Z0 impedance method (“Variable Z0”) for designing and/or optimizing antenna systems. The method provides that the value of an antenna's feed system characteristic impedance or apparatus internal impedance (Z0) changes as a true variable quantity during the antenna system design or optimization methodology. The value is allowed to be determined by the methodology, because different values of Z0 result in different antenna system performance. It is applied to any set of performance objectives on any antenna system wherein apparatus internal or transmission line characteristic impedance is an explicit or implicit parameter. Variable Z0 is applied to any design or optimization methodology. Structures include Yagi-Uda arrays, Meander Monopoles, and transmission line Multi-Stub Matching Networks, and can incorporate Central Force Optimization or Biogeography Based Optimization or other optimization algorithms.

Abstract: A computer-readable recording medium having stored therein a program for causing a computer to execute a circuit design process includes: calculating a maximum number of wirings arrangeable in an adjacent region of a part on a board based on a design rule; and drawing the wirings of the maximum number in the adjacent region of the part on the board.

Abstract: A netlist for an integrated circuit design is constrained by virtual or “soft” pins to control or stabilize the placement of logic such as an architectural logic path. One soft pin is inserted at a fixed location proximate an input net of the path and is interconnected with the input net, and another is inserted at a fixed location proximate the output net and is interconnected with the output net. Cell placement is then optimized while maintaining the virtual pins at their fixed locations. More than two virtual pins may be inserted to bound a cluster of logic. The virtual pins may lie along the input/output nets. Pseudo-net weights are assigned to pseudo-nets formed between a cell and the virtual pins, and the pseudo-net weight can be increased for each placement iteration.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.

Abstract: The disclosed method includes: identifying a first reference component from among first components defined in a first constraint condition that is a reference designated from among constraint conditions regarding a position relationship between plural components on a printed circuit board; identifying a second reference component from among second components defined in a second constraint condition that is to be compared with the first constraint condition and included in the constraint conditions; and identifying a fourth component that is a component other than the second reference component among the second components and has a correspondence with a third component, based on position relationships with the third component and an attribute of the third component, wherein the third component is a component other than the first reference component among the first components.

Abstract: Methods and apparatus for routing signal paths in an integrated circuit. One or more signal routing paths for transferring signals of the integrated circuit may be determined. A dummy fill pattern for the integrated circuit may be determined based on the one or more metal density specifications and at least one design rule for reducing cross coupling capacitance between the dummy fill pattern and the routing paths. The signal routing paths and/or the dummy fill pattern may be incrementally optimized to meet one or more timing requirements of the integrated circuit.

Abstract: The present disclosure provides a system, apparatus and method to transport data across a network node, as part of a network infrastructure of an optical transmission system. According to the various embodiments of the disclosure, a base architecture is provided which includes interconnectivity providing high throughput, while mitigating factors which may lead to signal loss or signal degradation. The base architecture is easily expandable to accommodate additional traffic.

Abstract: In a generation method, the computer detects a contact between a pin data group of a first connection destination included in three-dimensional shape data and a pin data group of a first connection source included in three-dimensional shape data of a connector, and determines first contact information that indicates combinations of pin data items of the pin data group of the first connection destination and respective pin data items of the pin data group of the first connection source. Furthermore, the computer detects a contact between a pin data group of a second connection destination and a pin data group of a second connection source, and determines second contact information that indicates combinations of pin data items of the pin data group of the second connection destination and respective pin data items of the pin data group of the second connection source, and generates a connection relationship data group.

Abstract: A design support apparatus acquires position information for a signal wire that is to be disposed in wiring layer stacked on an insulation layer. Subsequently, the design support apparatus acquires position information for an area obtained by projecting, in a direction for glass fiber bundles to be stacked on one another, the glass fiber bundles in an insulation layer actually used. The design support apparatus converts the position information for the signal wire that is to be disposed into position information for a position in the area of the glass fiber bundles such that the signal wire is included in the area of the glass fiber bundles in the insulation layer actually used. The design support apparatus outputs the converted position information.

Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.

Abstract: Systems and methods are disclosed for testing dies in a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.

Abstract: A technique for routing signal wires in an integrated circuit design includes applying a first rule that attempts to route a signal wire along existing power supply shapes of the integrated circuit design and applying a second rule that provides shield wires along segments of the signal wire that are not routed along one of the existing power supply shapes. The technique also includes routing the signal wire between a first endpoint and a second endpoint while applying the first and second rules to substantially minimize a route cost for the signal wire between the first and second endpoints.

Abstract: Methods for designing and manufacturing an integrated circuit are disclosed, in which the physical design process for a standard cell or cells utilizes a preferred diagonal direction for minimum-width patterns on at least one layer, where the standard cell or cells are used in the layout of an integrated circuit. The methods also include forming the patterns on a photomask using model-based fracturing techniques with charged particle beam simulation, and forming the patterns on a substrate such a silicon wafer using the photomask and an optical lithographic process with directional illumination which is optimized for the preferred diagonal direction.

Abstract: A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.

Abstract: A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.