Abstract: A logically hierarchical netlist may be split along physical partition boundaries while retaining information on the logical hierarchy. Nets can be driven to higher levels of hierarchy in order to maintain connectivity and enable the original logical function. A mapping of nets can be created. During the design process merging of physical partitions may result in a new logically hierarchical netlist which retains the hierarchy of the original logically hierarchical netlist. The lowest common hierarchical ancestor (LCA) is identified and then the appropriate cells and nets are included during the merging process.

Abstract: In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.

Abstract: A design support apparatus acquires position information for a signal wire that is to be disposed in wiring layer stacked on an insulation layer. Subsequently, the design support apparatus acquires position information for an area obtained by projecting, in a direction for glass fiber bundles to be stacked on one another, the glass fiber bundles in an insulation layer actually used. The design support apparatus converts the position information for the signal wire that is to be disposed into position information for a position in the area of the glass fiber bundles such that the signal wire is included in the area of the glass fiber bundles in the insulation layer actually used. The design support apparatus outputs the converted position information.

Abstract: According to some embodiments, a plurality of interconnected entities may be discovered in a network landscape. A subset of the entities may then be automatically consolidated into a business participant, the consolidating may performed in accordance with at least one rule based algorithm. A business process landscape, including the business participant, may then be generated and/or displayed to an operator.

Abstract: A computer-readable recording medium stores a program that causes a computer to execute a circuit design process. The process includes selecting component data in first board data from among the first board data including first connector component data and second board data including second connector component data that is associated with the first connector component data; setting a connection destination net name of the selected component data to a first vacant terminal of the first connector component data; and setting the connection destination net name of the component data to a second vacant terminal of the second connector component data that corresponds to the first vacant terminal of the first connector data when the component data is moved from the first board data to the second board data.

Abstract: An approach for providing conversion of a planar design to a FinFET design is disclosed. Embodiments include: receiving a planar design having a plurality of diffusion regions; overlapping a plurality of parallel fin mandrels with a plurality of evenly-spaced parallel lines of a grid; snapping the diffusion regions to the grid based on the parallel lines; and generating a FinFET design based on the overlapping and the snapping. Embodiments include the parallel lines and the parallel fin mandrels being perpendicular to a poly orientation associated with the planar design, and determining a spacing length between the parallel lines; determining a plurality of edges of the diffusion regions that are parallel to the poly orientation; and cropping the diffusion regions until each of the edges has a length that is a multiple of the spacing length.

Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: Some embodiments of the present invention provide systems for generating and using a route fix guidance for fixing design rule violations. A route fix guidance includes information that enables a router to locally modify a routing solution to fix one or more design rule violations. A route fix guidance can include a set of two or more metal avoidance areas, wherein avoiding any one of the set of two or more metal avoidance areas during routing fixes the design rule violation. Additionally, a route fix guidance can specify a set of rectangles to remove from a routing solution, and a set of rectangles to insert into or add to a routing solution. Further, the route fix guidance can include information for moving one or more vias to new locations in the routing solution. The route fix guidance can specify a sequence in which the local modifications are to be made.

Abstract: In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.

Abstract: Approaches for placement and routing of a circuit design are disclosed. Two or more modules of a circuit design are assigned to respective regions of a programmable integrated circuit. Placement and routing constraints are created for non-global resources of two or more modules of the circuit design. The placement and routing constraints restrict placement and routing of non-global resources of each of the two or more modules to respective regions of a programmable IC. Each non-global resource is used by at most one of the two or more modules. The two or more modules are placed. In response to the one of the placed circuit elements not being placed within the assigned region, the routing constraint on the one of the circuit elements is removed. The circuit design is routed.

Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.

Abstract: A method for implementing electronic circuit modules on elongated structures of semiconducting materials such as carbon nanotubes, graphene nanoribbons, elongated structures of semiconducting polymers or organic semiconductors, other related materials, and printed electronics strip structures is disclosed. The method provides that a plurality of modules can be implemented on distinct adjacent portions of the same elongated structure of semiconducting materials. In powering the modules, each circuit comprises a chain of electronic components arranged so that each end of the chain can function as a power supply terminal. Larger electronic circuit modules can be created from smaller module, and such a modular hierarchy may be extended to an arbitrary number of levels. In a Computer Aided Design (CAD) applications for nanoelectronics and printed electronics, designs for hierarchies electronic circuit modules can be stored and retrieved from one or more a libraries of circuit designs.

Abstract: The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re-assigned and new data routings established.

Abstract: A method and system for auto-routing wiring within a PCB. In some embodiment, a first broad region within a first layer and a counterpart first broad region within a second layer are defined. The counterpart regions define a first broad via location. In some embodiments, the first and second broad via locations of the first and second layers can then be subdivided into a plurality of triangular regions. The triangular regions on the first and second layers can then be compared to more accurately locate an appropriate via location.

Abstract: A method includes connecting in a wiring area a plurality of basic block patterns which include a plurality of track patterns extending to one direction and being disposed at a prescribed pitch in an intersection direction intersecting the one direction to generate a plurality of parallel wiring patterns, each of which includes the track patterns connected together; generating a wiring route running on a track pattern; cutting away a track pattern terminal end, on which no wiring route runs, out of track pattern terminal ends of a track pattern including a route end of the wiring route and an adjacent track pattern connected to a track pattern start end of the track pattern concerned; and generating a wiring pattern data including a block pattern identifier corresponding to a basic block pattern out of the basic block patterns in the wiring area and a layout position of the basic block pattern.

Abstract: One embodiment of the present invention provides a system that concurrently optimizes multiple routing objectives during routing of an integrated circuit (IC) chip design. During operation, the system starts by receiving a routing solution for the IC chip design and a set of routing objectives. The system then partitions the IC chip design into a set of partitions. Next, for each partition in the set of partitions, the system optimizes the routing solution by, iteratively: (1) analyzing the routing solution to determine weights for the set of routing objectives; (2) constructing a cost function based on the weights for the set of routing objectives; and (3) modifying the routing solution within the partition to attempt to optimize the cost function.

Abstract: A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.

Abstract: A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.

Abstract: An automated system, and method of operating the same, for editing the floorplan, placement, and toplevel wiring routing in a layout of an integrated circuit. Components in the layout of the integrated circuit, such components including functional blocks or subchips, and also wire segments of the toplevel wiring, are associated with horizontal reference frames and vertical reference frames. Each reference frame has its position, in the orthogonal direction, specified by a position of a reference line. The positions of subchips and wire segments within the reference frame are expressed as offsets from the reference line. Movement of components is accomplished by moving the reference frame in the orthogonal direction, and updating the reference line position while maintaining the offset values constant.

Abstract: A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.

Abstract: A method is described for routing a semiconductor chip's global nets. The method includes identifying a subset of the global nets and routing the subset of global nets using multiple threads, where, each of the global nets within the subset are routed by one of the threads in isolation of the subset's other global nets. The method further includes identifying a second subset of the global nets and routing the second subset of global nets using the multiple threads, where, each of the global nets within the second subset are routed by one of the threads in isolation of the second subset's other global nets but in respect of the routes of first subset of global nets.

Abstract: Methods and apparatuses for designing at least one integrated circuit (IC). In one embodiment, the method comprises partitioning a circuit into portions that represent a partitioning solution and assigning traces to interconnect the portions to generate a trace assignment solution. The method further comprises optimizing the circuit through a modification of at least one of the partitioning solution and the trace assignment solution, the optimizing based on evaluating a design parameter which is based at least in part on the trace assignment solution.

Abstract: An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.

Abstract: Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.

Abstract: A method, system and computer program product are provided for implementing enhanced net routing with improved correlation of pre-buffered and post-buffered routes on a hierarchical design of an integrated circuit chip. In initial wiring steps the nets are routed, and then buffers are add along the net route based upon predetermined electrical parameters. Responsive to adding the buffers, distance based constraints are added to the nets. Then the nets that have been modified are rerouted.

Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.

Abstract: A method, system, and computer program product for improved routing using layer ranges in the design of an integrated circuit (IC) are provided in the illustrative embodiments. Using an application executing in a data processing system, a score is computed for a net in a set of nets routed using a set of layers in the design. The set of nets is sorted according to scores associated with nets in the set of nets. A layer range from a set of layer ranges is assigned to a net in the sorted list such that a net with a higher than threshold score is assigned a high layer range.

Abstract: A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.

Abstract: An electronic circuit and method for designing an electronic circuit is provided that includes a first source element, a second source element, a first matching network, and a second matching network. The first matching network and the second matching network are designed by means of a method using the Poincaré distance, in which the second source element is designed to output a signal with a center frequency, in which the load has a load impedance, in which the second matching network has line-like series elements that carry the signal. The line-like series elements only have line impedances less than the load impedance or a sum of the electrical lengths of the line-like series elements, each of which has a line impedance greater than the load impedance, is less than one quarter of a wavelength associated with the signal.

Abstract: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow channels, the technique automatically places route paths to connect pins of cells in the solid channels, where route paths may be placed within the solid channels or hollow channels. The technique can reduce a width of at least one hollow channel when an entire space of the hollow channel is not occupied by a placed route path.

Abstract: The present invention provides a routing storage structure based on directional grid points and a routing method thereof. The routing storage structure includes a grid matrix having N×M grid points for storing a grid identifier corresponding to each grid point, where both N and M are natural numbers; a grid value acquisition module for acquiring the grid identifier corresponding to the current grid point from the grid matrix during a routing operation; and a grid value setting module for setting the grid points contained by the blocks in the routing plane and/or the grid points that the routing passes through as corresponding grid identifiers in accordance with a predetermined setting rule.

Abstract: A method of generating net routing constraints for nets of an IC design includes generating a file with hashes organized by nets. Each hash has attributes of a net, e.g. net name, length, fanout, total actual route (AR) resistance, a corresponding virtual route (VR) resistance, and a number of vias. A wire only AR resistance for each net can be calculated. Wire scaling factors can be calculated using the wire only AR resistances and their corresponding VR resistances. Wire scaling factors can be binned by one or more net characteristics. An average wire scaling factor can be calculated for each bin. Code used by a place and route tool can then be generated, wherein the code applies the average wire scaling factors to nets of the design to improve pre-route and post-route correlation.

Abstract: A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer.

Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

Abstract: Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.

Abstract: A method for the creation of rectilinear Steiner minimum trees includes determining a set of candidate connections from a terminal node to a different terminal node or to a graph edge. The length of each candidate connection may be used to determine the set of candidate connections that span the graph with a minimum total length.

Abstract: Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

Abstract: Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

Abstract: A method of increasing an initial threshold voltage (Vt) of selected devices. The method includes designing devices with desired antenna effects and adjusting an increase in Vt of some devices to specific values. The desired antenna effects produce a desired threshold voltage of the devices.

Abstract: The connection architecture of a network on a chip (NoC) is described in which (a) nodes in octahedron sections are connected in an arc Benes network, (b) a hierarchy of node clusters are connected using a globally asynchronous locally asynchronous (GALA) configuration, (c) a double wishbone 2D torus ring is applied to connection between network layers and (d) data is routed using buffer modulation.

Abstract: In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.

Abstract: A layout method of a semiconductor integrated circuit includes five steps. The first step is of extracting a wiring crowding place where wiring lines are crowded as compared with a predetermined condition, after carrying out a routing in a region where a placement of circuit elements is carried out. The second step is of generating routing prohibition regions where a routing is prohibited in an area including the wiring crowding place. The third step is of carrying out a routing by bypassing the routing prohibition regions. The fourth step is of deleting the routing prohibition regions. The fifth step is of carrying out a re-routing. The generating step includes: calculating a size and an interval of the routing prohibition regions based on a rate for generating a routing prohibition region in the area in each wiring layer, and generating the routing prohibition regions in the area on the basis of the calculating result.

Abstract: A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.

Abstract: A method for designing an optimal wiring topology for electromigration avoidance is disclosed. The wiring topology includes multiple sources, multiple sinks and multiple wires. The method includes the following steps: A feasible wire, a wire of the shortest length connecting each pair of source and sink, is calculated, and the capacity of each feasible wire is decided. An initial feasible topology is found. A flow network is created based on the initial topology. Negative cycles are iteratively checked and removed until no more negative cycles.

Abstract: A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Abstract: In one example, an integrated circuit includes memory control logic (e.g., CMOS logic circuit) and passive variable resistance memory disposed above the memory control logic. The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of the passive variable resistance memory is electrically connected to the memory control logic through at least one vertical interconnect accesses (vias). For example, the operation (e.g., write/read) of each passive variable resistance memory cell is controlled by the memory control logic. The integrated circuit may also include processor logic operatively coupled to the memory control logic.

Abstract: Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.

Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.