Abstract: This invention discloses a photomask manufacturing method. A pattern dimensional map is generated by preparing a photomask in which a mask pattern is formed on a transparent substrate, and measuring a mask in-plane distribution of the pattern dimensions. A transmittance correction coefficient map is generated by dividing a pattern formation region into a plurality of subregions, and determining a transmittance correction coefficient for each of the plurality of subregions. The transmittance correction value of each subregion is calculated on the basis of the pattern dimensional map and the transmittance correction coefficient map. The transmittance of the transparent substrate corresponding to each subregion is changed on the basis of the transmittance correction value.

Abstract: Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation of a set of partial intensity functions independent of (var,zt) using a mask transmittance function, a plurality of illumination system modes, and a plurality of preselected basis spatial functions independent of (var,zt). Subsequently, for each of many different (var,zt) combinations, expansion coefficients are computed for which the preselected basis spatial functions, when weighted by those expansion coefficients, characterize a point response of a projection-processing system determined for that (var, zt) combination. The resultant intensity for that (var,zt) combination is then computed as a sum of the partial intensity functions weighted according to corresponding products of those expansion coefficients.

Abstract: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.

Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

Abstract: At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at least one surrogate metric is modeled using a general joint probability density function. A chip disposition criterion is determined based on the general joint probability density function. The chip disposition criterion determines, for a given physical chip putatively manufactured in accordance with the design, based on the at least one surrogate metric for the given physical chip, whether the given physical chip is to be accepted or discarded during the manufacturing chip testing.

Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).

Abstract: A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

Abstract: Disclosed are embodiments of a method, system and computer program for optimizing system yield based on the results of post-manufacture integrated circuit (IC) chip performance path testing. In these embodiments, a correlation is made between IC chip performance measurements, which were acquired from IC chips specifically during post-manufacture (i.e., wafer-level or module-level) performance path testing, and system performance measurements, which were acquired from systems that incorporate those IC chips previously subjected to performance path testing. Based on this correlation and a target system performance value, a post-manufacture (i.e., wafer-level or module-level) chip dispositioning rule can be adjusted to optimize system yield (i.e., to ensure that subsequently manufactured systems which incorporate the IC chip meet the target system performance value).

Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the mask, for determining a manufacturing penalty in making the mask. The manufacturability of the mask, including the manufacturing penalty in making the mask, is determined based on the target edge pairs as selected, and is dependent on the manufacturing penalty in making the mask. Determining the manufacturability of the mask includes, for a selected edge pair having first and second edges that are at least substantially parallel to one another, determining a manufacturing shape penalty owing to an aspect ratio of the first edge relative to a size of a gap between the first edge and the second edge. This penalty takes into account a pair of connected edges of the first edge that are at least substantially parallel to the first edge.

Abstract: Aspects of the invention relate to techniques for determining edge fragment correlation information. With various implementations of the invention, image intensity slope information for edge fragments in a layout design is determined. The image intensity slope information comprises information describing how image intensity for each of the edge fragments changes with its position. Image amplitude sensitivity information for the edge fragments is also determined. The image amplitude sensitivity information comprises information describing how image amplitude for each of the edge fragments changes with positions of neighboring edge fragments. Based on the image intensity slope information and the image amplitude sensitivity information, edge fragment correlation information for the edge fragments is determined. Using the edge fragment correlation information, the layout design may be processed by using, for example, OPC techniques.

Abstract: A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows.

Abstract: A method of forming a photomask using a calibration pattern that may exactly transfer a desired pattern to a substrate. The method includes providing one-dimensional calibration design patterns each having first design measures and providing two-dimensional calibration design patterns each having second design measures; obtaining one-dimensional calibration measured patterns using the one-dimensional calibration design patterns and obtaining two-dimensional calibration measured patterns using the two-dimensional calibration design patterns; obtaining first measured measures of the one-dimensional calibration measured patterns and obtaining second measured measures of the two-dimensional calibration measured patterns; establishing a correlation between the first measured measures and the second measured measures; and converting a main measured measure of a main pattern into a corresponding one of the first measured measures using the correlation.

Abstract: A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a “unified” results database/directory (e.g., unified at least from a user's perspective), where results from various verification processes, such as Design-Rule-Check (DRC) processes, Layout-Versus-Schematic comparison (LVS) processes, Design-For-Manufacturing (DFM) processes Optical Proximity Correction (OPC) processes, and Optical Rule Check (ORC) processes are accessible from the same style of user interface, which may be a graphical user interface. The basic abilities for design team-based interactions can be equally available to each process involved in the physical verification of an integrated circuit design.

Abstract: Techniques for forming a first electronic circuit including a plurality of instances of a repeatable circuit element include the steps of: obtaining a total number of instances of the repeatable circuit element in a design of an IC including the first electronic circuit and at least a second electronic circuit; and configuring at least one functional parameter of the first electronic circuit as a function of the total number of instances of the repeatable circuit element in the IC to thereby satisfy a prescribed minimum composite manufacturing yield of the IC and/or at least one specification of the IC under prescribed operating conditions.

Abstract: A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+?d to d??d wherein d is the standard spacing and ?d<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.

Abstract: Disclosed are methods, systems, and articles of manufacture for processing a electronic design, which use a computer system to identify an operation associated with a task to be performed on the electronic design, to generate a hierarchical output for multiple shapes for performing the task based at least in part on performing an operation associated with the task, and to display or to store the hierarchical output. The task comprises a dummy fill insertion task or a design verification task in some embodiments. The methods or the systems may further determine or identify an inverse transform and apply the inverse transform to a shape before adding the shape to the hierarchical output. In some embodiments, there exists no duplication among the shapes in the hierarchical output, or only shapes derived from original shapes that belong to the first instance of a cellview master are added to the hierarchical output.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included.

Abstract: A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape based on the amount and the direction of retargeting.

Abstract: Techniques and systems for converting a non-bandlimited pattern layout into a band-limited pattern image are described. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.

Abstract: Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation of a set of partial intensity functions independent of (var,zt) using a mask transmittance function, a plurality of illumination system modes, and a plurality of preselected basis spatial functions independent of (var,zt). Subsequently, for each of many different (var,zt) combinations, expansion coefficients are computed for which the preselected basis spatial functions, when weighted by those expansion coefficients, characterize a point response of a projection-processing system determined for that (var, zt) combination. The resultant intensity for that (var,zt) combination is then computed as a sum of the partial intensity functions weighted according to corresponding products of those expansion coefficients.

Abstract: At least one pattern of a photomask is identified that has a likelihood of causing collapse of a microelectronic device feature that is formed using the photomask, due to surface tension of a solution that is applied to the feature during manufacture of the microelectronic device. The patterns of the photomask are then modified to reduce the likelihood of the collapse. The photomask may be formed and the photomask may be used to manufacture microelectronic devices. Related methods, systems, devices and computer program products are described.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A method for proactively preventing lithographic problems is disclosed, which employs information generated from layout patterns including hot spots in a first technology node to identify hot spots in a second technology node employing a scaled down minimum dimension. In this proactive approach, problematic patterns or complex product geometries are identified in a chip design layout of the second technology node based on detection, in the chip design layout, of topological features that are similar to topological features of known hot spots in the first technology node. The identified patterns are potential hot spots in the chip design layout for the second technology node. Known hot spots in layout patterns in the first technology node are topologically categorized to provide a database for performing the fault detection and diagnosis on the chip design layout.

Abstract: A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

Abstract: A method, system, and computer usable program product for fracturing a continuous mask usable in photolithography are provided in the illustrative embodiments. A first origin point is selected from a set of points on an edge in the continuous mask. A first end point is identified on the edge such that a separation metric between the first origin point and the first end point is at least equal to a threshold value. Several alternatives are determined for fracturing using the first origin point and the first end point. A cost associated with each of the several alternatives is computed and one of the alternatives is selected as a preferred fracturing. Several pairs of origin points and end points are formed from the set of points. Each pair has a cost of a preferred fracturing between the pair. The continuous mask is fractured using a subset of the several pairs.

Abstract: The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time.

Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.

Abstract: According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.

Abstract: A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.

Abstract: An integrated circuit design and fabrication method includes the following steps. Firstly, an integrated circuit design layout is provided. Then, a first hotspot group and a second hotpot group are searched from the integrated circuit design layout. Then, a hotspot score is acquired according to the first hotspot group, the second hotpot group and a product functionality. If the hotspot score is higher than a criterion, the integrated circuit design layout is corrected according to the first hotspot group and the second hotpot group.

Abstract: Provided is an etch proximity correction method in which an accurate etch bias value is calculated. The etch proximity correction method includes creating an etch bias value from a project area corresponding to an area blocked by a pattern region within a linear distance projected from a target position selected in a target layout to an outermost portion of the proximity region and a non-project area corresponding to an area projected into an edge linear distance from an edge of the pattern region blocked in the linear distance to the outermost portion of the proximity region and correcting the target position in the layout using the etch bias value. Since an etch bias model includes the project area and the non-project area, the accurate etch bias value may be calculated.

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract: A method includes: generating electron beam exposure data, used for electron beam exposure, from design data of a semiconductor device; extracting differential information indicating a difference in shape between an electron beam exposure pattern formed on a substrate through electron beam exposure on the basis of the electron beam exposure data and a photoexposure pattern formed on the substrate through photoexposure on the basis of the design data of the semiconductor device; determining whether the size of the difference in shape between the electron beam exposure pattern and the photoexposure pattern falls within a predetermined reference value; acquiring shape changed exposure data by changing the shape of the pattern of the electron beam exposure data in accordance with the differential information and updating the electron beam exposure data; and repeating the differential extraction, the determination and the updating when the size of the difference falls outside the predetermined reference value.

Abstract: A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within an allowable range. The design aiding program causes a computer to execute a process of determining the worst-case corner candidates that minimize the number of the worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners.

Abstract: A method and structure for a computer model of a device has a performance parameter. The performance parameter includes a first bounded range and a second bounded range. The first bounded range has performance parameter variations within a single manufacturing process, and the second bounded range has performance parameter variations of different device designs.

Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed.

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract: The present invention applies the data mining methodology by which the wafer exposure effectiveness and efficiency are predictable in terms of the chip size, chip length and chip width. More specifically, in the present invention, an index, named “Mask-field-utilization weighted Overall Wafer Effectiveness” (MOWE), integrates the two parameters of “Overall Wafer Effectiveness” (OWE) and “Mask-Field-Utilization” (MFU), mainly regarding the wafer exposure effectiveness and efficiency respectively, in order to construct a model tree of the MOWE to achieve the data mining. By the MOWE model tree, the causal relationship between design independent variables and fabrication dependent variables is constructed, which can be accordingly applied as design guidelines in the design phase to improve the chip layout in order to produce a better wafer exposure effectiveness and efficiency.

Abstract: Aspects of the invention relate to machine-learning-based hotspot detection techniques. These hotspot detection techniques employ machine learning models constructed using two feature encoding schemes. When two-level machine learning methods are also employed, a total four machine learning models are constructed: scheme-one level-one, scheme-one level-two, scheme-two level-one and scheme-two level-two. The four models are applied to test patterns to derive scheme-one hotspot information and scheme-two hotspot information, which are then used to determine final hotspot information.

Abstract: An overlapping margin of a second pattern for a first pattern is corrected for at least one of the first pattern and the second pattern (S50). Next, a relative distance between the first pattern and the second pattern after the overlapping margin is corrected is calculated (S60). Next, it is determined whether or not the relative distance satisfies a criterion (S70). Thus, the pattern can be verified under the consideration of the overlapping margin.

Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield/lifetime domain, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Abstract: The simulation information creating part 111 generates random numbers corresponding to the correlation coefficient data between the simulation model parameters, and also creates the simulation model library having correlated model parameters with variations, and the simulation net list for the objective characteristic, by Monte Carlo method using the typical simulation model library, the standard deviations for the plural simulation model parameters and the simulation net list for the typical objective characteristic. The simulation part 112 obtains samples having the objective characteristics with variations. The yield estimation part 120, estimates the yields by determining whether the samples satisfy the predetermined specification or not (Pass or Fail), wherein by repeating the determination by making the simulations again only for the samples on which the filter having the function of learning the boundary for decision of Pass or Fail did not determine as Pass.

Abstract: In a simulation step of simulating a surface configuration of a substrate which is used for a mask blank and which is set to an exposure apparatus, height information from a reference plane is derived from a plurality of measurement points on a main surface of the substrate. From the height information, a curved surface of fourth, fifth, or sixth order is approximated which is represented by a polynomial specified by a plurality of terms and coefficients of the terms. The coefficients are stored as coefficient information in association with the substrate.

Abstract: The Hessian (second derivative) of the image log slope (ILS) can be quickly and accurately calculated without the need to use approximate methods from the gradient of the ILS with respect to mask transmission and source intensity. The Hessian has been traditionally calculated using a finite-difference approach. Calculating the Hessian through a finite-difference approach is slow and is an approximate method. The gradient of the ILS improves the speed of calculation of the Hessian, and thus accelerated SMO operation is realized. The results of ILS evaluation can be used in design for manufacturing (DFM) to suggest changes in the design rules to improve imaging. For a fixed illumination, this information can help remove forbidden pitches and help select design rules for 1-D and 2-D patterns on a mask design layout.

Abstract: A method for the reproducible determination of the positions of structures (3) on a mask (2) is disclosed. A pellicle frame (30) is firmly attached to the mask (2). A theoretical model of the bending of the mask (2) with the firmly attached pellicle frame (30) is calculated, wherein material properties of the mask (2), of the pellicle frame (30), and of the attaching means between the pellicle frame (30) and the mask (2) are taken into account in the calculation of the bending of the mask (2). For the calculation of the bending of the mask (2) its contact with three support points is considered. The positions of the structures (3) on the mask (2) are measured with a metrology tool (1). The measured positions of each structure are corrected with the theoretical model of the bending of the mask at the position of the respectively measured structure.

Abstract: Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed layout are matched, After edge differences between the designed layout and the wafer patterns image contour are extracted, a checking layout for detecting wafer pattern defects is obtain by adding the edge differences on the designed layout. Defects on the checking layout is identified to verify the patterns in view of processes before fabrication of a photomask.