Abstract: Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution assist feature. A merge bar width of a merge bar is established. A distance between the first sub-resolution assist feature and the second sub-resolution assist feature is determined. A merging technique is determined in accordance with the distance and the merge bar width. The first sub-resolution assist feature and the second sub-resolution assist feature are merged according to the identified merging technique.

Abstract: A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract: One inventive aspect relates to a method of determining an estimate of system-level yield loss for an electronic system comprising individual components subject to manufacturing process variability leading to manufacturing defects. The method comprises obtaining a description of the composition of the electronic system in terms of which individual components are used. The method further comprises obtaining statistical properties of the performance of individual components of the electronic system with respect to first and second performance variables, e.g. energy consumption and delay, the statistical properties including correlation information of the first and second performance variables. The method further comprises obtaining information about execution of an application on the system, e.g. a number of accesses of a component by an application.

Abstract: A method of predicting a substrate current in a high voltage device that may accurately predict substrate current components in each of a first region, a second region, and a third region. This may be accomplished by modeling a substrate current component in a third region, in which an inconsistency may occur when a substrate current in a high voltage device is calculated, for example using BSIM3-based modeling. According to embodiments, a substrate current for a third region may be modeled by an expression with a ternary operator, and the modeled substrate current may be added to a substrate current obtained through BSIM3-based modeling.

Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask, for determining a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has a number of edges. Each target edge pair is defined by two of the edges of one or more of the polygons. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined. Determining the manufacturing penalty is based on the target edge pairs as selected. Determining the manufacturability of the lithographic mask uses continuous derivatives characterizing the manufacturability of the lithographic mask on a continuous scale. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.

Abstract: Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.

Abstract: Provided is a method to design an integrated circuit. The method reduces a time delay between introduction of a new lithography process and a start of production. A first semiconductor mask is designed at a first process feature size. The first process feature size can be based on an anticipated process feature size of the new lithography process. A second semiconductor mask is created by enlarging the first semiconductor mask to a second process feature size for which production is available. Thus, the second process feature size is larger than the first process feature size. An integrated circuit (IC) is fabricated with the second semiconductor mask. After the new semiconductor process has been developed and is available for production, another IC is fabricated with the first semiconductor mask.

Abstract: Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer.

Abstract: A circuit structure of an integrated circuit is provided. The circuit structure is adapted for a circuit layout of a wafer. The circuit structure at least includes a first array cell and a second array cell. The second array cell and the first array cell are connected to each other and have a connecting area, wherein the second array cell is shifted a distance along the connecting area. Therefore, the result of yield enhancement is achieved.

Abstract: An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

Abstract: A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material together occupy a second space having a second boundary. The first space and the second space are different. The stress model performed by the computer system transforms the representation of the material conversion of the first material to the second material into: i) the first material occupying the first space having the first boundary, and ii) a strain displacement condition of the first material. The strain displacement condition is determined by a spatial change from the first boundary to the second boundary.

Abstract: First and second evaluation substrates are prepared, a direction perpendicular to a surface of the first evaluation substrate being defined by first indices, and the direction defined by the first indices being inclined from a normal direction of a surface of the second evaluation substrate. Ion implantation is performed for the first evaluation substrate in a vertical direction. Ion implantation is performed for the second evaluation substrate by using an ion beam parallel to the direction defined by the first indices. Impurity concentration distributions in a depth direction of the first and second evaluation substrates are measured. A first impurity concentration distribution on an extension line of an ion beam and a second impurity concentration distribution in a direction perpendicular to the extension line are predicted from the measured impurity concentration distributions of the first and second evaluation substrates.

Abstract: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation of a set of partial intensity functions independent of (var,zt) using a mask transmittance function, a plurality of illumination system modes, and a plurality of preselected basis spatial functions independent of (var,zt). Subsequently, for each of many different (var,zt) combinations, expansion coefficients are computed for which the preselected basis spatial functions, when weighted by those expansion coefficients, characterize a point response of a projection-processing system determined for that (var, zt) combination. The resultant intensity for that (var,zt) combination is then computed as a sum of the partial intensity functions weighted according to corresponding products of those expansion coefficients.

Abstract: A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest

Abstract: In one embodiment, a method for predicting yield includes calculating a criticality factor (CF) for each of a plurality of defects detected in an inspection process step of a wafer, and determining a yield-loss contribution of the inspection process step to the final yield based on CFs of the plurality of defects and the yield model built for a relevant design. The yield-loss contribution of the inspection process step is then used to predict the final yield for the wafer.

Abstract: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.

Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

Abstract: Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation of a set of partial intensity functions independent of (var,zt) using a mask transmittance function, a plurality of illumination system modes, and a plurality of preselected basis spatial functions independent of (var,zt). Subsequently, for each of many different (var,zt) combinations, expansion coefficients are computed for which the preselected basis spatial functions, when weighted by those expansion coefficients, characterize a point response of a projection-processing system determined for that (var, zt) combination. The resultant intensity for that (var,zt) combination is then computed as a sum of the partial intensity functions weighted according to corresponding products of those expansion coefficients.

Abstract: Apparatus, methods, and computer readable code for computing parameters related to layout schemes of integrated circuits are disclosed herein. In some embodiments, an actual layout scheme is computed, for example, for a netlist. In some embodiments, one o or more layout schemes are scored based on, for example, susceptibility to failure and/or yield in manufacturing.

Abstract: A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns.

Abstract: Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of the interconnect to process variations causing variations in the value of a subject fabrication variable, and a revised layout is developed in dependence upon the adjusted value for the adjustment variable. In an embodiment, the adjustment is made in dependence upon a pre-calculated “interconnect optimization database” indicating combinations of values for the plurality of variables which have been pre-determined to minimize exposure of interconnect propagation delay to process variations affecting the subject variable.

Abstract: An optical proximity correction (OPC) based integrated circuit design system and method introduce a variable rule in which rules are specified in terms of multiple correction actions that yield acceptable results. This category of rules provides more degrees of freedom in actual application so that the rule-based OPC tool can intelligently select the proper valid rule that minimizes the OPC complexity or meets other objectives.

Abstract: A method, system, and computer program product are disclosed for generating a pattern signature to represent a pattern in an integrated circuit design. In one approach, the method, system and computer program product transform pattern data, two dimensional data for the pattern, into a set of one dimensional mathematical functions, compress the set of one dimensional mathematical functions into a single variable function, compress the single variable function by calculating a set of values for the single variable function, and generate a pattern signature for the pattern from the set of values.

Abstract: For determining an optimized wafer layout, at least two wafer layouts are specified for a given wafer, each wafer layout defining the location of a plurality of die with regard to the wafer. An optimization parameter value of at least one optimization parameter is determined for each of the at least two wafer layouts. The at least one optimization parameter includes at least one of a number of exposure fields necessary for exposing the respective wafer layout and a number of die of the wafer layout. The optimized wafer layout is selected out of the at least two wafer layouts depending on the optimization parameter values.

Abstract: Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation of a set of partial intensity functions independent of (var,zt) using a mask transmittance function, a plurality of illumination system modes, and a plurality of preselected basis spatial functions independent of (var,zt). Subsequently, for each of many different (var,zt) combinations, expansion coefficients are computed for which the preselected basis spatial functions, when weighted by those expansion coefficients, characterize a point response of a projection-processing system determined for that (var, zt) combination. The resultant intensity for that (var,zt) combination is then computed as a sum of the partial intensity functions weighted according to corresponding products of those expansion coefficients.