Abstract: A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully overlaps a short wire or an end of a long wire. The computer uses at least another rule to change at least one region in the set of regions, to obtain a second layout which is less likely to fail in the identified regions. An example of such a rule of correction is to elongate at least one of the two neighbors. The computer may perform optical rule checking (ORC) in any order relative to application of the rules, e.g. ORC can be performed between detection rules and correction rules i.e. performed individually on each identified region prior to correction.

Abstract: An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.

Abstract: A method optical proximity correction includes the following steps. First, a layout of an integrated circuit with an exposure intensity specification is provided. The integrated circuit includes a plurality of patterns and each pattern has an exposure intensity distribution. Second, a quadratic polynomial equation of each exposure intensity distribution is approximated. Third, a local extreme intensity of each exposure intensity distribution is computed by fitting the quadratic polynomial equation. Fourth, the local extreme intensity is determined whether violating the exposure intensity specification or not. Then, the layout is corrected when the local extreme intensity violates the exposure intensity specification.

Abstract: Method and apparatus for designing an integrated circuit, IC, layout by identifying one or more defects in a feature within the IC layout. Determining if an identified defect is improvable. Calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects.

Abstract: The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent.

Abstract: A method of developing a statistical model for integrated circuits includes providing a set of test patterns; collecting a set of intra-die data from the set of test patterns; collecting a set of inter-die data from the set of test patterns; generating a total variation sigma (sigma_total) from the set of intra-die data and the set of inter-die data; appointing one of a global variation sigma (sigma_global) and a local variation sigma (sigma_local) as a first sigma, and a remaining one as a second sigma; generating the first sigma from one of the set of intra-data and the set of inter-data; generating the second sigma by removing the first sigma from the sigma_total; generating a corner model for global variations based on sigma_global and the set of inter-die data; and generating a corner model for local variations based on sigma_local and the set of intra-die data.

Abstract: In one embodiment, a photomask designing method is disclosed. The method includes dividing design pattern data into predetermined regions and obtaining a pattern perimeter for each of the divided regions. The method includes obtaining the pattern perimeter for an entire region of the design pattern data by repeating the obtaining the pattern perimeter for the each of the divided regions. The method includes obtaining a dimension conversion difference for the entire region of the design pattern data using the pattern perimeter for the entire region of the design pattern data and a correlation obtained in advance between a predicted pattern perimeter and a predicted dimension conversion difference. The method includes performing process proximity correction on the design pattern data using a value of the obtained dimension conversion difference, and creating exposure pattern data from the corrected design pattern data.

Abstract: A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.

Abstract: A method for detecting and reporting changes in functional features of a simulation model caused by a software revision is disclosed. In one aspect, the method is independent of simulation model architecture. One performs regression testing with a plurality of feature-specific modules. The feature-specific modules are configured to generate a first set of information with the simulation model and compare the first set of information to a second set of corresponding information from the simulation model. In the above-described testing, the first set of information postdates the software revision and the second set of information predates the software revision.

Abstract: A method, system, and computer usable program product for fracturing a continuous mask usable in photolithography are provided in the illustrative embodiments. A first origin point is selected from a set of points on an edge in the continuous mask. A first end point is identified on the edge such that a separation metric between the first origin point and the first end point is at least equal to a threshold value. Several alternatives are determined for fracturing using the first origin point and the first end point. A cost associated with each of the several alternatives is computed and one of the alternatives is selected as a preferred fracturing. Several pairs of origin points and end points are formed from the set of points. Each pair has a cost of a preferred fracturing between the pair. The continuous mask is fractured using a subset of the several pairs.

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract: A method for designing a two-dimensional array overlay target set comprises the steps of: selecting a plurality of two-dimensional array overlay target sets having different overlay errors; calculating a deviation of a simulated diffraction spectra for each two-dimensional array overlay target set; selecting a sensitive overlay target set by taking the deviations of the simulated diffraction spectra into consideration; and designing a two-dimensional array overlay target set based on the structural parameters of the sensitive overlay target set.

Abstract: One embodiment of the present invention relates to a system that calibrates a photolithography process model. During operation, the system receives a process model which models a photolithography process. The system further receives measured critical dimension (CD) values for a first set of features that were printed by applying the photolithography process to a layout. The system then calibrates the process model using the measured CD values so that CD values predicted by the process model substantially match the measured CD values, and depth of focus (DOF) values predicted by the process model for a second set of features are substantially maximized.

Abstract: A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count.

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract: A set of parameter drifts is recorded over a period of time for each of a series of stress tests on a system at various stress levels. Each set of the recorded parameter drifts is plotted as parameter drift versus time. The plots are then time shifted in relation to a reference plot to form a single parameter drift plot. A non-linear equation is fitted to the single parameter drift plot and then used to predict parameter drift over the life of the system. The non-linear equation may be modified by adding a stress acceleration factor to allow prediction of parameter drift over time at different stress levels.

Abstract: A semiconductor-device manufacturing method includes steps of performing a sidewall fabrication thereby forming a first pattern structure; measuring an amount of displacement of line portions of the first pattern structure; correcting an overlay specification for an overlay of the first pattern structure and a second pattern structure dynamically based on the amount of displacement; and determining whether an error in the overlay of the first pattern structure and the second pattern structure meets the corrected overlay specification.

Abstract: A computer readable storage medium stores a program for generating reticle data for producing a reticle used in an exposure apparatus, the program including the steps of classifying target patterns to be formed on a substrate into a plurality of direction groups, extracting, for each of the plurality of direction groups, a region suited to resolution of a target pattern belonging to the direction group from an effective light source distribution formed on a pupil of a projection optical system by an illumination optical system, thereby determining the extracted region as a partial light source, executing, for each of a plurality of partial light sources determined in the step of extracting a region, processing of determining a pattern to be placed on a reticle when each partial light source is used as an illumination condition, and merging patterns determined in the step of executing processing.

Abstract: The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate ?i of spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate ?i, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate ?i, and a total energy entropy factor comprising total energy entropy of said diffraction orders. The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1.

Abstract: Provided is a semiconductor device that can be reduced in size while variation in shape among circuit patterns is reduced. The semiconductor device includes multiple circuit patterns and first dummy patterns. The multiple circuit patterns are disposed at regular intervals, and are used as part of the circuit. The multiple circuit patterns consist of two outermost circuit patterns and the other inner circuit patterns. The first dummy patterns are disposed on outer sides of the two outermost circuit patterns, respectively. The distance between each of the outermost circuit patterns and the corresponding first dummy pattern is equal to a distance between any adjacent two of the circuit patterns. A width of each of the first dummy patterns is smaller than a width of any of the circuit patterns, and is equal to a minimum design rule width, for example.

Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract: An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product.

Abstract: An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to avoid or minimize cross-capacitance problems on the IC design. A cost may be assigned to different candidate metal fill shapes. The cost is associated with the expected effect upon timing requirements by the metal fill shape, with lower costs corresponding to lower expected impacts upon the timing requirements. To meet density requirements, lower cost metal fill shapes are inserted prior to higher cost metal fill shapes.

Abstract: A technique for quantitatively expressing a manufacturing difficulty level of a photomask and for efficiently manufacturing the photomask is provided. A mask manufacturing difficulty level different for each mask layout, product, and mask layer is relatively recognized with a mask manufacturing load index calculated by a mask manufacturing load prediction system, and when layout correction is possible, the final layout is corrected to a layout with a low difficulty level, and a mask ordering party provides a mask manufacturer with information regarding the mask manufacturing difficulty level in an early stage. The mask manufacturing load index is expressed with a defect guarantee load index and a lithography load index.

Abstract: A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot spots determination.

Abstract: A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing.

Abstract: A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more lithographic contours. A mask and target movement module analytically evaluates a direction for mask and target movement thereby forming a plurality of pairs of mask and target movements. The mask and target movement module identifies a best pair of mask and target movements from the plurality of mask and target movements that minimizes a weighted cost function. A shape adjustment module adjusts at least one of a target shape or the mask shape based on the best pair of mask and target movements.

Abstract: A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Abstract: Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes “known good” patterns, which chip fabricators know from experience are successful, and “known bad” patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.

Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed.

Abstract: A charged particle beam writing apparatus which the apparatus includes a first area density calculation unit and a first dimension error calculation unit. The apparatus includes a first dimension calculation unit which calculates a second dimension of a pattern obtained by correcting the first dimension error of the first dimension, a second area density calculation unit which calculates a second area density occupied by the pattern of the second dimension in the predetermined region, a second dimension error calculation unit which calculates a second dimension error caused by the loading effect, a second dimension calculation unit which calculates a third dimension by adding the second dimension error to the second dimension, a judgment unit which judges whether a difference between the first dimension and the third dimension is within a predetermined range, and a writing unit which writes the pattern of the second dimension onto a target workpiece.

Abstract: The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a first characteristic linear dimension that is 15% or less of a wavelength of the light; a second tile, the second tile being transparent to the light, the second tile having a second characteristic linear dimension that is 15% or less of the wavelength of the light; and a third tile, the third tile being opaque to the light, the third tile having a third characteristic linear dimension that is 15% or less of the wavelength of the light.

Abstract: The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.

Abstract: A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.

Abstract: The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a first characteristic linear dimension that is 15% or less of a wavelength of the light; a second tile, the second tile being transparent to the light, the second tile having a second characteristic linear dimension that is 15% or less of the wavelength of the light; and a third tile, the third tile being opaque to the light, the third tile having a third characteristic linear dimension that is 15% or less of the wavelength of the light.

Abstract: The invention provides apparatus and methods for processing substrates using pooled statistically based variance data. The statistically based variance data can include Pooled Polymer De-protection Variance (PPDV) data that can be used to determine micro-bridging defect data, LER defect data, and LWR defect data.

Abstract: A desired set of diffracted waves using mask features whose transmissions are chosen from a set of supported values are generated. A representation of the mask as a set of polygonal elements is created. Constraints which require that the ratio of the spatial frequencies in the representation take on the amplitude ratios of the desired set of diffracted waves are defined. An optimization algorithm is used to adjust the transmission discontinuities at the edges of the polygons to substantial equality with the discontinuity values allowed by the set of supported transmissions while maintaining the constraints.

Abstract: Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs are provided. One method includes generating simulated images illustrating how each of the different reticle designs will be printed on a wafer at different values of one or more parameters of the wafer printing process. The method also includes detecting defects in each of the different reticle designs using the simulated images. In addition, the method includes determining a process window for the wafer printing process for each of the different reticle designs based on results of the detecting step.

Abstract: A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.

Abstract: An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield.

Abstract: Methods and systems for allowing an Integrated Circuit designer to specify one or more design rules, and to determine the expected probability of success of the IC design based on the design rules. Probability information is compiled for each circuit component, that specifies the probability of the circuit component working if a characteristic of the circuit component is varied. As the design rules are examined, the probability of each component working is calculated. The probabilities are combined to determine the overall probability of success for the IC design. Furthermore, the IC design may be broken into a plurality of portions, and design rules can be separately specified for each portion. This allows a designer the flexibility to use different design rules on different portions of the IC design.

Abstract: A method for defect diagnosis and management, which is implemented in a process for fabricating an article, comprising the following steps: obtaining an inspection image of the article, wherein the inspection image shows at least one defect of the article; retrieving a design layout corresponding to the inspection image, wherein the design layout has a plurality of conductive regions; matching the inspection image and the design layout for correcting the coordinates of the defect on the design layout; and judging the overlaps of the conductive regions so as to obtain a short failure if the defect covers two conductive regions, obtain a open failure if the defect intercepts one of conductive region, or obtain no failure if the defect overlaps one of conductive region but not intercepts or covers another conductive region.

Abstract: The contour shape of an aerial image formed on a resist by projecting a test pattern onto the resist via a projection optical system is computed. The shape of a resist pattern formed by the exposure using the test pattern and the development process is measured. A correction model indicating the relationship between the amount of characteristic of the contour shape and the amount of correction determined in accordance with the difference between the computed contour shape and the measured shape of the resist pattern is created. The contour shape of an aerial image formed on a resist by projecting an arbitrary pattern onto the resist via the projection optical system is computed. The shape of a resist pattern corresponding to the arbitrary pattern is predicted by correcting the computed contour shape of the aerial image, using the amount of correction given by the correction model in correspondence with the amount of characteristic of the contour shape.

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: A method for designing a mask is disclosed. A chip region can be defined and reduced to form a parent dummy pattern. A mesh dummy pattern can be formed, and portions where the parent dummy pattern and the mesh dummy pattern overlap each other can be removed to form offspring dummy patterns.

Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask to determine a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has edges, and where each target edge pair is defined by two of the edges of one or more of the polygons. The number of the target edge pairs is reduced to decrease computational volume in determining the manufacturing penalty in making the lithographic mask. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs as reduced in number. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.