Abstract: A method of intra-block memory usage analysis for a program can include identifying a memory block that has been allocated to the program and determining at least one intra-memory block usage characteristic for the allocated memory block.

Abstract: Methods and apparatus are provided for exploring paths through a graph representation of a program or another entity. According to one aspect of the invention, at least one property of a state machine, such as a graph representing a software program, is evaluated. One or more paths in the state machine are evaluated using a state exploration algorithm, wherein the state exploration algorithm maintains a stack data structure representing a current path being processed from an entry state to a current state and a visited state cache indicating zero or more states that have been evaluated. When a state satisfies at least one property, such as having an error, each of the states in the path are removed from the visited states cache if the path satisfies one or more predefined criteria. The one or more predefined criteria may comprise a feasibility of the path.

Abstract: A system and method for program verification includes generating a product transaction graph for a concurrent program, which captures warnings for potential errors. The warnings are filtered to remove bogus warnings, by using constraints from synchronization primitives and invariants that are derived by performing one or more dataflow analysis methods for concurrent programs. The dataflow analysis methods are applied in order of overhead expense. Concrete execution traces are generated for remaining warnings using model checking.

Abstract: Methods are provided that allow a false path pruner to traverse a directed acyclic graph in conjunction with one or more checker programs that are analyzing a program for defects or other artifacts of interest. While the checkers may have ways of avoiding re-traversal of portions of the graph that have already been traversed, the false path pruner may override such decisions made by the checkers as a result of a false path in order to allow re-traversal during a future different traversal when that same defect or artifact may not lie along a false path, and therefore avoid missing a valid defect or artifact. Computer programs stored on tangible media are provided that implement the methods of the invention.

Abstract: A system and method for mapping software components (e.g., source files, binary files, modules) to test cases that test the components and providing rating information regarding each test case's effectiveness against its tested components. Each test case is applied to test a corresponding subset of the components, during which data are gathered (e.g., amount or elements of a component that were tested, which components were tested, time). Each test case is applied separately so that correlations between each test case and the corresponding subset of the software components can be recorded (and vice versa). A rating is generated to indicate how completely or effectively a test case covers a software component. A bipartite graph and/or other data structures may be constructed to map test cases to the software components they test, and vice versa.

Abstract: A method of supporting the optimization of a test program that is made up of a plurality of actions is described. The method may include applying the test program to a device, recording a protocol having a plurality of entries, each corresponding to an action and each specifying at least the type and the time the action is performed, outputting a graphic representation of the sequence of the actions derived from the protocol highlighting at least one selected type of action performed during the application of the test program.

Abstract: The present invention provides a graphical model in a computing environment, where the graphical model includes at least a caller entity. A call command associated with the caller entity is executed, where the call command includes at least a partial name of the callee entity. The at least one callee entity may be identified based on the partial name of the at least one callee entity provided in the call command. The at least one callee entity may then be called.

Abstract: A workflow application is represented by a graph comprising a plurality of components, some of which may be processes. At least two of the processes are interpreted according to different respective sets of rules. The sets of rules are implemented in either a plurality of respective navigation engines or in a single engine implementing multiple sets of rules.

Abstract: Pointer analysis is used for different applications, e.g., compilers, debugging tools and programs understanding tools, each having different requirements. A framework for pointer analysis is provided that defines a multidimensional space, for example a three-dimensional space, containing an order sensitivity dimension, a predicate sensitivity dimension and a value persistence dimension. A point in the three-dimensional space is identified. This point yields values for order sensitivity, predicate sensitivity and value persistence. Pointer analysis is then conducted on a computer program in accordance with the identified values for order sensitivity, predicate sensitivity and value persistence.

Abstract: The present invention provides a system and method for detecting problems caused by access to incompletely initialized data storage in assembler and high-level language programs. An internal representation of the control flow of the source code of the assembler program is generated and a data-flow analysis method is applied to the internal representation.

Abstract: Methods and systems of testing software and modeling user actions are described. In some embodiments, multiple different algorithms are provided for operating on a software model. The software model describes behavior associated with software that is to be tested. Different sets of algorithms can be selected for operating on the software model to produce a sequence of test actions that are to be used to test the software. The algorithms can be mixed and matched to achieve a desired testing result. In some embodiments, the different algorithms comprise deterministic algorithms, random algorithms, and various types of algorithms therebetween. In one embodiment, the software model comprises a state graph having nodes that represent state, and links between the nodes that represent actions. The different algorithms that are available for selection can have different graph traversal characteristics such that the state graph can be traversed in different manners.

Abstract: Traces routed through a computer depiction of a routing area of a system, such as an electronics system, comprise a plurality of connected nodes. The traces may be smoothed, straightened, or otherwise adjusted (e.g., to correct design rule violations) by assigning forces to the nodes and moving the nodes in accordance with the nodes. The forces may be based on such things as the proximity of the nodes to each other and to obstacles in the routing area.

Abstract: Sequential digital integrated circuits have stable state nodes that are capable of retaining their state (logic value) even in the absence of any input directly driving these points. However, in addition to stable state nodes, some custom-designed digital circuits have so-called transient state nodes. A transient state node is defined as node that can directly affect the value of a stable state node and is combinatorially driven by inputs of the circuit, but the transition delay from at least one input to the node is greater than a predefined threshold value. Identifying such transient state nodes, along with the stable state nodes, is critical for the efficient simulation of custom digital circuits by a hierarchical device level digital simulator. A method is provided herein for identifying transient state nodes in a digital circuit, given the circuit's netlist and the identity of the stable state nodes in the circuit.

Abstract: Program execution profile data is collected by direct measurement of some code paths, and by inferring data for unmeasured paths. The data collection process may cause errors, which are propagated by the inferencing process. The profile data thus constructed is further enhanced by detecting certain data mismatches, and adjusting inferred data to reduce the scope of errors propagated during the inferencing process. Preferably, a control flow graph of the program being measured is constructed. Mismatches in the total weights of input arcs versus output arcs are detected. For certain specific types of mismatches, it can be known or guessed which count is incorrect, and this count is accordingly corrected. Correction of arc counts proceeds recursively until it is no longer possible to correct mismatches. Additionally, certain other conditions are adjusted as presumed inaccuracies.

Abstract: An improved testing assessment tool and methodology maps the Testing Maturity Model (TMM) structure to individual test areas, thereby enabling comprehensive and targeted improvement. In this way, the present invention uses the five TMM maturity levels to assess individual areas, rather than merely assigning a single maturity level to the entire organization. Embodiments of the present invention include a quick assessment that includes a relatively small number of questions to be subjectively answered using the TMM hierarchy. Embodiments of the present invention further include a full assessment that includes a relatively large number of questions to be discretely answered, with these results being use to evaluate various testing areas using the TMM hierarchy.

Abstract: An interface design tool may include a traditional call flow design view and a traditional WSDL interface design view. The call flow design view may allow for the grouping of the call flow into segments or exchanges, and allow for labeling of each message in the segment. The tooling then allows for the creation of a mapping between WSDL operations and the call flow. The mapping may be labeled with the interaction type. The output of the visual artifacts may then be a WSDL and call flow XML document, where the additional bindings are included for the operations that capture the interaction relationships.

Abstract: A system and method for computing dataflow in concurrent programs of a computer system, includes, given a family of threads (U1, . . . , Um) and a Linear Temporal Logic (LTL) property, f, for a concurrent program, computing a cutoff for the LTL property, f, where c is called the cutoff if for all n greater than or equal to c, Un satisfies f if Uc satisfies f. The cutoff is computed using weighted multi-automata for internal transitions of the threads. Model checking a cutoff number of processes is performed to verify race freedom in the concurrent program.

Abstract: An instance of a flow definition language for designing an integrated circuit implementation flow. The instance of the flow definition language includes a hierarchical collection of stages for a physical chip design. Relational constraints define the execution order of a plurality of tasks in the hierarchical collection of stages. Parameters customize the plurality of tasks. The relational constraints and parameters are hierarchically defined, such that higher order definitions in the hierarchical collection of stages override lower level definitions of the relational constraints and parameterized knobs.

Abstract: A Java application is debugged in a Java micro device by selectively loading from a host computer into the device, a subset of Java classes and/or Java resource files that is used during the debugging the Java application in the device, that is automatically selected from a set of Java classes and/or Java resource files in the host computer. Thus, the need to load a potentially huge Java ARchive (JAR) file that contains all classes and/or resources, at the start of debugging, can be reduced or eliminated. The invention also may be used to load modules that are used during debugging an application on a device from a host computer.

Abstract: A system and method for implementing a data-flow based system includes three basic components: a data-flow based scheduling environment that balances the needs of data initiated program execution as a result of flows with other practical considerations such as user responsiveness, event driven invocation, user interface considerations, and the need to also support control-flow based paradigms where required; a visual programming language, based on the flow of strongly-typed run-time accessible data and data collections between small control-flow based locally and network distributed functional building-blocks, known as widgets; and a formalized pin-based interface to allow access to data-flow contents from the executing code within the widgets. The pins on the widgets include both pins used to control execution of a widget as well as pins used to receive data input from a data flow.

Abstract: A method for debugging flowchart based computer programs for industrial controllers, in particular motion controllers, wherein suspend commands are assigned to the graphical elements. Through the use of a task control mechanism in the run time system, the user may debug the program on the flowchart level, using a single-step mode and/or a breakpoint mode.

Abstract: An embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, and converting said two or more basic blocks into code blocks, where the code blocks are formed into the control-dataflow graph. Another embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, forming a lode node in at least one of said basic blocks, forming a store node in at least one of said code blocks, inserting a delay node in at least one of said code blocks, segregating external hardware logic modules from said control flow graph, and converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph.

Abstract: A system and method for visualization and debugging of constraint systems and for constraint resolution. The present invention features a systematic, graphical representation that relates generation objects and generation decisions, preferably for example as a simple, two dimensional chart. The representation of relationships between generation entities and generation decisions, and the order in which generation decisions are made, help the user to identify and solve generation problems.

Abstract: A facility control monitor method and a facility control monitor apparatus capable of visually tracing a control logic and easily finding a cause of an operation trouble caused by the control logic. The facility control monitor method monitors control performed by a control device included in a facility having a controllable device, the control device for controlling the controllable device, a setting device for transmitting a setting control value to the control device, and a sensor for transmitting an operation state measurement value of the controllable device to the control device. Processes of control performed by the control device are stored. When an arbitrary date and time is specified by a trace controller (35), predetermined control steps of the specified date and time and after are displayed in a flowchart on a control flow display unit.

Abstract: An improved method is provided for performing register allocation in a compiler. This method determines the allocation of a plurality R of registers of a processor for use during the execution of a software program. The register allocation process is treated as a graph-coloring problem, such that an interference graph is constructed for the software program, the graph is simplified, and an R-coloring the interference graph to the extent possible is attempted. Then, spill code is inserted in the software program each for each uncolored node of the graph, a new interference graph is constructed, and the process is repeated. During the simplification process, nodes with degree greater than or equal to R are removed from the graph in an order dictated by a spill cost metric. During the coloring process, these same nodes are reinserted in the graph in an order dictated by reapplying the spill cost metric.

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment, determine the control flow relationship between breakpoints and graphically display this relationship. Breakpoints are added to a breakpoint group based on their position within the control flow of a program. In an embodiment, when a control flow construct is selected in the graphical display, the breakpoints associated with the control flow construct are added to a breakpoint group.

Abstract: Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of multiprocessor digital signal processors (DSP). This approach substantially reduces the cost of pre-initializing the contents of VLIWs.

Abstract: An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.

Abstract: A method of obfuscating an object-oriented program is provided. A program is provided that is defined in terms of a plurality of classes. Each of the classes has at least one of a field and a method. At least two of the plurality of classes are combined into a combined class. When the at least two classes are combined, at least one field from at least one of the two classes is included in the combined class, and/or at least one method from at least one of the two classes is included in the combined class. After the at least two classes are combined, the program is transmitted.

Abstract: A zero-footprint remotely hosted phone application development environment is described. The environment allows a developer to use a standard computer without any specialized software (in some embodiments all that is necessary is a web browser and network access) together with a telephone to develop sophisticated phone applications that use speech recognition and/or touch tone inputs to perform tasks, access web-based information, and/or perform commercial transactions. Some embodiments support concurrent call flow tracking that allows a developer to observe, using a web browser, the execution of her/his application. A variety of reusable libraries are provided to enable the developer to leverage well-developed libraries for common playback, input, and computational tasks. Embodiments support rapid application deployment from the development environment to hosted application deployment to the intended audience.

Abstract: A method for modeling a Discrete Event System includes the steps of: a) receiving the user-defined requirement and specification of a Discrete Event System; b) extracting events and action from the user-defined requirement and specification and storing the events and action; c) generating a tree-type data structure including start node; d) searching the stored events to determine existence of allowable events from the event represented by a leaf node. which quits the generation of the tree-type data structure when there is no allowable event; e) when there is the allowable event in the stored events, generating a child node of the leaf node, the child node representing to allowable event and F) iterating the step of searching and the step of generating a child node for all the leaf nodes of the tree-type data structure.

Abstract: A system and method for accessing an Advanced Configuration and Power Interface (ACPI) namespace nodal tree in a computer platform employing an ACPI-compatible implementation is disclosed.

Abstract: Primary and alternate circuits on protocol flow objects representing application protocol layers in a communications channel are linked to connect multiplexed requests and replies. Various protocol flow objects are arranged in a hierarchical flow tree data structure that corresponds to multiple protocol layers in the channel. One branch of the flow tree data structure is selected to represent a reply, and source-destination address pairs for lower layer protocol flow objects for the reply are used to identify the branch of the flow tree data structure that represents the corresponding request. In one aspect, the address pairs for network and transport layer protocol flow objects for the reply are used to identify the request branch. In a further aspect, a link layer protocol object corresponding to the link layer protocol object for the reply may be used to reduce the number of network and transport protocol flow objects examined to identify the request branch.

Abstract: Described is a method and system for performing path-sensitive value flow analysis on a software program. Concrete state and value alias information is tracked along each statement and each relevant path in an abstract program and is stored as a symbolic state in a symbolic store. The value alias information includes a first set of aliases that identify aliases for a designated value that is being analyzed and a second set of aliases that identify possible aliases for the designated value. The value alias information is obtained using imprecise memory alias analysis. Along each relevant path for each statement, transforms are applied to the sets of aliases to update the first and second sets of aliases. The transforms are applied based on the type of statement being processed. Symbolic states existing at the same location are merged if the value alias information is identical within the symbolic states.

Abstract: This invention is applied to a system design support system which handles at system level, e.g., a specification for software executed by a computer, a specification for hardware combined with semiconductor devices and the like, a specification for an embedded system constituted by a combination of software and hardware, and a specification for a business process such as a work flow. A consideration is given to difficulty in efficiently implementing an interrupt in a specification created in a system description language in such a case where the interrupt is defined at a lower level which is structurally separate from a portion where the interrupt actually occurs. An interrupt structure localizing apparatus specifies a portion in a system-level specification in which an interrupt actually occurs and localizes the portion, thereby obtaining a specification structure in which an interrupt does not occur across hierarchical structures.

Abstract: A system that detects and resolves circular paths within a graphical flow diagram that represents the logical operation of a corresponding application program. The flow diagram is formed by interconnecting symbolic representations that correspond to program objects configured to execute associated functions in response to corresponding triggering events. The functions of the program objects are called upon and executed by the application program at run-time. At the program objects, a busy indicator is established. When a program object is triggered by its respective event, the object first tests its busy indicator to determine whether it is already in the process of executing its associated function. If not, it proceeds to execute its associated function in response to an earlier triggering event. If, however, the object is already in the process of executing its associated function, then the object is blocked from re-executing in response to this new triggering event.

Abstract: Methods and computer readable media for a software tool capable of subdividing programs into autonomous modules, where the modules enable a feature of the program, are provided. One exemplary method includes a computer implemented method for identifying modules of an executable program. The method begins with initiating the executable program. Then, the executable program is monitored as it is running. The monitoring of the executable program further includes, identifying interrelated classes for each of the modules where each of the modules correspond to a feature functionality of the executable program. Also included in the monitoring is generating a data structure for each module as the executable program is running. Here, the data structure defines the classes for each feature functionality.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and develop a data flow program for execution in a multiprocessor computer system. The tool allows the programmer to define a region divided into multiple blocks, wherein each block is associated with data operated on by code segments of the data flow program. The development tool also maintains dependencies among the blocks, each dependency indicating a relationship between two blocks that indicates that the portion of the program associated with a first block of the relationship needs the resultant data provided by the portions of the program associated with a second block of the relationship. The development tool supports several debugging commands, including insertion of multiple types of breakpoints, adding and deleting dependencies, single stepping data flow program execution, and the like.

Abstract: The present invention relates to a humanity interface development system of a testing program of a circuit board, essentially including: building configuration of objects to be tested, defining footing of objects to be tested, using a program generator, building data of the testing chapters, building documents and figure files of objects to be tested, building reference data, building intercepted data of coordinates of positions of the parts, building relationships of items to failure rates of parts, and linking and compiling files, thereby forming a humanity interface, to build a data base required by the testing programs simultaneously, for testing the same circuit board in a large amount manner, thereby achieving the purpose of convenience and utility.

Abstract: Presently described is a decompilation method of operation and system for parsing executable code, identifying and recursively modeling data flows, identifying and recursively modeling control flow, and iteratively refining these models to provide a complete model at the nanocode level. The nanocode decompiler may be used to determine if flaws, security vulnerabilities, or general quality issues exist in the code. The nanocode decompiler outputs in a standardized, human-readable intermediate representation (IR) designed for automated or scripted analysis and reporting. Reports may take the form of a computer annotated and/or partially human annotated nanocode listing in the above-described IR. Annotations may include plain English statements regarding flaws and pointers to badly constructed data structures, unchecked buffers, malicious embedded code or “trap doors,” and the like. Annotations may be generated through a scripted analysis process or by means of an expert-enhanced, quasi-autonomous system.

Abstract: A method and system for verifying resolution of attributes of a computer program. The verification system analyzes a command-based computer program prior to runtime to determine whether the input attributes associated with a command would be properly resolved prior to execution of that command at runtime. During verification, the verification system processes the commands of the program in sequence. For each input attribute of a command, the verification system identifies a source (e.g., output attribute of a command) of the value for the input attributes. The verification system then determines whether that source would be properly resolved during execution of the computer program.

Abstract: A section of a computer program is used to ascertain a control flow description and a data flow description, and program elements are selected from the section of the computer program. For each selected program element, a stored fault description associated with a respective reference element is used to ascertain an element fault description which describes possible faults in the respective program element. The element fault descriptions are used to ascertain the overall fault description, taking into account the control flow description and the data flow description.

Abstract: A system and method for executing multiple graphical programs, in which program output from each graphical program is displayed in a single graphical user interface. Program output from a first graphical program and program output from a second graphical program may be displayed in a single graphical user interface on a display. The single graphical user interface may also be used for specifying program input for the first and/or the second graphical program. Any number of graphical programs may share the single graphical user interface. In one embodiment different graphical program development environments may be used to create the separate graphical programs.

Abstract: System and method for enabling graphical program polymorphism. A “polymorphic node” to be included in a graphical program may be created and configured. A parameter interface that defines allowable inputs and outputs for the polymorphic node may be specified, and a set of functions or subprograms may be associated with the polymorphic node. The functions may have parameter interfaces that specify particular data types for the inputs/outputs of the functions. Once a polymorphic node is included in a graphical program, the node may be configured with typed inputs and outputs. The graphical programming system may determine a particular function associated with the polymorphic node to match the polymorphic node to, based on the data types of the configured inputs and outputs. This determination may also be based on an ordering specified for the set of functions associated with the polymorphic node. A best-fit heuristic for automatically making this determination is described.

Abstract: A computer system has an input system and an output system. Program code to be debugged has a plurality of program code statements. The input system is utilized to indicate an error variable in the program code. The error variable has an error value that differs from a desired value. An error set of the error variable is obtained, which is a subset of the statements in the computer readable code. Each statement in the error set is relationally connected to the error variable. A priority value is given to each statement in the error set. The priority values indicate a computed probability that the associated statement is an error source of the error variable. Finally, the output system is used to present each statement in the error set in an ordered manner according to the priority values.

Abstract: In an exemplary aspect of the invention, a method for displaying a computer program organization on a screen monitor provides a graphical representation of a source code structure during a debugging session. The graphical representation may include a program call graph (PCG) or portion thereof for a procedure within the source code. The PCG may comprise a P_node to symbolize a procedure and an association reference to identify the relationship between two such procedures. Alternatively, the graphical representation may include a control flow graph (CFG) or portion thereof associated with a procedure within the source code. The procedure may comprise of one or more basic blocks, each basic block associated with a potentially executable source code statement. The CFG may comprise a B_node symbolizing a first basic block and an association reference to identify the relationship between two such basic blocks.

Abstract: A set of computer code is profiled by breaking each code segment of the computer code down into basic instructions. Thereafter, the set of computer code is executed. As each code segment is executed, a log is updated to indicate execution of that code segment. This is done for each executed code segment; thus, at the end of execution, the log reflects all of the code segments that were executed, and how many times each code segment was executed. Using the log, and a set of calibration statistics, which specify how much processing time is consumed by each basic instruction, an overall execution cost is derived for each executed code segment. The set of overall execution costs for all of the executed code segments are incorporated into an overall profile for the set of computer code.

Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.

Abstract: A method for changing an operation performed by an electronic device includes defining a process flow chart of the operation to be performed by the electronic device, the process flow chart having one or more primitive actions, the operation having one or more components, the primitive action operating on the components to produce an output. The method further includes determining a number of information dispersal units for each of the components. For each of the components, defining a set of information dispersal units, transforming one or more of the primitive actions of the operation using a transform function to create a transformed primitive action, and applying each of the transformed primitive actions to all the respective sets of information dispersal units to produce a transformed set of transformed information dispersal units.

Abstract: Debugger impact reduction through motion of an induction variable based breakpoint (“IV-breakpoint”) set within a program loop, where the IV-breakpoint and the loop are controlled by an induction variable having an induction rate, may include extracting, from program code within the program loop, the induction rate; extracting, from the IV-breakpoint, a final value of the induction variable for which the IV-breakpoint would be satisfied; and if the IV-breakpoint is satisfied and the induction variable has a present value that would be beyond the final value upon a next iteration of the loop based on the induction rate, removing the IV-breakpoint. Debugger impact reduction may further include setting, at one or more loop exit program positions, a reset breakpoint; and if one of the reset breakpoints is satisfied, removing the reset breakpoints and/or reestablishing the IV-breakpoint.