Using Program Flow Graph Patents (Class 717/132)
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Patent number: 6959431Abstract: A computer-implemented method and system for measuring and reporting on the effectiveness of software program testing combines information from existing debugging and analysis tools to provide various displays of the logical paths of a program under test that have been executed, as well as related data. Logical path execution is determined based on the number of times a decision block has been executed and the number of times statements coming out of the decision block have been executed.Type: GrantFiled: February 15, 2000Date of Patent: October 25, 2005Assignee: Compuware CorporationInventors: Pamela L. Shiels, William Noble, Michael A. Horwitz, David Lagermeier
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Patent number: 6957122Abstract: A method for generating and visualizing a task-oriented step representation of one or more parts programs in machine tools or production machines is described. A syntax analyzer searches the parts program for key terms, whereafter a task-oriented step representation of the parts program(s) is generated based on the key terms found in the search. The task-oriented step representation can then be visualized to a user. The disclosed method can advantageously be used to visualize and display parts programs of machine tools or production machines, which are available in ASCII code, in form of a step representation or step diagram without necessitating changes in the parts programs.Type: GrantFiled: February 27, 2004Date of Patent: October 18, 2005Assignee: Siemens AktiengesellschaftInventors: Matthias Dütsch, Klaus Hertinger, Timo Pallas, Martin Seithe, Winfried Wacker
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Patent number: 6934938Abstract: A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.Type: GrantFiled: June 28, 2002Date of Patent: August 23, 2005Assignee: Motorola, Inc.Inventors: Philip E. May, Kent Donald Moat, Raymond B. Essick, IV, Silviu Chiricescu, Brian Geoffrey Lucas, James M. Norris, Michael Allen Schuette, Ali Saidi
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Patent number: 6922828Abstract: A method and system for detecting and counting bytecode sequences in a data processing system is provided. A bytecode tree data structure is used to represent sequences of bytecodes. A bytecode sequence is a subset of consecutive bytecodes within the set of bytecodes. The bytecode tree data structure contains a set of nodes in which each node represents a bytecode in a bytecode sequence or subsequence and in which a path through the bytecode tree data structure represents a bytecode sequence or subsequence. Each node of the bytecode tree data structure records one or more bytecode occurrence statistics for its corresponding bytecode in a set of bytecode sequences or subsequences. In order to determine the frequency of occurrence of common bytecode sequences and subsequences, a bytecode sequence tree data structure is generated from a set of bytecode sequences.Type: GrantFiled: September 9, 1999Date of Patent: July 26, 2005Assignee: International Business Machines CorporationInventors: William Preston Alexander, III, Frank Eliot Levine, Robert J. Urquhart
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Patent number: 6922830Abstract: A compiler and method of compiling provide enhanced performance by utilizing a skip list data structure to store various properties of a program at points of interest in the procedure, for example, the properties of the statements in each block in the control flow graph. A special procedure is used to initialize the skip list, prior to performing data flow analysis, to ensure that the skip list structure is not used in an inefficient manner as a result of initialization. Furthermore, special procedures are used to simultaneously scan and compare two skip lists as part of solving dataflow equations.Type: GrantFiled: July 27, 2000Date of Patent: July 26, 2005Assignee: International Business Machines CorporationInventor: William Jon Schmidt
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Patent number: 6904590Abstract: Methods are discussed that enhance program analysis. One aspect of the invention includes a method for checking a model of a program. The method includes a control-flow graph having vertices from the model, applying a transfer function to each vertex to form a set of path edges, and analyzing the set of path edges of a vertex. The set of path edges includes valuations that are implicitly represented so as to inhibit an undesired explosion in the valuations that would hinder the act of analyzing.Type: GrantFiled: May 25, 2001Date of Patent: June 7, 2005Assignee: Microsoft CorporationInventors: Thomas J. Ball, Sriram K. Rajamani
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Patent number: 6865429Abstract: A composite object group (COG) data structure embodied in a computer-readable medium for building a control system that has both a clock cycle and event processing is provided. An interface for passing information to and from the COG data structure is provided. One or more data flow objects are provided in the COG to accept input data and to produce output data on the clock cycle. The data flow object is connected to the interface and provides sampled-data processing for the control system. One or more state machine objects are provided in the COG; each includes a plurality of states and a plurality of transitions between the states that are each triggered by an event. The state machine object provides event-driven processing for the control system, whereby the COG data structure provides both sampled-data and event-driven processing for the control system.Type: GrantFiled: July 29, 2002Date of Patent: March 8, 2005Assignee: Real-Time Innovations, Inc.Inventors: Stanley A. Schneider, Vincent W. Chen, Gerardo Pardo-Castellote, Howard H. Wang, Rajive Joshi
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Patent number: 6865729Abstract: A flowchart-based programming and control system includes a computer with a processor, memory, and display. A device is connected to the computer and is associated with a process. A flowcharting module generates and edits flowchart source code that includes flowchart blocks and that contains logic for operating the device. First and second flowchart blocks assign an operational state of the process. A reason code module associated with the flowcharting module assigns first and second reason codes to the first and second flowchart blocks. The flowchart module compiles the flowchart source code into flowchart object code. A flowchart run-time engine module executes the flowchart object code to control the process. The flowchart object code generates the first and second reason codes during execution of the first and second flowchart blocks. A performance analysis module and a charting module record and graphically represent the operational state of the process over time.Type: GrantFiled: September 29, 2000Date of Patent: March 8, 2005Assignee: Entivity, Inc.Inventors: Andrew H. McMillan, Joseph Gasiorek, Thomas Harkaway
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Patent number: 6854089Abstract: Techniques for generating maps of graphical user interfaces of applications are provided. An application mapper programmatically executes an application to generate a map of the graphical user interface of the application. The map can include windows, graphical user interface objects, actions, shortcuts, and transitions. The map can be utilized by a script generator to generate scripts that include instructions to test the application.Type: GrantFiled: October 5, 1999Date of Patent: February 8, 2005Assignee: International Business Machines CorporationInventors: John Santee, Robert Warfield
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Publication number: 20040243982Abstract: A method for analyzing and optimizing programs that operate on a data structure where the state of the data structure must be valid at certain program points. The program is represented as a control-flow graph. The method decomposes the state of the data structure into components, and applies partial redundancy elimination to place instructions that set the state of the data structure, with a variation that permits speculative placement. Application extends to manipulating a stack that keeps track of what to do should an exception arise during execution. In this context, a control-flow representation of contingencies is converted into placement of instructions that manipulate the stack.Type: ApplicationFiled: October 24, 2003Publication date: December 2, 2004Inventor: Arch D. Robison
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Patent number: 6826579Abstract: A computerized method for automatically transforming the process model of a workflow-management-system into trigger-specifications executable within a trigger system. The process model comprises at least one source activity S, a target activity T and a control connector defining a potential control flow from said source activity to said target activity associated with a transition condition P. The source activity S is transformed into a trigger event. The trigger-event, if raised at run-time, indicates to said trigger system that an instance of said source activity has been terminated. The control connector is transformed into a trigger condition, causing said trigger system at run-time, once said trigger event has been raised, to evaluate the truth value of said transition condition. Furthermore said target activity is transformed into a trigger action causing said trigger system at run-time, in case said trigger condition evaluates to TRUE, to start an instance of said target activity.Type: GrantFiled: February 4, 2000Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: Frank Leymann, Dieter Roller
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Patent number: 6820251Abstract: The present invention is a system and method for providing a software recovery mechanism. In architecture, the system includes a compiler that parses a source program. Error condition test logic detects if an error condition test exists in the source program, and determination logic determines if error recovery is enabled when the error condition test is detected. Error recovery flag generation logic generates an error recovery flag code when the error condition test is detected and the error recovery is enabled, and error recovery code is inserted in computer program if error recovery is enabled. The method includes the steps of parsing a source program, and detecting if an error condition test exists in the source program. If an error condition test is detected, determining if error recovery is enabled. An error recovery flag code is created when the error condition test exists and the error recovery is enabled. Error recovery code is inserted into the computer program if error recovery is enabled.Type: GrantFiled: November 6, 2000Date of Patent: November 16, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventor: Lawrence Dwyer
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Patent number: 6813761Abstract: Methods and structures are described that enhance flow analysis for programs. Whereas previous methods are complicated by the presence of function pointers, the present methods present a framework that abstracts function pointers as if they were any other program expressions so as to allow a desired level of analytical decision within a desired duration of analysis. One aspect of the present invention includes inferring types from a program, forming a type graph from the types, and forming a flow graph from the type graph to inhibit imprecise paths so as to enhance context-sensitivity of flow analysis. The methods may be used in any analysis tools such as code browsers and slicing tools.Type: GrantFiled: June 30, 2000Date of Patent: November 2, 2004Assignee: Microsoft CorporationInventors: Manuvir Das, Manuel A. Fahndrich, Jakob Rehof
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Publication number: 20040117772Abstract: A method and apparatus are provided for analyzing software programs. The invention combines data flow analysis and symbolic execution with a new constraint solver to create a more efficient and accurate static software analysis tool. The disclosed constraint solver combines rewrite rules with arithmetic constraint solving to provide a constraint solver that is efficient, flexible and capable of satisfactorily expressing semantics and handling arithmetic constraints. The disclosed constraint solver comprises a number of data structures to remember existing range, equivalence and inequality constraints and incrementally add new constraints. The constraint solver returns an inconsistent indication only if the range constraints, equivalence constraints, and inequality constraints are mutually inconsistent.Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Applicant: International Business Machines CorporationInventors: Daniel Brand, John A. Darringer, Florian Krohm
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Patent number: 6748583Abstract: Provided are an execution monitoring tool, a method and a computer program product for monitoring execution of an hierarchical visual program. Execution progress reports are sent to an execution monitoring controller which maps the report data to its own representation of the hierarchical program to determine the current position within an execution program. The hierarchical structure of the program and the current execution position are displayed during execution on a test system. The execution monitoring controller maintains an hierarchical representation of the visual program's structure, builds an execution stack from the execution progress reports, and compares the received reports with the hierarchical representation to determine a current execution position. The execution reports include the current execution status as well as the position within the execution flow.Type: GrantFiled: December 27, 2000Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: Neta Aizenbud-Reshef, Yael Shaham-Gafni, Michael Starkey, Marc-Thomas Schmidt, Gabi Zodik, Stephen James Todd
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Patent number: 6745383Abstract: A computer method for issuing an early warning includes determining, using change and test coverage and control flow and data flow analyses of a program, locations in the program at which to insert early warning (EW) code to monitor for an event. The program is instrumented with EW code which monitors for the event, by inserting EW code at the determined locations. Upon detecting the event, EW code performs an early action warning, or issues an early action. Early warnings are issued when an EW-instrumented block is reached. Issuance of an early warning action can be conditional upon execution of the program in a particular environment, such as a production environment. Issuance of an EW can also be conditional upon executing an untested block of code that was recently modified.Type: GrantFiled: December 29, 1999Date of Patent: June 1, 2004Assignee: Veritas Operating CorporationInventors: Anant Agarwal, Andrew E. Ayers, Richard Schooler
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Publication number: 20040103402Abstract: The present invention discloses a method of developing a software system. The method facilitates the task of checking the software system's conformity to design during development, testing, and maintenance. A design control flow graph describes how the software system is to operate. Coding of the software system proceeds with reference to the design control flow graph. The design control flow graph can also be used as a framework for the construction of a monitoring module that comprises a collection of functions for checking the coding of the software system. During development, each node in the software system executes a corresponding monitoring function of the monitoring module. The monitoring function verifies, for example, whether the node was entered from a valid predecessor node, and whether some or all variables visible to the node have permissible values.Type: ApplicationFiled: November 25, 2002Publication date: May 27, 2004Applicant: International Business Machines CorporationInventor: Rajendra K. Bera
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Patent number: 6738893Abstract: A process for scheduling computer processor execution of operations in a plurality of instruction word formats including the steps of arranging commands into properly formatted instruction words beginning at one end into a sequence selected to provide the most rapid execution of the operations, and then rearranging the operations within the plurality of instruction words from the other end of the sequence into instruction words selected to occupy the least space in memory.Type: GrantFiled: April 25, 2000Date of Patent: May 18, 2004Assignee: Transmeta CorporationInventor: Guillermo J. Rozas
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Patent number: 6711717Abstract: The present invention is a programming language method called Pipeline Language 1 (PL1) and its associated compiler system for generating logical circuit designs. The semantics allow the implementation to add more slack than exists in the specification, aiding the design of slack-elastic systems. In PL1, the value probe and peek are the most basic operations: receiving a value is done by first using the peek, and then acknowledging it as a separate action. Another embodiment is a PL1 compiler comprised of a technology-independent front-end module and a technology-dependent back-end module. It parses the input, converts it into BDD expressions, checks determinism conditions, generates BDD expressions for assignments and sends and converts the BDD expressions to unary representation. The back-end compiler module is technology-dependent, meaning that different back-end modules generate different circuit design types (e.g. QDI and STAPL).Type: GrantFiled: October 11, 2002Date of Patent: March 23, 2004Assignee: California Institute of TechnologyInventors: Mika Nyström, Alain J. Martin
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Patent number: 6694456Abstract: A method for the graphic presentation of the results of tests of software programs. The software program to be tested is composed of module building blocks and the software program can be presented in the form of a run graph. A run log was produced in the test of this software program. A critical precondition of the inventive method is that the software program to be tested can be resolved into individual program modules. The program run can then be simply displayed as a graph in which the individual program modules are connected to one another (by edges) in the run sequence. A test run protocol (trace protocol) is produced when testing the software program, this protocol containing particulars about the test run, i.e. the reactions of the program to be tested to the individual test instances, for example to the software modules (SIB names) that are respectively traversed.Type: GrantFiled: June 7, 2000Date of Patent: February 17, 2004Assignee: Siemens AktiengesellschaftInventor: Ralf-Carsten Ludwig
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Patent number: 6678884Abstract: A method for determining a status of a variable during an execution of an optimized code, the optimized code being originated from a source code, the method comprising the steps of: (A) Receiving at least a source flow graph, an optimized flow graph and information that describes a connection between instructions within the optimized code and statements in the source code; receiving a request to show the status of the variable at a breakpoint. (B) Generating a source reaching definition set and a reflected optimized reaching definition set. (C) Comparing the source reaching definition set and the reflected optimized reaching definition set and determining a status of a variable.Type: GrantFiled: June 30, 2000Date of Patent: January 13, 2004Assignee: Motorola, Inc.Inventors: Alexander Kesselman, George Agasandian, Yoram Shacham, Arnon Mordoh
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Publication number: 20040003376Abstract: A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input (502, 522) of the data-flow graph, a computational instruction is generated for each node (506, 510, 514 etc) of the data-flow graph, and a sink instruction is generated for each output (520, 540) of the data-flow graph. The computation instruction for a node includes a descriptor of the operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list (A, B, C, . . . , J, K, L, FIG. 2) comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Inventors: Philip E. May, Kent Donald Moat, Raymond B. Essick, Silviu Chiricescu, Brian Geoffrey Lucas, James M. Norris, Michael Allen Schuette, Ali Saidi
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Patent number: 6651243Abstract: A method and system for profiling a program using periodic trace sampling is provided. During the execution of the program, sample-based profiling of the executing program is performed—for a predetermined period, a profiler performs trace processing for the program, after which the profiler pauses and does not perform trace processing for a predetermined period. The periods controlling the profiler may be selected by a user, and the periods may be measured by temporal or non-temporal metrics. The profiler cycles through these periods, during which selected events are processed to generate a profile of the execution flows within the program. For each sample period, a tree data structure is generated in which nodes of the tree data structure represent the routines of the program that execute during the sample period, as may be indicated by entry and exit events caused by the execution of the routines.Type: GrantFiled: October 14, 1999Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: Robert Francis Berry, Frank Eliot Levine, Robert J. Urguhart
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Patent number: 6634023Abstract: The present invention enables re-ordering of instructions to be executed while assuring a precise exception. In Java language, an optimization process of re-ordering instructions to be executed is performed by Just-In-Time compiler. For instance, the instructions lining in order from instruction E1 which was moved forward to instruction S2which had been located before E1 is registered as interrupt inhibited section R1, and from instruction S4 which was moved forward to instruction S3 which had been located before S4 is registered as interrupt inhibited section R2 (S is an instruction which has an affect observable from the outside at the execution, and E is an instruction which may cause an exception). Also, in FIG. 7, S4 which was an instruction behind E1 in the original order is registered as R1's instruction invalid at an exception. If E1 causes an exception, an interrupt handler is activated and the instructions of interrupt inhibited section R1 are copied to another area.Type: GrantFiled: June 16, 1999Date of Patent: October 14, 2003Assignee: International Business Machines CorporationInventors: Hideaki Komatsu, Takeshi Oqasawara
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Publication number: 20030177472Abstract: A method for reducing dynamic memory allocation includes designing a software program using a memory allocation module for allocating memory, analyzing the software program to determine a bound on dynamic memory allocation and modifying the program based on the analyzing. According to one aspect, the program is modified to use static memory allocation in lieu of dynamic memory allocation based on the analyzing. According to another aspect, the program is modified to reduce the amount of dynamically allocated memory based on the analyzing.Type: ApplicationFiled: March 18, 2002Publication date: September 18, 2003Applicant: Sun Microsystems, Inc., a Delaware CorporationInventor: Eduard de Jong
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Publication number: 20030145313Abstract: A trace scheduler schedules instructions within a trace and after register allocation. The trace scheduler computes critical path information across the trace, which is used to schedule instructions across basic block boundaries. In this manner, the efficiency of the compiler is maximized.Type: ApplicationFiled: January 30, 2002Publication date: July 31, 2003Applicant: Sun Microsystems, Inc.Inventor: Spiros Kalogeropulos
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Publication number: 20030079206Abstract: A debugger capable of providing warnings for unreachable breakpoints is disclosed. After a breakpoint has been set by a user, within an application program source code that is monitored by a debugger, a debugger determines whether or not the breakpoint is set on a statement listed in an unreachable statement list. If the breakpoint is set on a statement listed in an unreachable statement list, the debugger displays an unreachable breakpoint warning to the user.Type: ApplicationFiled: October 18, 2001Publication date: April 24, 2003Applicant: International Business Machines CorporationInventors: Cary Lee Bates, John Matthew Santosuosso, William Jon Schmidt
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Patent number: 6553565Abstract: Methods and apparatus for providing a substantially full set of state information to a debugger, without significantly compromising system performance, in order to debug optimized computer program code are disclosed. According to one aspect of the present invention, a method for obtaining information associated with program code includes adding a segment of code, which includes a representation that is effectively not used after it is computed, to the program code. Debugging code is added in proximity to the segment of code, and machine code is generated from the program code. The machine code includes a break point that is associated with the debugging code, and includes an instruction at the breakpoint. Finally, the method includes replacing the instruction at the break point with a branch instruction that is arranged to cause the debugging code to execute.Type: GrantFiled: April 23, 1999Date of Patent: April 22, 2003Assignee: Sun Microsystems, IncInventors: Clifford N. Click, Jr., Christopher A. Vick, Michael H. Paleczny
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Patent number: 6553268Abstract: A programming language for programming industrial controllers in relay ladder logic language, the programming language including both extensions to standard RLL rung form itself and extensions wholly independent of the standard form. The language uses a plurality of templates, each template including truly reusable relay ladder language sections. Most templates also include specifications identifying other templates which provide additional language logic required to define job-specific aspects of the referencing template. Using the templates a machine tree can be provided which mirrors an industrial process. By compiling all of the templates, a relay ladder language program can be provided.Type: GrantFiled: March 16, 2000Date of Patent: April 22, 2003Assignee: Rockwell Automation Technologies, Inc.Inventors: Marvin J. Schwenke, J. Andrew Sinclair, Raymond J. Staron
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Patent number: 6519765Abstract: Java language is, as its specification, capable of detecting an access exceeding an array range, and when there is no user-defined exception handler, moving control to an invoked method after getting out of a method in which an exception occurred, or when there is a user-defined exception handler, moving the process to the exception handler. Accordingly, an array range check is essential since occurrence of an exception may be described as a correct operation. However, an array range check slows execution speed compared with a language which does not require it. In an actual program, there is an array access to ensure that there is no access exceeding a range, and thus elimination of such redundant range checks greatly contributes to improved performance, and in addition, brings about an effect of expanding the range of optimization from the viewpoint of ensuring order of execution between occurrence of an exception and a process with a side effect such as an assignment of a value to an array.Type: GrantFiled: July 9, 1999Date of Patent: February 11, 2003Assignee: International Business Machines CorporationInventors: Motohiro Kawahito, Toshiaki Yasue, Hideaki Komatsu
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Publication number: 20020184616Abstract: A workflow application is represented by a graph comprising a plurality of components, some of which may be processes. At least two of the processes are interpreted according to different respective sets of rules. The sets of rules are implemented in either a plurality of respective navigation engines or in a single engine implementing multiple sets of rules.Type: ApplicationFiled: March 7, 2002Publication date: December 5, 2002Applicant: International Business Machines CorporationInventors: Amanda E. Chessell, Vernon M. Green, Catherine S. Griffin, David J. Vines
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Patent number: 6473896Abstract: A method and system for graphically generating user-defined rules to be used for checking the quality of a language. A Graphical User Interface (GUI) with a plurality of menus provides easy and effective means for generating user-defined rules. Generally, each rule comprises a node type associated with a matching function. Nodes and their properties are graphically generated and connected to construct rules. In one embodiment, the present invention graphically generates user-defined rules to be used for checking the quality of a computer programming language. Each instruction in a computer programming language is represented by at least one node of a particular type stored in a parse tree for describing dependencies between such nodes. Both the parse tree and the rules are stored in the computer. The parse tree is searched beginning from a root node indicating an entry point into the parse tree for at least one of the nodes having such a particular type matching one of the node types.Type: GrantFiled: October 6, 1999Date of Patent: October 29, 2002Assignee: Parasoft, Corp.Inventors: Wendell T. Hicken, Adam K. Kolawa
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Publication number: 20020129340Abstract: Data flow graph representation is combined with message passing and delegation, a stackless execution model, and a real-time compiler technology, to provide an improved software development and distribution paradigm. Polymorphic objects represent nodes that can be reconfigured, replaced, and/or modified as needed. Complex functionality is achieved by passing messages among nodes. Authored content is published by replacing interactive nodes with fixed-value nodes as desired. Software representations can be translated among various isomorphic formats, including data flow graphs and scripts, without loss of information or modifiability.Type: ApplicationFiled: November 8, 2001Publication date: September 12, 2002Inventor: Douglas D. Tuttle
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Patent number: 6449711Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and develop a data flow program for execution in a multiprocessor computer system. The tool displays an interface that enables the programmer to define a region divided into multiple blocks, wherein each block is formed of a set of values associated with a function, and to define sets of the blocks, each block in a set having a state reflected by a designated portion of the program that when executed transforms the values forming the block based on the function. The interface also records any dependencies among the blocks, each dependency indicating a relationship between two blocks and requiring the portion of the program associated with a first block of the relationship to be executed before the portion of the program associated with a second block of the relationship.Type: GrantFiled: February 4, 1999Date of Patent: September 10, 2002Assignee: Sun Microsystems, Inc.Inventor: Jeremy Week
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Patent number: 6442751Abstract: A method is provided for tracking the type of at least one local variable after calling a subroutine. The exemplary method associates each one of a plurality of branch instructions calling the subroutine with a first information, which indicates the type of value stored in the local variable when each one of the plurality of branch instructions is executed. The exemplary method associates at least one execution point-of-interest within the subroutine with a second information. The execution point-of-interest is any point within the subroutine where it may be necessary to ascertain the type of each local variable. The second information is a data structure indicating a change in type made to the local variable after entering the subroutine and before the execution point-of-interest. The exemplary method associates the execution point-of-interest with a return address for the subroutine.Type: GrantFiled: December 14, 1998Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Anthony Cocchi, Janice Cynthia Shepherd
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Publication number: 20020073403Abstract: Defect detection in a software system made of multiple computer program programs is facilitated by using information about cross-program interactions and dependency relationships between programs to analyze the individual programs in such a way that the behavior of the system as a whole is accurately represented. A list of dependency relationships is read in; these dependency relationships are used to determine an order in which the programs should be analyzed. The programs are then analyzed in that order. Information from the analysis of the programs is used to inform the analysis of subsequently-analyzed programs.Type: ApplicationFiled: December 13, 2000Publication date: June 13, 2002Applicant: Microsoft CorporationInventors: Timothy G. Fleehart, Jonathan D. Pincus, Jeffrey S. Wallace