Abstract: A switched capacitor integrator that shares a switched capacitor CAP1 at the input of the integrator for the signal input and the reference capacitor. The operation of the circuit includes discharging the capacitor CAP1 with a first clock signal CK3; transferring an input voltage IN onto the capacitor CAP1 with a second clock signal CK1′; applying a reference voltage REF to a first end of the capacitor CAP1 with a third clock signal CK2; and coupling a second end of the capacitor CAP1 to the integrator with the third clock signal CK2 while the reference voltage REF is applied to the first end of the capacitor CAP1.

Abstract: An SRAM array 22, with improved leakage in standby, raises the wordline driver lower supply voltage Vss-WL when raising the array lower supply voltage Vss-array in standby. When the SRAM array 22 is in active mode, a source voltage is provided to the SRAM array lower supply node Vss-array and to the wordline driver lower supply node Vss-WL. When the SRAM array is in standby mode, a voltage offset is provided between the source voltage and both the SRAM array lower supply node Vss-array and the wordline driver lower supply node Vss-WL.

Abstract: An offset compensated comparator 70 has capacitors 80 and 81 coupled directly between the inputs of a preamplifier 78 and the outputs of a previous stage amplifier 62. The comparator 70 also includes additional capacitors 82 and 83 coupled between the inputs of the preamplifier 78 and reference voltage nodes VREFP and VREFM. Switches 73 and 74 are coupled between the additional capacitors 82 and 83 and the reference voltage nodes VREFP and VREFM. An additional switch 72 is coupled between the additional capacitors 82 and 83. In this configuration, there are no series sampling switches between the previous stage amplifier 62 and the comparator 70. Eliminating the series switches reduces the load seen by the previous stage amplifier 62, which allows the previous stage amplifier 62 to have a faster settling time. This allows the current in the previous stage amplifier 62 to be decreased which reduces the power consumption.

Abstract: A microphone bias current detection circuit includes: a microphone circuit 18; an amplifier 10 having a first output and a second output, the first output is coupled to the microphone circuit 18 for providing a bias current to the microphone circuit 18, the second output provides a sampled current Is proportional to the bias current; a first switch 30 having a first end coupled to the second output of the amplifier 10; a resistor 38 having a first end coupled to a second end of the first switch 30; and a second switch 32 coupled between the first end of the resistor 38 and a reference current source.

Abstract: The electrostatic discharge protection circuit includes: at least two bipolar transistors Q1-Qn coupled in series; a top one Qn of the at least two bipolar transistors coupled to a protected node 10; a bottom one Q1 of the at least two bipolar transistors coupled to a common node 12; at least two resistors R1-Rn coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one R1 of the at least two resistors coupled between a base of the bottom one Q1 of the at least two bipolar transistors and the common node 12.

Abstract: A voltage regulator circuit that provides the current necessary to drive an output driver during transients and maintain low output impedance, while having a much better dropout voltage than a single source follower gain stage includes: an output driver 22; a source follower 34 for controlling the output driver; a localized feedback gain loop coupled to the source follower 34; and an amplifier 24 for controlling the source follower 34.

Abstract: The temperature compensated threshold circuit includes: a positive trip point circuit 60 for providing a positive trip point when an input voltage PSM is higher than a positive supply voltage VCC; a negative trip point circuit 62 for providing a negative trip point when the input voltage PSM is below a negative supply voltage AGND; and a bias circuit 64 for providing to the positive and negative trip point circuits 60 and 62 a first current proportional to absolute temperature and a second current proportional to a base emitter voltage.

Abstract: The amplifier output stage circuit includes: a translinear loop 30 having first and second input nodes Vin+ and Vin−; a first transistor Q7 coupled between a first output node of the translinear loop 30 and a first supply node V+; a first output transistor Q9 coupled between an output node 36 of the circuit and the first supply node V+, and having a base coupled to a base of the first transistor Q7; a second transistor Q10 coupled between a second output node of the translinear loop 30 and a second supply node V−; a second output transistor Q12 coupled between the output node 36 of the circuit and the second supply node V−, and having a base coupled to a base of the second transistor Q10.

Abstract: The low dropout voltage regulator (LDO) circuit with improved power supply rejection ratio includes: a first amplifier 20 having a first input coupled to a reference voltage node Vref; a second amplifier 22 having an input coupled to an output of the first amplifier 20; a pass transistor 24 having a control node coupled to an output of the second amplifier 22; a feedback circuit 26 and 28 having an input coupled to the pass transistor 24 and an output coupled to a second input of the first amplifier 20; an inverting gain stage 36 coupled to the input of the second amplifier 22; and a high pass filter 42, 44, and 38 coupled between a power supply node and a control node of the inverting gain stage 36. The circuit uses the high pass filter 42, 44, and 38 and inverting gain stage 36 to feedforward the power supply ripple into the LDO's control loop which counter-acts the impact of the supply ripple on the output node Vo.

Abstract: A differential line driver with 4X supply voltage swing with a 1:1 transformer, which enhances the loop length for applications such as digital subscriber line includes: a differential circuit having first and second input nodes, first and second output nodes 52 and 54, and a supply voltage node; a transformer 22 having a first coil coupled between the first and second output nodes; and a center tap 50 of the first coil coupled to the supply voltage node. The device also acts as an active impedance termination, which eliminates the series termination resistor in conventional hybrids and thereby saving 6 dB transmit power.

Abstract: The leakage current correction circuit uses a dummy device Mleak to detect leakage current. The dummy device is a scaled down version of the pass element Mpass. A current router is used to either gain up the dummy leakage current and apply it to the output Vout or simply dump the small un-gained current to ground GND.

Abstract: A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes an operational amplifier that is configured in a sample hold operation. The single-ended input is first clamped by a switch (34) to clamp the DC level therein for a given pixel. A switch (38) then samples the reset level onto a sampling capacitor (46), and a switch (42) thereafter samples the video signal onto one plate of a capacitor (50). The lower plates of the capacitors (46) and (50) are then equalized and the other plates thereof connected to the positive and negative inputs of the operational amplifier (68). An offset is provided by a programmable DAC (26) to account for the dark current offset. The output scale is adjusted or mapped by limiting the output between a negative and a positive reference input. The sampling capacitors (46) and (50) can be varied to vary the gain of the amplifier.

Abstract: The opamp with a slew rate booster includes a first high side transistor 23 coupled to a first differential output node OUT−; a second high side transistor 26 coupled to a second differential output node OUT+; a first booster circuit 72 coupled to the control node of the first high side transistor 23; a second booster circuit 70 coupled to the control node of the second high side transistor 26. The opamp exploits the gate control available on the high side transistors 23 and 26. During the charge-discharge differential transient of the load capacitances 58 and 60, the circuit increases the current given by the high side transistor 23 or 26 that is pulling up its output OUT− or OUT+, and reduces by the same amount the current provided at the other output OUT+ or OUT− that is being pulled down by a low side driver 43 or 40. The gate control is accomplished through a simple, symmetrical capacitor-resistor network that implements a basic differentiator.

Abstract: The circuit includes: a transistor 22; and a switch 32 coupled to a backgate of the transistor 22 for switching between a power supply node and current-path node of the transistor 22 to prevent a voltage on the backgate from dropping below the voltage on the current-path node.

Abstract: A method of compensating for nonuniformities in an image sensor includes: providing an image sensing device 20; measuring test pixel signals from the image sensing device 20 during a test mode; determining which test pixel signals are greater than a fixed threshold level ST; and calculating nonuniformity coefficients for the pixels having test pixel signals greater than the fixed threshold level ST.

Abstract: The buffer/driver for low dropout regulators (LDO) uses a feedback amplifier with low output impedance to drive the gate of the pass device MP6 of the regulator. This effectively pushes the gate pole out to a higher frequency. The feedback amplifier is designed for very high slew rate and high bandwidth while running at very low quiescent current. The circuit enhances the LDO performance, stability, and slew rate.

Abstract: The voltage configurable circuit includes: a first transistor 20 having a first end coupled to a first power supply node VCCA; a second transistor 21 having a first end coupled to a second power supply node VCCB and cross-coupled with the first transistor 20; input buffers having input buffer supply nodes coupled to a second end of the first transistor 20 and a second end of the second transistor 21; a first output port A-port coupled to a first one of the input buffers; and a second output port B-port coupled to a second one of the input buffers.

Abstract: The improved Class AB input stage monitors the needs of base current in the slewing transistors 22-25 and supplies that base current with extremely fast and precise feedback loops 90-93. This allows the input stage quiescent current to be very small and gets rid of the non-linearities associated with the lack of base current available to drive the slewing transistors 22-25 in a conventional prior art Class AB input stage. The input stage is a very efficient, low distortion, high small signals and full power bandwidth Class AB input stage.

Abstract: This application describes a method of multiplying numbers represented in multiple-word chains. The multiplication scheme allows for the multiplication of both signed and unsigned numbers of varying lengths. The multiplier block 30 executes a 17-bit by 17-bit two's complement multiply and multiply-accumulate in a single instruction cycle. A 4-bit shift value register with a 4 to 16 bit decoder 35 allows the multiplier to do a 1-16 bit barrel shift on either a 16-bit operand or an (N×16)-bit chain operand.

Abstract: A controller (203) for coupling between a computer bus (20) and one or more units (221, 222) compatible with the bus. The controller comprises a first input (28) for receiving a first reset signal issued from the computer bus, and a second input (30) for receiving a second reset signal. The controller further comprises circuitry (26) for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry (24) for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal.