Abstract: A variable threshold comparator receiving, on an input node, an input signal having a voltage, and providing an output signal on an output node when the voltage of the input signal exceeds a selectable threshold voltage of the comparator. The comparator includes a transistor coupled by way of its source and drain between a power supply and an output node, and having its gate coupled to the input node. Also included are a plurality of pairs of transistors coupled together by a source of a first one of the pair of transistors and drain a drain of a second one of the pair of transistors, and coupled in series between the output node and a ground, a gate of the first one of the transistors coupled to the input node, and a gate of the second one of the transistors coupled to a control signal specific to the second one of the transistors. The threshold voltage of the comparator is selectable by the application of one or more of the control signals to a respective one or more of the second ones of said transistors.

Abstract: A high-speed differential comparator is disclosed. The comparator (100) includes a transconductance device (102 through 112) that receives first and second input voltages (V.sub.IN and -V.sub.IN) and generates first and second currents in response to the first and second input voltages. A first resonant tunneling diode (118) conducts the first current and generates a first output voltage (V.sub.OUT1) at a first output terminal (105) in response to the first current. A second resonant tunneling diode (126) conducts the second current and generates a second output voltage (V.sub.OUT2) at a second output terminal (109) in response to the second current. The comparator responds to input voltages at high speed and may be used for high frequency signal sampling and level determination.

Abstract: An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).

Abstract: A fuse trim circuit includes: a fuse 40; and a logic gate 55 having a first input coupled to the fuse 40 and a second input coupled to a logic code such that the logic code bypasses the fuse 40 to avoid prestressing the fuse 40.

Abstract: A trimming circuit for a gain stage in a pipeline analog-to-digital converter includes an amplification stage (30) having associated therewith on one input thereof a coupling capacitor (38). In parallel with the coupling capacitor is provided a trimming network. The trimming network includes a series configuration of a coupling capacitor and a plurality of trimming capacitors, which trimming capacitors can be disposed in parallel with each other. Each of the trimming capacitors has associated therewith a switch which allows them to be selectively disposed in series with a coupling capacitor (42) and in parallel with each other. This trimming network is connected in parallel with the sampling capacitor (38). The input to the amplifier is isolated from the trimming network with a buffer (62) which is operable to isolate the impedance of the trimming capacitors from the input and from preceding stages.

Abstract: A trimming algorithm for a pipeline A/D converter includes the step of trimming the input sampling capacitor on each of the gain stages for each stage of the pipeline A/D converter. The input thereof is swept from a minimum to a maximum analog voltage and then the integral non-linearity (INL) of the A/D converter determined. The maximum transitions are then examined to determine which transitions are associated with which stage. The transitions for a given stage then constitute the gain error for these stages. The trim values are determined from this gain error and then the trim values incorporated into each of the gain stages.

Abstract: The output control circuit includes: a first high side transistor 56 coupled to an output node 68; a second high side transistor 59 coupled in parallel with the first high side transistor 56; a first transmission gate 72 coupled between a control node of the first high side transistor 56 and a control node of the second high side transistor 59, the first transmission gate 72 is controlled by feedback from the output node 68; a first low side transistor 50 coupled to the output node 68; a second low side transistor 53 coupled in parallel with the first low side transistor 50; a second transmission gate 74 coupled between a control node of the first low side transistor 50 and a control node of the second low side transistor 53, the second transmission gate 74 is controlled by feedback from the output node 68.

Abstract: A driver circuit (12) having a controlled transition rate is provided. The driver circuit (12) includes a first device (56) operable to switch a supply voltage to load. A second device (54) is coupled to an input for the first device (56) in source follower arrangement. A third device (66), coupled to the input for first device (56) and an output for the second device (54), is operable to function as a Miller amplifier in conjunction with the first device (56). A fourth device (152) is coupled to an input of the second device (54). The fourth device (152) is operable to function as a Miller amplifier in conjunction with the first device (56) and the second device (54). A capacitor (68) is coupled between an output for the first device (56) and inputs for the third device (66) and the fourth device (152). The capacitor (68) is operable to function as a Miller capacitor to control transition rates at the output of the first device (56).

Abstract: A gain stage circuit includes a first transistor Q.sub.3 having a control node coupled to a bias node V.sub.B1 ; a second transistor Q.sub.2 having a control node coupled to the bias node V.sub.B1 ; a third transistor Q.sub.1 coupled in series with the second transistor Q.sub.2 and having a control node coupled to an input node V.sub.IN ; a fourth transistor Q.sub.5 matched to the second transistor Q.sub.2 and having a control node coupled to the bias node V.sub.B1 ; a current subtracting circuit 22 coupled to the second and fourth transistors Q.sub.2 and Q.sub.5 ; and a quiet current generator 20 coupled to the current subtracting circuit 22, the current subtracting circuit 22 subtracts a current in the fourth transistor Q.sub.5 from a quiet current in the quiet current generator 20.

Abstract: An analog-to-digital converter test system and method 10 is provided that comprises a digital-to-analog converter system 26. An analog-to-digital converter system 32 is tested using an internal analog input signal 30 generated by the digital-to-analog converter system 26. The digital-to-analog converter system 26 generates the internal analog input signal 30 from an internal digital input signal 24 generated by a programmable data ramp controller 14. The programmable data ramp controller 14 produces a high precision internal digital input signal 24 with predetermined start and stop voltage values 16 repeated over a fixed frequency determined by a programmable divide circuit 18.

Abstract: An image sensing cell includes: a light sensing device 18; a first transistor 10 having a first node coupled to the light sensing device 18; a second transistor 12 having a first node coupled to a second node of the first transistor 10; a third transistor 14 having a control node coupled to the light sensing device 18; and a fourth transistor 16 having a first node coupled to a first node of the third transistor.

Abstract: The invention is a multiplex circuit for outputing two or more signals of different levels to a common output pad where a first output driver (D.sub.h) is powered from a voltage rail having a higher voltage than at least one second output driver (D.sub.1) power by a lower voltage rail. An interface circuit (IFC) and level shift circuit provides two output signals base on a single input signal, one signal being equivalent to the voltage of the higher voltage (V.sub.High) and the other being based on the lower voltage (V.sub.low). PMOS device connected to the output pad has its back gate connected to V.sub.high to prevent leakage current through the PMOS device when the output to the output pad (P.sub.1) is equivalent to V.sub.High.

Abstract: An output stage of an amplifier circuit includes a sinking bipolar circuit 22 for sinking current from an external load 12; a sourcing MOS transistor 14 for sourcing current to the external load 12, a source of the MOS transistor 14 coupled to the sinking bipolar circuit 22 to form a common output node 34; a mirroring MOS transistor 16 having a gate coupled to a gate of the sourcing MOS transistor 14 such that current in the sourcing transistor 14 approximately mirrors current in the mirroring transistor 16; and a current mirror circuit 39 responsive to the mirroring transistor 16 and coupled to control current flow through the sinking bipolar circuit 22.

Abstract: An analog clipping circuit includes: a main amplifier 20; a feedback resistor 26 coupled between a first input of the main amplifier 20 and an output of the main amplifier 20; a first current source 50 coupled in parallel with the feedback resistor 26; a first clipping amplifier 42 coupled to the first current source 50 for controlling the first current source 50, the first clipping amplifier 42 having a first input coupled to an output of the main amplifier 20 and a second input coupled to a first reference node; a second current source 54 coupled in parallel with the feedback resistor 26; and a second clipping amplifier 44 coupled to the second current source 54 for controlling the second current source 54, the second clipping amplifier 44 having a first input coupled to an output of the main amplifier 20 and a second input coupled to a reference node.

Abstract: A video processing system (10) is provided that comprises an image sensor image area (14) that operates to transfer an image to an image memory (18) to be processed by a video processor (16). The exposure length of the image is controlled by an iris controller (24) which comprises a signal decoder (30). An IMAGE CLEAR signal is juxtaposed with an IMAGE TRANSFER signal to set the length of the exposure. The IMAGE CLEAR signal is generated by an iris counter (36) and an iris signal decoder (34). The maximum count used by the iris counter (36) is set using a count length set circuit (38) which receives command signals generated by monitoring the video output.

Abstract: A device for sensing light includes: an active pixel sensor 20; a holding capacitor 67 for storing a pixel signal from the active pixel sensor 20; a scanning switch 71 coupled between the holding capacitor 67 and a sense line 80; a switch control line 76 for turning the switch 71 on and off; a logic gate 90 having a horizontal scan shift register input and a strobe input, the switch control line 76 is an output of the logic gate 90.

Abstract: A pipelined analog-to-digital converter is disclosed having a plurality of sample and hold converter stages, each having an interstage amplifier (28) associated therewith. This is a differential amplifier that is implemented without common-mode feedback. The sample and hold stage operates on a reset phase and a gain/DAC phase, wherein the output of the reconstructive DAC is summed with the input to the amplifier (28). A differential input amplifier (60) has the inputs thereof set to common-mode input voltage with a feedback capacitor biased to a common-mode output bias point. During the gain/DAC phase, the bias input is removed and the feedback capacitor connected across the input/output of the amplifier (60). This effectively establishes the common-mode bias points for use by the amplifier (60) during the gain/DAC phase.

Abstract: A test system (10) is provided that comprises a controller (14) which controls a test head (12) which comprises a pattern sequence controller (16). An integrated circuit (20) is tested through pin cards (18a) through (18n). A test program (32) operating in controller (14) operates to perform both functional and scanning tests on the integrated circuit (20). Scanning tests are provided for set-up, hold, pulse width, and maximum frequency.

Abstract: A resistive element including a P-channel MOS device (101, 401, 402, 608a-608c) having a first and second current carrying electrodes, and a gate. The first current carrying electrode forms a first impedance terminal and the second current carrying electrode forms a second impedance terminal. A bias circuit (103, 104, 105, 106) coupled to the first current carrying electrode and gate of the P-channel MOS device (101, 401, 402, 608a-608c). The bias circuit (103, 104, 105, 106) generates a voltage less than the threshold voltage of the P-channel MOS device (101, 401, 402, 608a-608c).

Abstract: A device (10) identifies a defective object (12) from an image of the object (12) stored as pixel data in a pixel-data memory (52, 54, 56, 58). An inspection-point memory (72, 74, 76, 78) stores inspection-point data for the object (12). The inspection-point data represents inspection points (122, 124, . . . ) that are arranged in circuital (112, 136) and transverse (110) groups, where member inspection points of the circuital groups (112, 136) are also members of different ones of the transverse groups (110). A program memory (84) stores a program, which is executed by a processor (64, 66, 68, 70).