Abstract: An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN3, MN1) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (Vmain). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MNmain) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.

Abstract: A low dropout voltage regulator includes: a first amplifier A1 having a reference voltage node VREF coupled to a first input; a second amplifier A2 having an input coupled to an output of the first amplifier A1; a variable bias current source I1 coupled to the first amplifier A1 and having a control node coupled to an output of the second amplifier A2; a power switch M1 having a control node coupled to the output of the second amplifier A2 and having a first end coupled to a source voltage node VDD; and a feedback circuit R1 and R2 having an input coupled to a second end of the power switch M1 and an output coupled to a second input of the first amplifier A1. The best node in the system that detects the load current level is the output of the second amplifier A2. This signal is used to modulate the bias current I1 of the first amplifier A1 by increasing the bias current when the load current increases and vice versa, which consequently modulates the transconductance of amplifier A1.

Abstract: A method for adjusting the output response of a complementary bipolar operational amplifier includes: providing a first bipolar transistor 14; providing a second bipolar transistor 16 coupled to the first bipolar transistor 14; providing a first current source 26 coupled to a base of the first bipolar transistor 14; providing a second current source 28 coupled to a base of the second bipolar transistor 16; providing a third bipolar transistor 10 coupled to the base of the first bipolar transistor 14; providing a fourth bipolar transistor 12 coupled to the base of the second bipolar transistor 16; providing a first resistor 20 coupled between a base of the third transistor 10 and a common node; providing a second resistor 18 coupled between a base of the fourth transistor 12 and the common node; providing a capacitor 30 coupled to the common node; providing a first input stage current source 24 coupled to the first resistor 20; providing a second input stage current source 22 coupled to the fourth resistor 18;

Abstract: A segmented digital-to-analog converter includes: upper segments 200, 210, and 220; a thermometer decoder 400; a randomizing circuit 410 coupled between the thermometer decoder 400 and the upper segments 200, 210, and 220 for randomizing an output of the thermometer decoder 400; a divider location selector circuit 420 coupled between the randomizing circuit 410 and the upper segments 200, 210, and 220 for choosing a selected segment from the upper segments 200, 210, and 220; and lower segments 225 coupled to the selected segment.

Abstract: A differential receiver circuit includes: a current source 20; a differential pair 22 and 24 coupled to the current source 20; a first transistor 26 coupled to a first branch of the differential pair 22 and 24; a second transistor 28 coupled to a second branch of the differential pair 22 and 24, the first and second transistors 26 and 28 are cross coupled; a third transistor 54 coupled in series with the first transistor 26; a fourth transistor 56 coupled in series with the second transistor 28; a fifth transistor 30 coupled in parallel with the first and third transistors 26 and 54; and a sixth transistor 32 coupled in parallel with the second and fourth transistors 28 and 56.

Abstract: The disclosed invention utilizes a host controller's mechanism to start an isochronous transmit stream on a particular IEEE1394 bus cycle to calculate an offset value from the first time stamped packet that is transmitted in a CIP stream. Packet generating applications indicate the desired offset through the difference of programmed time to start transmitting and the value placed in the first time stamp field. This offset is then applied to the time stamps that are inserted in the remainder of the packets.

Abstract: A transconductance bias circuit includes: a differential pair having a first transistor M14 and a second transistor M15; a resistor R coupled between a gate of the first transistor M14 and a gate of the second transistor M15, the gate of the first transistor M14 is coupled to a reference voltage node; a third transistor M10 coupled to the first transistor M14; a fourth transistor M11 coupled to the second transistor M15; a fifth transistor M8 coupled to the third transistor M10, a gate of the fifth transistor M8 is coupled to the reference voltage node; a sixth transistor M9 coupled to the fourth transistor M11, a gate of the sixth transistor M9 is coupled to the reference voltage node; a current mirror 22 coupled to the fifth and sixth transistors M8 and M9; and a seventh transistor M6 coupled to the fourth transistor M11, a current in the seventh transistor M6 is equal to a current in the resistor R.

Abstract: The two-stage power amplifier includes: a first stage transconductor 60; and a second stage having at least two parallel output branches 57-59 supplying current to an output node 89, each output branch has an input coupled to an output of the first stage transconductor 60.

Abstract: The opamp with common mode feedback bias includes: a first differential pair M1 and M2 having first and second inputs; active load devices M3 and M4 coupled to the first differential pair M1 and M2; a common mode feedback circuit 20 coupled to the active load devices M3 and M4 for controlling the active load devices M3 and M4; a second differential pair M18 and M19 having a first input coupled to the first input of the first differential pair M1 and M2 and a second input coupled to the second input of the first differential pair M1 and M2; and current drivers M22 and M23 having control nodes coupled to the second differential pair M18 and M19 and outputs coupled to the active load devices M3 and M4.

Abstract: Driver circuitry (300) is disclosed, incorporating feedback circuitry (310) inter-coupled with reference circuitry (348) to equalize the voltage level of an output (328) with a reference voltage source (320) in the reference circuitry; where the driver circuitry comprises a first transistor (340) having a first terminal coupled to a voltage source (342), a second terminal coupled to an input (336), and a third terminal coupled to a resistor (344), a second transistor (338) having a first terminal coupled to ground (332), a second terminal coupled to an input (334), and a third terminal coupled to a resistor (346), a third transistor (318) having a first terminal coupled to the output, a second terminal (326) coupled jointly to the resistors, and a third terminal coupled to ground, and a resistor (330) coupling the output to a voltage source (306).

Abstract: A technique for detecting three modes of video input signal and outputting a vertical sync signal based on the input signal. In a first mode, a standard video signal is received and a line counter is used to decode and output the vertical sync. In a second mode where a non-standard signal is received, line counter cannot be used, but a vertical sync is detected and output. In a third mode, no video input signal is received, yet a vertical sync is output in free-running mode so that a blank screen is displayed.

Abstract: An output stage of a complementary bipolar operational amplifier includes: a first bipolar transistor 14; a second bipolar transistor 16 coupled to the first bipolar transistor 14; a third bipolar transistor 10; a fourth bipolar transistor 12; a first resistor 42 coupled between a base of the first bipolar transistor 14 and the third bipolar transistor 10; a second resistor 43 coupled between a base of the second bipolar transistor 16 and the fourth bipolar transistor 12; a first current source 26; a second current source 28; a third resistor 40 coupled between the first current source 26 and the third transistor 10; a fourth resistor 41 coupled between the second current source 28 and the fourth transistor 12; a fifth resistor 19 coupled between a base of the third transistor 10 and a common node; a sixth resistor 18 coupled between a base of the fourth transistor 12 and the common node; a first input stage current source 24 coupled to the base of the third transistor 10; and a second input stage current sou

Abstract: A low-pass filter circuit includes: a first compound transistor device (22) and (24) coupled between an input node (30) and an output node (32); a first transistor (20) coupled to the input node (30), a gate of the first transistor (20) is coupled to a drain of the first transistor (20); a second compound transistor device (36) and (38) coupled between a gate of the first compound transistor device (22) and (24) and the gate of the first transistor (20); a second transistor (34) coupled to the first transistor (20) and having a gate coupled to a gate of the second compound transistor device (36) and (38), the gate of the second transistor (34) is coupled to a drain of the second transistor (34); a current source (26) coupled to the drain of the second transistor (34); a first capacitor (C1) coupled to the output node (32); and a second capacitor (C2) coupled to the gate of the first compound transistor device (22) and (24).

Abstract: A method and apparatus for dithering idle channel tones in delta-sigma converters is provided. In a delta-sigma modulator (10), random dither signal (23) is added before quantizing a signal in order to attenuate the idle channel tones. A random number generator (50) coupled to a digital-to-analog converter (52) with an applied biasing current (54) produces the dither signal (23). The dither signal (23) combines with an input signal at the input of a quantizer (14) in order to randomly change the quantizer output (15) and attenuate idle channel tones.

Abstract: A phase-locked loop is provided which is operable to lock the sampling clock (pixel clock) to the incoming horizontal sync pulse contained within composite video information. Two modes of operation, coarse lock mode and fine lock mode, are used in controlling the phase-locked loop. In the coarse lock mode, coarse corrections are made to a horizontal discrete time oscillator so that a fast lock may be achieve using the fine lock mode. Coarse corrections are based on a normalized sum of weighted pixels collected within a narrow gate window. Lock is achieved when the falling edge is centered within the window.

Abstract: The edge rate controller circuit includes: a first transistor coupled to an output control node; a second transistor coupled to the output control node; an edge rate control driver; a third transistor coupled to the first transistor; a fourth transistor coupled in parallel with the third transistor, the fourth transistor having a control node coupled to the edge rate control driver; a fifth transistor coupled to the second transistor; and a sixth transistor coupled in parallel with the fifth transistor, the sixth transistor having a control node coupled to the edge rate control driver.

Abstract: A skewless differential switching circuit uses skewless switching elements to convert complementary signals with skew into complementary output signals with minimal time skew between the output signals and with equalized rise and fall times of the output signals for minimum harmonic distortion.

Abstract: A controllable current limiting circuit (30) that, when used with a low precision current limiting circuit (10), will limit the current of the output driver transistor M1 to a relatively flat response over a broad temperature range. The current is limited by setting the voltage across a resistance, R1, to a certain value. To overcome temperature induced variations in this voltage, the compensation circuit (20) generates a current that varies with temperature. This current is injected into a terminal of the resistance, R1. This current is generated in such as a manner to ensure that the current flowing in the output driver transistor M1 is relatively constant over a wide temperature range.

Abstract: This document describes a simple modification to the traditional pipelined analog-to-digital converter (ADC) architecture that reduces the signal swing of the inter-stage amplifier by a factor of two. This is a significant advantage when low power supply voltages limit the output range of operational amplifies. The modification requires no additional hardware and produces no additional power consumption.

Abstract: A cross-coupled bandgap circuit (10, 30) generates a stable voltage reference (Vref) at an output port (12, 32). The circuit comprises a cross-coupled current source (14, 34) coupled to a Wilson current mirror (16,36) mirroring a first current through the current source (14,34) to a current sink (18, 38), and also to a voltage generator generating the stable voltage reference. The circuit may be implemented in bi-polar, Bi-CMOS or CMOS circuitry, and is very stable across varying temperatures, varying and noisy operating voltages, between low and high operating voltages, and is stable at low operating currents.