Abstract: The method for making a charge coupled device includes: forming a semiconductor region 24 of a first conductivity type; forming gate regions 28 and 30 overlying and separated from the semiconductor region 24; forming clocked barrier implants 36 and 38 of a second conductivity type in the semiconductor region 24 and aligned to the gate regions 36 and 38; depositing a semiconductor layer 70 overlying and separated from the semiconductor region 24 and the gate regions 28 and 30; removing a portion of the semiconductor layer 70 leaving semiconductor side walls 40 and 42 coupled to the gate regions 28 and 30.

Abstract: A digital to analog conversion system (10) includes a noise shaper (14) and a digital to analog converter (16). The digital to analog converter (16) includes a series of weighted taps (32, 102) with switched capacitor circuitries (42, 106, 108). The digital to analog converter (16) also includes an amplifier (36, 120) having an associated integrating capacitor (62, 122, 130). The switched capacitor circuitries (42, 106, 108) include capacitors (46) that are coupled in parallel to integrating capacitors (62, 122, 130) by common busses (34, 114, 115).

Abstract: A network circuit has a single port device 28 having a high impedance output node 42 when the single port device 28 is powered down; and a multi port device 50 having a bias node 60 coupled to the output node 42.

Abstract: An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.

Abstract: A digital-to-analog converter includes a first array of resistors 10-16 connected in series; a switch matrix 20 coupled to the first array of resistors 10-16; a first variable resistor RTOP coupled to a first end of the first array of resistors 10-16; and a second variable resistor RBOT coupled to a second end of the first array of resistors 10-16, the first variable resistor RTOP and the second variable resistor RBOT having a combined resistance that is a fixed resistance value.

Abstract: A boost regulator circuit includes a rechargeable power supply Vcc, an energy storage component 22 coupled to the rechargeable power supply, a load C.sub.L, and a bi-directional drive means (S1-S6, 20 and 27) for delivering energy from the energy storage component 22 to the load C.sub.L. The bi-directional drive means allows energy transferred to the load to be recovered back to the rechargeable power supply Vcc before switching the load C.sub.L in an opposite direction, thereby effectuating an efficient management of energy and extending the life of the rechargeable power supply Vcc.

Abstract: The current-integrating analog-to-digital converter includes a first charge storage device C.sub.1 ; a second charge storage device C.sub.2 ; an input current I.sub.in coupled to the first charge storage device C.sub.1 for a first time period; a variable reference current I.sub.dac coupled to the second charge storage device C.sub.2 for a second time period; and a comparator 20 for comparing the voltage on the first charge storage device C.sub.1 with the voltage on the second charge storage device C.sub.2.

Abstract: An ESD protection structure which includes, preferably a single semiconductor chip, a forward SCR for coupling across a source of potential and a reverse SCR for coupling across the same source of potential which is non-symmetrical to the forward SCR. The breakdown voltage of the forward SCR is different from the breakdown voltage of the reverse SCR. Each of the SCRs has a separate triggering mechanism. None of the anode, cathode and triggering elements of the forward SCR are common to the reverse SCR. A unidirectional device, preferably a Schottky diode, is disposed in the body of semiconductor material between the forward and reverse SCRs to prevent conduction from the body of semiconductor material when the source of potential across the SCRs is reversed.

Abstract: A phase shifter transmission line includes a semiconductor layer 20; a first conductor region 42 on the semiconductor layer 20; a first doped region 24 and 30 in the semiconductor layer adjacent the first conductor region; and a variable bias voltage coupled to the first conductor region 42 for varying an effective dielectric constant in the transmission line.

Abstract: A low-power differential switching amplifier (200, 210, 220, 230) is provided which utilizes a unique technique of generating interlaced ramps. The interlacing of the ramps causes the ramp discharge time to be effectively zero, which produces exceptionally accurate sawtooth waveforms with virtually no distortion. The timing of the differential switching amplifier circuitry can be synchronized with an external clock. A voltage null point is produced in the differential amplifier where zero voltage at the input of the amplifier produces essentially zero power dissipation within the load, even if the load is low-Q or substantially resistive. Also, by use of a phase balancing technique, residual errors resulting from component mismatches, which would otherwise have imposed power losses upon the load, are nulled out automatically during the operation of the amplifier.

Abstract: A method of making a semiconductor device and the device wherein a chip is provided having plural bond pads thereon. A plurality of adjacent wires is provided, each wire having one end thereof coupled to and extending from one of the bond pads. The other end of each wire is coupled to one of a plurality of lead fingers. A mass of hardenable, flowable adhesive having a viscosity in its flowable state sufficient to enable the adhesive to rest on a the wire until hardened, preferably an epoxy, is disposed on adjacent wires and the adhesive is then hardened. Optionally, some of the adhesive is permitted to be disposed on a surface of the chip and beneath a wire and then hardened.

Abstract: A leadframe (10) for diverting current to an adjacent conductor (55) when a current in the leadframe (10) exceeds a predetermined level includes a first portion (12) for carrying a chip (13) in which an integrated circuit has been constructed. A second portion (20) is connected to receive a current that flows through at least a portion of the integrated circuit. The second portion (20), which may include a bimetallic portion (40,41), is physically deformed by the current and is located to contact the adjacent conductor (55) when the current reaches the predetermined magnitude.

Abstract: The charge coupled device (CCD) charge detection system includes a first CCD register having N non-destructive charge readouts where N is an integer greater than one, and N second CCD registers coupled to the N non-destructive charge readouts where each of the N second CCD registers is coupled to a corresponding one of the N non-destructive charge readouts.

Abstract: A gas detector, preferably for carbon monoxide detection, which includes a light detector(5), a light source (1) for providing a light beam which travels along a light path to the detector and detection chemistry (3) disposed in the light path for altering the light beam responsive to the impingement of a predetermined gas thereon. The detection chemistry includes a plurality of spaced apart members, each disposed in the light path. Each member includes a chemistry responsive to the impingement of the predetermined gas thereon for reversibly altering the light transmissive properties of the detection chemistry. The chemistry of any one of the members can differ from the chemistry of one or more of the other members if more than two members are present. The detection chemistry can, in part, act as a filter to light from the light beam. The detection chemistry is disposed in a gas ambient, the gas ambient being disposed between the spaced apart members.

Abstract: A circuit (10) and method for reducing a tilt of a video picture on a color monitor includes a circuit (30) for providing an output signal for controlling the vertical position of the scanning beam that includes an MOS transistor (60) having substantially zero current flow in its gate element, and connected to control the magnitude of the output drive signal. In a preferred embodiment, a LinBiCMOS semiconductor manufacturing process is employed to fabricate a plurality of bipolar transistors connected to provide a control voltage on the gate of the MOS transistor (60), which may conveniently be an NMOS device. The bipolar transistors may be connected to form a translinear cell (11) connected to receive a signal (17) related to a horizontal synchronizing signal and to provide a voltage output to the gate of the MOS transistor (60) in response thereto.

Abstract: The invention is to a method of placing symbolization on a heat spreader, used in conjunction with the semiconductor package, through the use of a low powered laser beam. The beam is scanned over the package surface at a preset intensity and for a desired time to change the surface texture of the heat spreader, and to change the reflectivity of the scanned area.

Abstract: A semiconductor device includes conductor regions 24 and 26 on a layer of the semiconductor device; a first insulator layer 28 over and between the conductor regions 24 and 26; polyimide regions 30, 32, and 34 over the first insulator layer 28 in gaps between the conductor regions 24 and 26; and a second insulator layer 38 over the first insulator layer 28 and over the polyimide regions 30, 32, and 34. A surface of the second insulator layer 38 is substantially planar.

Abstract: A low voltage drop out circuit (10) has a voltage regulating transistor (13) between a supply voltage (12) and an output terminal (28). An active feedback loop controls the voltage regulating transistor (13) according to a magnitude of the supply voltage (12) to control the voltage on the output terminal (28). A reference voltage source (25) produces a reference voltage, and a switch, which may be a second transistor (45) of similar type than the voltage regulating transistor (13), is connected in parallel with the voltage regulating transistor (13). A comparing circuit (42) detects when the supply voltage (12) falls below the reference voltage (25) to operate the second transistor (45), which may be sized to be much larger than the voltage regulating transistor (13) to effectively short across the voltage regulating transistor (13) when the supply voltage (12) falls below a predetermined level.

Abstract: The voltage regulator circuit contains a MOS transistor 12 connected between a voltage supply line 22 and an output line 30. The MOS transistor 12 provides a stable voltage on the output line 30 independent of voltage transients on the voltage supply line 22 and independent of current transients on the output line 30. An amplifier 14 coupled to the MOS transistor 12 controls the response of the MOS transistor 12. Feedback circuitry connected between the output line 30 and the amplifier 14 provides feedback to the amplifier 14. A voltage source 16 provides the reference for amplifier 14.

Abstract: The apparatus (10) includes a flat transparent surface (30) and two angled mirrored surfaces (32, 34) which direct the light to the ball grid array (12) on the underside of the semiconductor device (14) positioned on the flat transparent surface (30) in a live bug mode. The mirrored surfaces (32, 34) also direct the image of the ball grid array (12) to an image capturer (18) such as a video camera. The focus information of each solder ball is used to determine the distance to the tips of each solder ball. The coplanarity of the ball grid array can then be determined and/or verified.