Patents Represented by Attorney Albert P. Cefalo
  • Patent number: 5446622
    Abstract: A PC board cartridge for a computer terminal, the cartridge including a casing for holding a PC board with a connector mounted thereon. A handle is pivotally mounted on the casing along an axis extending in a plane that extends perpendicular to a major surface of the board and intersects the board at the connector. The PC board cartridge preserves electrical and mechanical connector integrity by providing a handle for removal which applies generally equal forces across the connector during removal. In addition, no additional hardware is required for assembly, installation, or removal of the cartridge.
    Type: Grant
    Filed: August 6, 1993
    Date of Patent: August 29, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Christian C. Landry, Tzong-Bin Tsai, Bradford G. Chapin, Jin-Bond Lou
  • Patent number: 5418973
    Abstract: A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The execution unit generates load/store memory addresses for vector load/store instructions. The load/store addresses are translated by the memory management unit, and stored in a write buffer that is also used for buffering scalar write addresses and write data. The cache controller coordinates-loads and stores between the vector processor and the shared cache with scalar reads and writes to the cache. Preferably the cache controller permits scalar reads to precede scalar writes and vector load/stores by checking for conflicts with scalar writes and vector load/stores in the write queue, and also permits vector load/stores to precede vector operates by checking for conflicts with vector operate information stored in a vector register scoreboard.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: May 23, 1995
    Assignee: Digital Equipment Corporation
    Inventors: James P. Ellis, Era Nangia, Nital Patwa, Bhavin Shah, Gilbert M. Wolrich
  • Patent number: 5414524
    Abstract: A clipping circuit and method for selecting a rectangular region of interest from an image comprised of scan lines of pixels. The circuit stores the lengths of the portions of scan lines inside and outside the region of interest. A data decompression unit presents image data to the clipping circuit in scan line order. When pixels from the portion of a scan line within the region of interest are processed, the circuit passes the pixels through the system. When pixels outside the region are processed, they are blocked from further processing by the circuit.
    Type: Grant
    Filed: January 14, 1992
    Date of Patent: May 9, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Christopher J. Payson, Timothy M. Hellman
  • Patent number: 5410448
    Abstract: A parallel air flow system which automatically maintains proper coolant flow regardless of the number of circuit boards installed in an enclosure. The enclosure is constructed such that air flow path through any one slot does not affect the air flow through any other slot. Proper air flow through the entire system is maintained by an air flow sensor disposed in an air flow path having a known air flow resistance. This sensor controls the speed of an air-mover in order to maintain a constant predetermined air flow through the known resistance, in such a way that a constant static air pressure is maintained at each slot. Baffle modules are preferably inserted into the enclosure to prevent air flow into any empty slots, to reduce the total air volume necessary to achieve the predetermined static pressure, thereby reducing the audible noise generated by the air-mover.
    Type: Grant
    Filed: August 10, 1993
    Date of Patent: April 25, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Charles R. Barker, III, Richard E. Olson
  • Patent number: 5407850
    Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of positive charge within the gate to correspond to the positive polarity formed in the substrate by ion implantation for threshold voltage control. A positive charge layer is formed by furnishing sulfur ions on the substrate before growth of an oxide to form a portion of the gate oxide. The sulfur will form a charge layer on the surface of the oxide, and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the positive charge layer in the same.
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: April 18, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Brian S. Doyle, Ara Philipossian
  • Patent number: 5406147
    Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.
    Type: Grant
    Filed: June 18, 1993
    Date of Patent: April 11, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Joseph P. Coyle, William B. Gist
  • Patent number: 5394347
    Abstract: A method for generating test programs for an implementation of a specification that has been modeled as an extended finite state machine (EFSM), the EFSM including vertices and transitions, where the transitions represent functions to be performed by the implementation, including predicates and actions such as variable assignments. The method includes traversing the EFSM in a depth-first manner from a root model start state to a root model exit state, through intermediate vertices which may be normal states or models. Models include further vertices and transitions, and may be called as submodels or as go-to models, where a go-to model includes an EFSM exit state. The EFSM may be traversed exhaustively, such that all possible paths are traversed, or in a partial transition coverage mode, where a user-defined subset of the possible paths are traversed.
    Type: Grant
    Filed: July 29, 1993
    Date of Patent: February 28, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Ronald A. Kita, Sylvia C. Tremblay, Thomas M. Lynch
  • Patent number: 5390299
    Abstract: In a network adapter for a host computer, the data occupancy level of a buffer memory used to store network packets is monitored, and the occupancy level is reported to the host. The buffer memory is organized as a plurality of fixed-size pages. A memory controller uses an allocation counter to track the number of pages available to store incoming data packets, and the value of the allocation counter is compared with a programmable threshold. A data word accompanies each packet delivered to the host to indicate whether the allocation count exceeds the threshold. When the buffer memory has insufficient free space to store an incoming packet, the packet is discarded. The network adapter keeps a count of the number of discarded packets. An adapter manager microprocessor, which is part of the network adapter, reports the count to the host computer on request. The adapter manager also reports the value of the allocation count and other important network adapter variables to the host computer.
    Type: Grant
    Filed: December 27, 1991
    Date of Patent: February 14, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Satish L. Rege, Kadangode K. Ramakrishnan, David A. Gagne
  • Patent number: 5390327
    Abstract: In a storage system having a plurality of disks arranged in a RAID-4 or RAID-5 array, a method of improving the performance and reliability of the array in the absence of a member. The method re-organizes the array into the equivalent of a higher performance and reliability RAID-0 organization while allowing concurrent high performance application access to the array and includes a deliberate reorganization activity concurrent with application access. The method also restores the RAID-4 or RAID-5 organization subsequent to the failure of a member using a replacement member while continuing to allow concurrent high performance application access to the array. In order to perform this reorganization on-line state information is maintained for each parity block, each data block and the array itself. A recently removed disk may be reinserted using an expedited replacement process.
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: February 14, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Clark E. Lubbers, David W. Thiel
  • Patent number: 5389757
    Abstract: A key switch and resilient actuator assembly that includes an electrical switching region and a hollow open ended actuator cover of elastomeric material overlaying the switching region with the open end of the actuator cover in surrounding relationship with the switching region. The actuator cover includes a first wall portion shaped to provide substantially linear resistive force during compression displacement of the cover toward the switching region and to provide substantially linear restoring force during expansion displacement of the actuator cover away from the switching region. The actuator cover further includes a second wall portion shaped to undergo buckling toward the switching region at a predetermined compression displacement and to undergo unbuckling away from the switching region at a predetermined expansion displacement that is smaller in total displacement than the predetermined compression displacement.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: February 14, 1995
    Assignee: Digital Equipment Corporation
    Inventor: Ernest G. Souliere
  • Patent number: 5388224
    Abstract: A computer system including a plurality of processors and a bus coupling the processors to one another via respective bus interfaces. The bus includes a plurality of slots for coupling the interfaces to the bus. Each interface includes an ID register coupled to the interface device, the ID register containing identification information unique to the slot of the bus used to couple the respective interface to the bus. The interface device is responsive to an address command cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another slot of the bus. A processor requiring identification of the corresponding slot causes the respective interface to initiate a READ bus transaction directed to another slot of the bus.
    Type: Grant
    Filed: April 24, 1992
    Date of Patent: February 7, 1995
    Assignee: Digital Equipment Corporation
    Inventor: Barry A. Maskas
  • Patent number: 5388099
    Abstract: A backplane wiring scheme is provided for use in a hub of a packet data communications system. Line cards are connected to the backplane wiring arrangement in the hub, where each line card is a coupling to a network segment, a station or a to a bridge to other stations or segments. The connection is usually in either a ring or a bus topology, and increased flexibility, reduced power consumption, and easier implementation are provided by a unique wiring scheme. Each line card has a number of receive ports (e.g., N-1) and has two transmit ports, the transmit ports including a transmit-left port and a transmit-right port. The receive ports and transmit ports are arranged in a regular linear pattern on an edge of each of said line cards.
    Type: Grant
    Filed: October 22, 1992
    Date of Patent: February 7, 1995
    Assignee: Digital Equipment Corporation
    Inventor: Nigel T. Poole
  • Patent number: 5388247
    Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in memory accesses used to fill the stream buffer. The system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. The system also prevents the unnecessary prefetching of data by preventing certain CPU requests from being used to detect streams. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access.
    Type: Grant
    Filed: February 16, 1994
    Date of Patent: February 7, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Paul M. Goodwin, Kurt M. Thaller, Barry A. Maskas
  • Patent number: 5387530
    Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of charge within the gate oxide, which layer has a polarity corresponding to that of the ion implantation for threshold voltage control. A negative charge layer is formed by furnishing trace amounts of aluminum on the substrate before growth of an oxide to form a portion of the gate oxide. The aluminum will form a charge layer on the surface of the oxide and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the charge layer in the same.
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: February 7, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Brian S. Doyle, Ara Philipossian
  • Patent number: 5386143
    Abstract: Integrated circuit package (10) includes a substrate (12) comprising a porous ceramic body (14). A non-porous covering (16) provides a hermetic seal around the porous ceramic body (14). A heat transfer liquid (18) partially fills pores (30) of the porous ceramic body (14). A plurality of integrated circuit chips (20) are attached to a surface of the substrate (12) by epoxy, solder or other bonds (22). On an opposite surface, the substrate (12) includes a plurality of heat transfer fins (24). In use, the heat transfer liquid (18) in the ceramic body (14) is vaporized to fill the balance of the pores (30) and condensed in a continuous heat pipe cycle to remove heat from the integrated circuits (20) mounted on the substrate.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: January 31, 1995
    Assignee: Digital Equipment Corporation
    Inventor: John S. Fitch
  • Patent number: 5384779
    Abstract: An apparatus for controlling configuration of a communications network, the network including a trunk having trunk segments and lobe circuits for connecting to nodes. The apparatus comprises an internal trunk circuit, and a plurality of ports. The ports include a lobe port for connecting to a lobe circuit, an input port for connecting to an input trunk segment, and an output port for connecting to an output trunk segment. State machines are provided for sensing the communications signal at a corresponding one of each of said plurality of ports. Each state machines is transitioned by a set of transition rules which include inputs from the sensed communications signals. The state machines enable the connection and disconnection of said ports to said internal trunk.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: January 24, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Michael W. Patrick, James A. Daly
  • Patent number: 5382831
    Abstract: For enhanced resistance to electromigration failure, a thin metal film interconnect on an integrated circuit chip should use multiple parallel minimum-width lines when the minimum linewidth is less than one and one-half times the mean grain size of the metal film. When the interconnect is longer than a certain predetermined length, then the multiple lines of the interconnect should have intermediate interconnections or bridges between neighboring ones of the multiple lines. When the interconnect is many times longer than the predetermined length, then the bridges define slots between the neighboring lines, and the slots should have a length of about the predetermined length. When the interconnect is many times longer than the predetermined length and the interconnect has more than two parallel lines, then the slots on one side of a parallel line should be staggered or offset with respect to the slots on the other side of the parallel line.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: January 17, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Eugenia M. Atakov, John J. Clement, Brian C. Lee
  • Patent number: 5383096
    Abstract: An apparatus for increasing the number of electrical I/O ports on an existing computer system chassis, while maintaining the RF shield of the chassis and without changing the design of the existing chassis, by the use of an I/O expansion box. The I/O expansion box comprises a bottom and a cover. The bottom has a base plate with openings for cables from the computer chassis to pass therethrough and has lips at the openings. The lips extend outwardly away from the recess and are used to attach the base plate to the chassis at its I/O port openings. The cover has a top with openings therein for the attachment of electrical cable connectors that are attached to the cables from the computer chassis. The number of openings in the top of the cover are greater than the number of openings in the base plate of the bottom.
    Type: Grant
    Filed: May 3, 1993
    Date of Patent: January 17, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Matthew C. Benson, Laurence M. Mazzone
  • Patent number: 5381052
    Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.
    Type: Grant
    Filed: July 6, 1993
    Date of Patent: January 10, 1995
    Assignee: Digital Equipment Corporation
    Inventor: Ravindra N. Kolte
  • Patent number: 5381146
    Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.
    Type: Grant
    Filed: July 6, 1993
    Date of Patent: January 10, 1995
    Assignee: Digital Equipment Corporation
    Inventor: Ravindra N. Kolte