Abstract: A compiler includes a register allocation method making use of the concept of assigning temporary items to lifetime holes if such holes exist that are suitable. The compiler includes a front end for converting the input code to an intermediate representation, then this input representation is traversed to identify all of the temporary items, and to find all of the holes in the temporary items. Lists are maintained of the identified temporaries and holes. Register allocation then includes assigning temporaries to registers so long as there are free registers, and if holes are available in already-assigned temporaries then these holes are used in assigning registers. After all the available registers and holes are used, remaining temporaries are unallocated and thus represent memory references.

Abstract: A method and apparatus for providing asynchronous communication between at least one central processing unit (CPU) and at least one associated memory unit with specially programmed timing signals to latch, select and transmit data between them.

Abstract: A communications system having a plurality of nodes is disclosed, including a reliable method and apparatus for collision detection. Each node includes a primary and a secondary collision detection circuit, and a unique value that is included in each transmission. The unique values of the nodes are designed so that collisions not detected by the primary collision detection circuit are reliably detected by the secondary collision detection circuit, even in the presence of logic delays within the circuits, and propagation delays between nodes.

Abstract: A thin film two-pole inductive magnetic head for a computer disk drive assembly. The head comprises a substrate, a first pole formed over the substrate, a gap layer formed over the first pole and a second pole formed over the gap layer. The first and second poles have their distal ends coupled together in a yoke region, while their proximal ends terminate at their tips in an air bearing surface. A leading surface of the first pole extends back toward the yoke region at an acute angle to the air bearing surface. The head reduces the amplitude and high frequency content of secondary pulses in a readback waveform so as to ease the task of electronically isolating the main pulses for downstream processing of the read data.

Abstract: A storage assembly for mounting "0" to "N" storage devices to a computer or electronic system.

Abstract: Disclosed is an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, which has a greater or equal number of input levels. Generally, neither the number of input nor output levels need to be a power of two. The present invention is implemented in a number of different embodiments. These embodiments generally rely upon an image processor which, depending on the particular implementation, includes memory devices and an adder, a comparator, or a bit shifter. Additional embodiments use an image adjustment system to refine the raw input levels of the input device, in order to create an improved output image. Also, the particular embodiments of the image processors can be used in connection with imaging systems having hi-tonal, monochromatic, or color input and output devices.

Abstract: A method of and an apparatus for the electroplating of material onto substrates, such as computer memory disks, by use of a plating cell comprising cathodes, anodes, passive shields, filters, an oscillation system and an electrical power supply. Anodes and magnets are attached to the inside side walls of the plating cell. The magnets have a coating of an electrically nonconducting material covering it. Shields, each having a filter attached to it, are also fixed to the inside side walls. A pallet, having openings for holding disk substrates during electroplating, is placed between the shields in the plating cell. The disk substrates function as cathodes during electrolytic plating. The anodes and cathodes when electrically energized results in deposition of desired material, having uniform thickness, across the entire surface area of the substrate.

Abstract: Disclosed is an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, which has a greater or equal number of input levels. Generally, neither the number of input nor output levels need to be a power of two. The present invention is implemented in a number of different embodiments. These embodiments generally rely upon an image processor which, depending on the particular implementation, includes memory devices and an adder, a comparator, or a bit shifter. Additional embodiments use an image adjustment system to refine the raw input levels of the input device, in order to create an improved output image. Also, the particular embodiments of the image processors can be used in connection with imaging systems having bi-tonal, monochromatic, or color input and output devices.

Abstract: A station transmits a sequence of one or more frames on a token ring, keeping count of the frames transmitted. At the end of the transmitted frame the station originates onto the ring one or more coded marker frames and finally transmits a token. After the station transmission is begun, the station strips from the ring all the frames it receives, decrementing its count for each properly stripped frame, until either its count is reduced to zero or one of its marker frames is detected.

Abstract: A thin film magnetic head, and process for making the same, features a thin film magnetic transducer formed from multiple layers of film and having a magnetic yoke interacting with an electrical coil. The yoke has multiple magnetic flux circuits, deposited on multiple layers of film, encircling the center of the transducer and connected together by proximal and distal vias. A coil has multiple turns intertwined with the yoke, passing between the distal and proximal vias so that the distal vias are exterior to the coil and the proximal Vias are interior to the coil, to provide at least four magnetic flux interactions between the coil and the yoke. In preferred embodiments at least one layer of the film is deposited with at least two pole pieces having different easy axis orientations.

Abstract: A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.

Abstract: A surface selection mechanism is disclosed for an optical disk storage system. The mechanism comprises a linearly movable slider having a first and second mirror mounted side by side thereon. The first and second mirrors have reflective mirrors positioned at right angles with respect to each other. The mechanism includes apparatus for positioning the slider so that either the first or second mirror is positioned at the optical axis of a light beam to direct the light beam at either a first or a second recording surface of a double sided disc.

Abstract: A reliable diagnostic system for running power-up diagnostics, displaying power-up diagnostic results, and retaining a power system status history. First, a method of testing a processor module in a computer system is provided. A processor including a serial port reads processor module diagnostic test instructions from a PROM in a serial line controller through the serial port by way of a serial bus in response to power-up reset instructions. Next, a reliable means for connecting a serial control bus modules is provided. Accordingly, backplane connectors are provide including wide signal conducting elements having multiple solder connection points to the modules and backplane. The serial control bus is electrically connected to each module through the multiple connection points of these signal conducting elements. Also, an apparatus and method for indicating module failures in a computer system is provided.

Abstract: A duplicate address condition in a computer network may be detected by a station of the type for attachment to a computer communications network, the network capable of maintaining communications among a plurality of stations, the station having means for receiving a frame, the frame having a source address field and a frame control field; means for maintaining an individual address of the station; means for maintaining a source address list of address, the source address list not containing the individual address; means for determining that a contents of the source address field in the frame matches at least one address in the source address list; means for determining that the frame control field of the frame has a predetermined contents; and, means, responsive to the source address of the frame matching at least one address in the source address list and the frame control field of the frame having the predetermined value, for setting an indicator that a duplicate address condition exists.

Abstract: A computer-aided software development system includes programs to implement edit, compile, link and run sequences, all from memory, at very high speed. The compiler operates on an incremental basis, line-by-line, so if only one line is changed in an edit session, then only that line need be recompiled if no other code is affected. Dependency analysis is performed incrementally, without requiring the user to enter dependencies. Scanning is also done incrementally, and the resulting token list saved in memory to be used again where no changes are made. All of the linking tables are saved in memory so there is no need to generate link tables for increments of code where no changes in links are needed. The parser is able to skip lines or blocks of lines of source code which haven't been changed.

Abstract: A protocol analysis system is provided with data specifying the defined states of processes participating in a distributed computation. State transitions between states are specified as being enabled by (A) receiving a message, (B) unreliably sending a message, or (C) performing an external action such as reliably sending a message. The specification data also identifies process states known to be final states, and all other states are initially denoted as intermediate states. The protocol analysis system determines if any intermediate states can be re-categorized as final states. Then it determines if any state transitions initially identified as unreliable send operations must be treated as derived external actions, and thus made reliable. Thirdly, for each derived external action, the states of the affected application process must be re-evaluated so as to determine if derived final states need to be converted into intermediate states.

Abstract: Use of a multicast address in a LAN, where the LAN does not support an adequate multicast address space, is implemented. An apparatus is provided for delivering a multicast address to a station on a local area network, where the local area network does not support the multicast address. The frame is transmitted onto the local area network, where the frame has: a predetermined field containing a reference to the multicast address; an indicator, the indicator capable of being interpreted by a receiving station to mean that the multicast address may be recovered from the frame by parsing the frame; and an applications program may be executed in response to the multicast address. Also, the apparatus may have a receiving station capable of receiving the frame, and an applications program may be executed in the receiving station in response to the multicast address.

Abstract: A residue buffer, for temporary storage of portions of transmissions from a CPU to a graphics processor. Graphics commands are transmitted, in transmission units of uniform size, from a processor unit to an address generator, which processes the commands. The portion of the transmission unit not immediately usable by the graphics processor is stored in the residue buffer.