Patents Represented by Attorney Albert P. Cefalo
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Patent number: 5321724Abstract: A line driver is coupled by a pair of signal lines to a receiver. Preprocessing circuitry, for processing signals arriving on the pair of signal lines at the receiver, includes regulating circuitry for regulating the voltage between the signal lines between predetetermined limits and thereby modifying the sensitivity of the system to compensate for changes in line conditions and reject interference when the line driver is powered down. The regulating means includes: bias circuitry, for putting a bias on the signal passing through to the receiver, so as to hold the receiver input away from the triggering voltage level so that it is not triggered by noise; and bias limiting circuitry, responsive to signals from the driver so as to limit or reduce the effective bias, so that the sensitivity of the system to true signals from the driver is not reduced below a desired level. A resistor is connected between the two signal lines.Type: GrantFiled: October 23, 1992Date of Patent: June 14, 1994Assignee: Digital Equipment CorporationInventors: Brian Long, Michael J. Hynes
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Patent number: 5321373Abstract: An electromagnetic noise filter has a plurality of U-shaped wires passing through a ferrite core. Some of the wires are singly fitted in throughholes, whereas other wires are commonly fitted in throughholes. The wires can be interconnected to provide for impedance to both differential-mode and common-mode noise.Type: GrantFiled: July 2, 1993Date of Patent: June 14, 1994Assignee: Digital Equipment CorporationInventors: Boris I. Shusterman, Robert Curtis
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Patent number: 5321703Abstract: A method of data recovery in systems employing error-correction coding techniques is described. The technique may be used, for example, in conjunction with a data storage device or a data communications network. Several trials of accessing or transmitting the ECC-protected data are performed. The data from each trial is decoded, and is also saved. If none of the trials results in the successful decoding of the data, then a reconstruction function is employed to create a reconstructed version of the data from the sequence of data created by the trials. One method of reconstruction involves majority voting on a symbol-by-symbol basis. The reconstructed data created that way is then decoded in the same fashion as for each trial. A more powerful reconstruction function employs a threshold to determine whether each voted-on symbol is sufficiently "reliable". If not, it is marked as an erasure.Type: GrantFiled: March 13, 1992Date of Patent: June 14, 1994Assignee: Digital Equipment CorporationInventor: Lih-Jyh Weng
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Patent number: 5319512Abstract: A head positioning device in a disc storage system is constructed of individual flat components, particularly of ceramics which are individually ground or lapped to their final dimensions before connected with one another. Individually, the flat components comprise positioning arms, spacers and carrier arms. Head carriers are fixed to the free ends of the head positioning arms by means of pins of memory metal permitting removal of the head carriers. Read/write heads for recording and retrieving information are fixed to the removable head carriers. The carrier arms are arranged for receiving positional magnetic units. The spacers are arranged between the positioning arms and the carrier arms.Type: GrantFiled: September 13, 1993Date of Patent: June 7, 1994Inventor: Hans Grapenthin
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Patent number: 5319785Abstract: A method and apparatus for polling a status register selectively delays the returning of status data in the status register. Prior to polling, a match register is loaded via a system bus with a desired status. Status data is presented to the system bus when the status data is the same as the desired status. The features of the invention also permit the masking of selective bits of the status register during the comparison of the status data with the desired status. A mode register selectively inhibits the delayed presentation, and a timer ensures that status data is presented to the system bus within a predetermined interval even if the status data is not the same as the desired status.Type: GrantFiled: October 16, 1992Date of Patent: June 7, 1994Assignee: Digital Equipment CorporationInventor: Kurt M. Thaller
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Patent number: 5316965Abstract: An improved process for planarizing an isolation barrier in the fabrication of a semiconductor chip involves reducing the etch rate of the field oxide independently of the sacrificial oxide layer. The field oxide layer is implanted with nitrogen ions and then thermally annealed resulting in a hardened and densified field oxide. In subsequent operations, a sacrificial oxide layer is formed on the semiconductor top surface by thermal oxidation. Upon etching with HF, the etch rate of the hardened field oxide is significantly reduced relative to untreated field oxide. Thus, the exposed hardened field oxide is etched at about the same rate as the sacrificial oxide layer. In the example given, the etch rate of untreated densified TEOS field oxide in 10:1 HF is 6.90 .ANG./sec, while the etch rate of TEOS field oxide hardened according to the processes of this invention is 5.90 .ANG./sec. After planarization using the hardened field oxide, depressions in the isolation barrier are eliminated.Type: GrantFiled: July 29, 1993Date of Patent: May 31, 1994Assignee: Digital Equipment CorporationInventors: Ara Philipossian, Hamid R. Soleimani, Brian S. Doyle
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Patent number: 5316642Abstract: A method of and an apparatus for the electroplating of material onto substrates, such as computer memory disks, by use of a plating cell comprising cathodes, anodes, passive shields, filters, an oscillation system and an electrical power supply. Anodes and magnets are attached to the inside side walls of the plating cell. The magnets have a coating of an electrically non-conducting material covering it. Shields, each having a filter attached to it, are also fixed to the inside side walls. A pallet, having openings for holding disk substrates during electroplating, is placed between the shields in the plating cell. The disk substrates function as cathodes during electrolytic plating. The anodes and cathodes when electrically energized results in deposition of desired material, having uniform thickness, across the entire surface area of the substrate.Type: GrantFiled: April 22, 1993Date of Patent: May 31, 1994Assignee: Digital Equipment CorporationInventors: David J. Young, Jr., Scott L. Randall, Scott D. Shaw, Andrew F. Wylde
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Patent number: 5315698Abstract: In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. A separate translator provides conversion from generated virtual addresses to physical addresses. The address generator formulates addresses as a function of distance from the origin of desired destination area in destination memory to the requested position in the destination area. A plurality of drawing graphics commands specify different raster drawing operations. A plurality of context graphics commands is used to define a desired context in which drawing graphics commands operate. The defined context includes destination location for resulting data, type and plane depth of graphics operations, foreground and/or background color of resulting data. Different parts of the context are changeable/redefinable independently of the other parts. The graphics commands have a format of multiple fields. Different fields specify different parameters.Type: GrantFiled: August 21, 1991Date of Patent: May 24, 1994Assignee: Digital Equipment CorporationInventors: Colyn Case, Kim Meinerth, John Irwin, Blaise Fanning
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Patent number: 5315480Abstract: A system for cooling an electronic module in a computer system. In one embodiment of the invention, predetermined areas of the module, such as those exposed parts that carry electrical currents are covered with an conformable, electrically insulating layer. Thereafter, a second conformable, thermally conductive layer is formed on the first layer. In addition, surface expanding elements may be arranged on the first layer near devices particularly sensitive to heat before the application of the second layer.Type: GrantFiled: April 28, 1993Date of Patent: May 24, 1994Assignee: Digital Equipment CorporationInventors: Victor M. Samarov, Ralph I. Larson, Jr., George A. Doumani
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Patent number: 5315602Abstract: A system for reducing the number of I/O requests required to write data to an redundant array of inexpensive disks (RAID) of a computer system including a host central processor unit and a memory buffer cache. The system includes determinations for writing new data stored in the cache to the disk drives, as stripes, using the least number of I/O requests possible. The system uses the best of two alternative techniques in which the parity for the stripe can be generated. A first procedure determines the number of I/O requests that would be required to generate the parity data from the entire stripe including the new data to be written to the disk drives. A second procedure determines the number of I/O requests that would be required to generate the parity data from the new data to be written to the disk drives and the old parity data of the stripe.Type: GrantFiled: August 12, 1992Date of Patent: May 24, 1994Assignee: Digital Equipment CorporationInventors: Eric S. Noya, Randy M. Arnott, Mitchell N. Rosich
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Patent number: 5313641Abstract: An arbitration mechanism for controlling a coupling order between a number of resources and a number of requesters having a number of requests processing units, one associated with each one of the requesters, for receiving a resource type request signal from the associated requester, a number of grant processing units, one associated with each one of the resources, for monitoring a busy status signal from said associated resource, a common broadcast medium coupled to the number of request processing units and the grant processing units, and an arbiter for granting access to said common broadcast medium to one of the request processing units and the grant processing units using the common broadcast medium to control the coupling order between the requesters and the resources in a first come, first served manner.Type: GrantFiled: January 6, 1993Date of Patent: May 17, 1994Assignee: Digital Equipment CorporationInventors: Robert J. Simcoe, Robert E. Thomas
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Patent number: 5313369Abstract: A simple, low cost, reduced tolerance interconnect enclosure in which a blind m A siVpV:interconnect between modules and the backplane may be guaranteed without the need for assembly fixtures or floating connectors, and a method of manufacturing the enclosure. The enclosure includes two matching enclosure sections for holding a backplane. The backplane has spaced apart recesses on opposing edges. Each enclosure section includes alignment protrusions spaced apart to engage the backplane recesses. These protrusions have curved apex regions and a height greater than the depth of the backplane recesses. Means for latching the enclosure sections together are provided, and the enclosure sections are dimensioned such that when the enclosure sections are closed around the backplane, the protrusions from the enclosure sections are urged against the recesses on the backplane.Type: GrantFiled: November 3, 1992Date of Patent: May 17, 1994Assignee: Digital Equipment CorporationInventors: Mark S. Lewis, Lori A. Treseder, Reuben Martinez, Ralph M. Tusler
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Patent number: 5313581Abstract: A communication client is connected to multiple display servers. When a client of one of the display servers issues a communication, the communication client notes the communication in the display server coupled to the client and relays the communication to the other servers for use by clients of the other servers.Type: GrantFiled: September 28, 1993Date of Patent: May 17, 1994Assignee: Digital Equipment CorporationInventors: Dennis G. Giokas, Andrew T. Leskowitz
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Patent number: 5313595Abstract: An automatic termination system for an end terminated bus especially useful with the SCSI bus. When utilized with a computer device, for example, a storage subsystem, configuration or reconfiguration of the bus can be automatically effectuated without concerns for inappropriate signal termination of the bus. The invention comprises a circuit which determines if any additional devices have been coupled to the bus and enables an active terminator chip if none is detected. Should another device be coupled onto the bus, the active terminator chip is automatically disabled.Type: GrantFiled: December 10, 1992Date of Patent: May 17, 1994Assignee: Digital Equipment CorporationInventors: Mark S. Lewis, Ronald R. Ravey
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Patent number: 5309294Abstract: The present invention is directed to a circuit and method for nullifying a drop in the voltage across an MR head caused a parasitic cable resistance. The invention uses local modeling of the cable resistance in order to generate a nulling voltage, equal in magnitude to the voltage across the cable resistance. The magnitude of the nulling voltage is adjusted as the resistance of the MR head varies within a population of heads. The nulling voltage is added to the bias voltage, in order to negate the effect of the cable resistance.Type: GrantFiled: September 8, 1992Date of Patent: May 3, 1994Assignee: Rocky Mountain Magnetics, Inc.Inventor: Dennis J. Cahalan
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Patent number: 5309437Abstract: A device and related method for coupling segments of an extended local area network (LAN) in such a way that message traffic employing inter-network protocols such as TCP/IP will be handled without the difficulties usually associated with bridges, and without the complexity and expense of full IP router capability. The device operates like a bridge for non-TCP/IP traffic. For TCP/IP traffic it operates in a bridge-like manner but maintains a database associating extended LAN segment addresses with port numbers in the device, so that packets can be automatically forwarded over a spanning tree connecting the network segments. A host computer in any network segment can address others in different network segments of the extended LAN as though all were in a single LAN. The device of the invention functions to block the flow of ARP messages and to generate ARP replies that render the device of the invention transparent to hosts within the extended LAN.Type: GrantFiled: June 29, 1990Date of Patent: May 3, 1994Assignee: Digital Equipment CorporationInventors: Radia J. Perlman, G. Paul Koning
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Patent number: 5308429Abstract: A method and apparatus for bonding a heatsink to a semiconductor chip package using localized pressure and conducted heat. A thermally conductive adhesive film is positioned between the heatsink and the package. A heated copper slug is positioned on top of the heatsink. Heat conducted from the slug and through the heatsink to the adhesive melts and cures the adhesive under a constant pressure supplied by the dead weight of the slug to create a bond-line having a desired thickness.Type: GrantFiled: September 29, 1992Date of Patent: May 3, 1994Assignee: Digital Equipment CorporationInventor: Susan J. Bradley
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Patent number: 5309451Abstract: A method for prefetching the data and parity blocks for generating parity data of a stripe. The method uses a low and high thresholds marker indicative of a first and second level of fullness of the cache to determine whether or not to prefetch the data and parity blocks. If the cache is filled to a level exceeding the first level of fullness, the data and parity blocks are prefetched for any blocks to be written to the disk drive between the low and high threshold. The data and parity blocks are read from the disk drive at a lower processing priority in anticipation of the writing of the block.Type: GrantFiled: August 12, 1992Date of Patent: May 3, 1994Assignee: Digital Equipment CorporationInventors: Eric S. Noya, Randy M. Arnott, Mitchell N. Rosich
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Patent number: 5309035Abstract: An "absolute" delay regulator of a clock repeater chip performs a precise measurement of the propagation delay of a clock signal and adjusts that delay so as to maintain a fixed-phase relationship with an input clock signal. A replica loop accurately replicates the internal path and external loading, including input and output buffers, of the chip. The output of the replica loop drives a delay line whose tapped outputs provide an absolute delay measurement. Results of the measurement are decoded and used to select an appropriate tap to another delay line used to insert a desired amount of delay to an output clock signal.Type: GrantFiled: April 30, 1993Date of Patent: May 3, 1994Assignee: Digital Equipment CorporationInventors: Richard B. Watson, Jr., Hansel A. Collins, Russell Iknaian
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Patent number: D347624Type: GrantFiled: April 29, 1992Date of Patent: June 7, 1994Assignee: Digital Equipment CorporationInventors: William F. McCarthy, Kenneth R. Palumbo, Robert D. Hellweg, Jr., Richard M. Masters, Colin E. Brench, Daniel M. Snow, Peter B. Barron, Michael Freeman, Christopher H. Williams