Abstract: A clamp for fixturing a substrate when forming and thermally processing upon the substrate a thermally flowable layer. The clamp comprises a backing member having a top member connected through a first mechanical means to the backing member. The backing member and the top member are sized such that a substrate may be clamped between the backing member and the top member. A portion of the top member overlaps the substrate and leaves exposed a first portion of the substrate when the substrate is clamped between the backing member and the top member. The clamp also comprises a shroud connected through a second mechanical means to the backing member, where a portion of the shroud overlaps the top member. The shroud leaves exposed a second portion of the substrate which is smaller than and contained within the first portion of the substrate. The shroud is removable from the backing member while the substrate remains clamped between the backing member and the top member.

Abstract: A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereupon a blanket target layer. Formed upon the blanket target layer is a blanket focusing layer, where the blanket focusing layer is formed from an organic material and where the blanket focusing layer is susceptible to a reproducible negative etch bias within a first etch method employed in etching the blanket focusing layer to form a patterned focusing layer. There is then formed upon the blanket focusing layer a blanket photoresist layer which is photoexposed and developed to form a patterned photoresist layer. There is then etched through the first etch method the blanket focusing layer to form the patterned focusing layer while employing the patterned photoresist layer as a first etch mask layer. The patterned focusing layer so formed has the reproducible negative etch bias with respect to the patterned photoresist layer.

Abstract: A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with limited susceptibility to Hot Carrier Effects (HCEs), and a method by which that MOSFET is formed. There is first provided a semiconductor substrate which has a first portion, a second portion adjoining a side of the first portion and a third portion adjoining an opposite side of the first portion. Formed upon the first portion of the semiconductor substrate is a gate oxide layer which has a gate electrode formed and aligned thereupon. The gate electrode has a first sidewall adjoining the second portion of the semiconductor substrate and a second sidewall adjoining the third portion of the semiconductor substrate. Formed upon the first sidewall of the gate electrode and upon the surface of the second portion of the semiconductor substrate adjoining the first sidewall is a conformal oxide layer. The conformal oxide layer has a dose of fluorine atoms incorporated therein.

Abstract: A method for continuously monitoring and controlling the etch rates within integrated circuits of silicon nitride insulator layers and silicon nitride insulator structures in aqueous ortho-phosphoric acid (H3PO4) solutions. To practice the method of the present invention, there is first provided an etch bath chamber containing therein an aqueous ortho-phosphoric acid (H3PO4) solution. There is provided continuously from the etch bath chamber to a hydrometer cell a sample stream of the aqueous ortho-phosphoric acid (H3PO4) solution. The sample stream of the aqueous ortho-phosphoric acid (H3PO4) solution is analyzed continuously within the hydrometer cell to provide a continuous specific gravity analysis of the sample stream of the aqueous ortho-phosphoric acid (H3PO4) solution.

Abstract: A method and apparatus through which there may be delaminated, within the context of a pick-and-place processing method, an integrated circuit die from an adhesive tape backing. To practice the method of the present invention, there is first provided upon an adhesive tape backing an integrated circuit die. The adhesive tape backing comprises a carrier layer and an adhesive layer formed over the carrier layer, where the adhesive layer is positioned between the integrated circuit die and the carrier layer. The adhesive layer has a first portion of the adhesive layer upon which is positioned the integrated circuit die. The adhesive character of the first portion of the adhesive layer is susceptible to substantially complete degradation through exposure to a dose of radiation. There is then exposed selectively the first portion of the adhesive layer to the dose of radiation, preferably ultra-violet (UV) radiation. Finally, the integrated circuit die is removed from the adhesive tape backing.

Abstract: A method for forming a Spin-On-Glass (SOG) residue free Inter-Metal Dielectric (IMD) spacer layer as a substrate layer for a void free conformal insulator layer within a high aspect ratio exceedingly narrowly spaced patterned layer within an integrated circuit. First there is provided a semiconductor substrate having formed thereupon a patterned layer. The patterned layer has a first aperture formed therein. Formed upon the patterned layer and into the first aperture is a conformal Inter-Metal Dielectric (IMD) layer. The conformal Inter-Metal Dielectric (IMD) layer has a second aperture formed therein where the conformal Inter-Metal Dielectric (IMD) layer is formed into the first aperture. Formed upon the conformal Inter-Metal Dielectric (IMD) layer and filling the second aperture is a planarizing Spin-On-Glass (SOG) layer.

Abstract: A method for filling a trench within a substrate. There is first providing a substrate having a trench formed within the substrate. There is then formed over the substrate and within the trench a gap filling silicon oxide trench fill layer. The gap filling silicon oxide trench fill layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method. The method employs an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material at an ozone: TEOS volume ratio of less than about 2:1. Finally, the substrate is annealed thermally within an oxygen containing atmosphere at a temperature of greater than about 1100 degrees centigrade to form from the gap filling silicon oxide trench fill layer a densified gap filling silicon oxide trench fill layer. Through the method there is formed a densified gap filling silicon oxide trench fill layer with a limited surface sensitivity, a low etch rate and a limited shrinkage.

Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer through a first reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer through a second reactive ion etch (RIE) method employing a second etchant gas composition comprising carbon tetrafluoride and oxygen.

Abstract: A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer.

Abstract: A thermal annealing method for forming a nitride layer within an integrated circuit. There is first provided a substrate. There is then formed over the substrate a nitride forming material layer. The nitride forming material layer is then annealed through a thermal annealing method in the presence of an atmosphere of activated nitrogen to yield a nitride layer. The method is particularly useful for forming titanium nitride barrier layers and titanium nitride adhesion promoter layers within integrated circuits.

Abstract: A method for forming upon a reflective layer, such as a reflective conducting layer, within an integrated circuit an Anti-Reflective Coating (ARC) which simultaneously possesses adhesion promotion characteristics for an organic layer to be formed upon the reflective layer. There is first formed upon a semiconductor wafer a reflective integrated circuit layer which may be a hydrophilic reflective integrated circuit layer or a hydrophobic integrated circuit layer. The semiconductor wafer is then immersed into and withdrawn from a Langmuir trough having formed therein a Langmuir-Blodgett (LB) monolayer film of a dye surfactant molecule ordered upon a surface of water. Upon withdrawing the wafer from the Langmuir trough, there is formed upon the reflective integrated circuit layer an ordered LB film of the dye surfactant molecule. The chromophore groups within the dye surfactant molecule and ordered LB film provide ARC characteristics to the reflective layer.

Abstract: A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer.

Abstract: A method for forming a narrow via through a portion of an integrated circuit layer between a pair of integrated circuit structures within an integrated circuit. There is first provided a substrate layer having a pair of integrated circuit structures formed thereupon. The integrated circuit structures are separated by a width over the substrate layer no less than the width of a narrow via desired to be formed through a portion of a first integrated circuit layer formed between the pair of integrated circuit structures plus two times a registration tolerance of a photoexposure apparatus employed in defining the location of a wide via from which is formed the narrow via plus two times a minimum integrated circuit layer width separating the narrow via from each integrated circuit structure within the pair of integrated circuit structures. There is then formed over the substrate layer and upon the integrated circuit structures the first integrated circuit layer.

Abstract: A method for forming a dual stripe magnetoresistive (DSMR) sensor element. The method employs a lift off stencil an etch mask for sequentially anisotropically etching a blanket second magnetoresistive (MR) layer, a blanket inter stripe dielectric layer and a blanket first magnetoresistive (MR) layer to form a patterned second magnetoresistive (MR) layer, a patterned inter stripe dielectric layer and a patterned first magnetoresistive (MR) layer with fully aligned edges. The lift off stencil is then employed as a lift off mask in forming a patterned dielectric layer covering the fully aligned edges. In a second embodiment a window within a lift off stencil is employed as an etch mask in forming aligned edges of a trimmed patterned first magnetoresistive (MR) layer and a trimmed patterned second magnetoresistive (MR) layer within the composite track width of a patterned first magnetoresistive (MR) layer and a patterned second magnetoresistive (MR) layer which are offset.

Abstract: A Chemical-Mechanical Polish (CMP) planarizing method and a Chemical-Mechanical Polish (CMP) slurry composition for Chemical-Mechanical Polish (CMP) planarizing of copper metal and copper metal alloy layers within integrated circuits. There is first provided a semiconductor substrate having formed upon its surface a patterned substrate layer. Formed within and upon the patterned substrate layer is a blanket copper metal layer or a blanket copper metal alloy layer. The blanket copper metal layer or blanket copper metal alloy layer is then planarized through a Chemical-Mechanical Polish (CMP) planarizing method employing a Chemical-Mechanical Polish (CMP) slurry composition. The Chemical-Mechanical Polish (CMP) slurry composition comprises a non-aqueous coordinating solvent and a halogen radical producing specie.

Abstract: An anti-reflective reticle and a method by which the anti-reflective reticle is formed. Formed upon a first surface of a transparent substrate is a patterned metal layer. Formed upon at least one of: (1) the first surface of the transparent substrate including the patterned metal layer; or (2) the surface of the transparent substrate opposite the patterned metal layer is a two-layer dielectric stack. The two layer dielectric stack has a first dielectric layer which is closer to the transparent substrate and a second dielectric layer which is formed directly upon the first dielectric layer. The first dielectric layer has an index of refraction greater than the index of refraction of the transparent substrate or the second dielectric layer. The second dielectric layer has a thickness of about one-quarter the wavelength of reflected light desired to be attenuated or eliminated from the surface of the reticle.

Abstract: A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer formed from an organic anti-reflective coating (ARC) material, where the blanket focusing layer is susceptible to a reproducible negative etch bias within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing a reactant gas composition comprising trifluoromethane, carbon tetrafluoride, oxygen and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer which is photoexposed and developed to form a patterned photoresist layer.

Abstract: A method for forming within an integrated circuit a low impurity diffusion polysilicon layer. Formed upon a semiconductor substrate is an amorphous silicon layer. Formed also upon the semiconductor substrate and contacting the amorphous silicon layer is a polysilicon layer. The amorphous silicon layer and the polysilicon layer are then simultaneously annealed to form a low impurity diffusion polysilicon layer. The low impurity diffusion polysilicon layer is a polysilicon multi-layer with grain boundary mis-matched polycrystalline properties. Optionally, a metal silicide layer may be formed upon the amorphous silicon layer and the polysilicon layer either prior to or subsequent to annealing the amorphous silicon layer and the polysilicon layer. The metal silicide layer and low impurity diffusion polysilicon layer may then be patterned to form a polycide gate electrode.

Abstract: A magnetic material which may be employed as a thin film magnetic layer within magnetic heads, and a method for forming the magnetic material as a thin film magnetic layer for use within magnetic heads. The magnetic material has an elemental composition comprising about 40 to about 60 weight percent iron, about 40 to about 60 weight percent nickel and about 0.002 to about 1 weight percent tin. The magnetic material may be formed as a thin film magnetic layer for use within a magnetic head through an electrochemical plating method employing an aqueous plating solution comprising iron (II) ions, nickel (II) ions and tin (II) ions.

Abstract: A method for forming upon a semiconductor substrate a void free titanium nitride Anti-Reflective Coating (ARC) layer upon an aluminum containing conductor layer. There is first formed upon a semiconductor substrate an aluminum containing conductor layer. There is then formed upon the aluminum containing conductor layer a titanium rich titanium nitride layer which has a titanium:nitrogen molar ratio of greater than about 1.1:1. Finally, there is formed upon the titanium rich titanium nitride layer a substantially stoichiometric titanium nitride layer which has a titanium:nitrogen molar ratio of from about 1.0:1 to about 1.1:1. Optionally, a patterned photo resist layer may be formed upon the surface of the substantially stoichiometric titanium nitride layer and the substantially stoichiometric titanium nitride layer, the titanium rich titanium nitride layer and the aluminum containing conductor layer may be sequentially patterned.