Abstract: A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer, where the blanket focusing layer is formed of an organic anti-reflective coating (ARC) material which is susceptible to a reproducible positive taper within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer. The blanket photoresist layer is then photoexposed and developed layer to form a patterned photoresist layer.

Abstract: An N-Channel Metal Oxide Semiconductor Field Effect Transistor (N-MOSFET) with minimum susceptibility to the Hot Carrier Effect (HCE) and a method by which the N-MOSFET is fabricated. Formed upon a semiconductor substrate is a N-MOSFET structure including a gate oxide upon a semiconductor substrate, a gate electrode upon the gate oxide and a pair of N+ source/drain regions adjoining the gate electrode and the gate oxide. Implanted into the gate oxide regions beneath the gate electrode edges is a dose of a hardening ion. The hardening ion may be either nitrogen ion or fluorine ion. The hardening ion is implanted at an angle non-orthogonal to the plane of the semiconductor substrate through means of a large tilt angle ion implant process. Optionally, a Lightly Doped Drain (LDD) source/drain electrode structure or Double Doped Drain (DDD) source/drain electrode structure may be incorporated into the N-MOSFET structure.

Abstract: A three-dimensional polysilicon capacitor for use within integrated circuits and a method by which the three-dimensional polysilicon capacitor is formed. Formed upon a semiconductor substrate is a first polysilicon layer which has a series of apertures formed at least partially through the first polysilicon layer. A conformal insulator layer is then formed upon the first polysilicon layer and into the apertures within the first polysilicon layer. The conformal insulator layer has a series of apertures corresponding to the series of apertures within the first polysilicon layer. A second polysilicon layer is then formed upon the surface of the conformal insulator layer and filling the apertures within the conformal insulator layer. Optionally, the first polysilicon layer may be formed from a multi-coating stack comprising two polysilicon coatings separated by an metal silicide etch stop layer.

Abstract: A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then formed upon the thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material.

Abstract: A method for forming a patterned non-transparent layer over a substrate. There is first provided a substrate which has an alignment mark formed thereupon. There is then formed over the substrate including the alignment mark a blanket non-transparent layer. The blanket non-transparent layer only partially replicates the alignment mark to yield upon the blanket non-transparent layer a partially replicated alignment mark at a location substantially corresponding with the location of the alignment mark formed upon the substrate. There is then removed through a first photolithographic and etch method a first portion of the blanket non-transparent layer to completely expose the alignment mark while simultaneously forming a partially patterned non-transparent layer. The first photolithographic and etch method employs the partially replicated alignment mark to register a first photolithographic mask with respect to the substrate.

Abstract: A method for forming within an integrated circuit a narrow line-width high aspect ratio via through a first integrated circuit layer which resides upon a second integrated circuit layer. There is first formed upon a semiconductor substrate a second integrated circuit layer which has formed upon its surface a first integrated circuit layer. Through a first etch method, a partial via is then formed within the first integrated circuit layer to a distance of from about 2500 to about 4000 angstroms above the surface of the second integrated circuit layer. The first etch method is chosen to provide a partial via with substantially parallel sidewalls. Through a second etch method, the partial via is then etched completely through the first integrated circuit layer. The second etch method is chosen to possesses an etch selectivity ratio for the first integrated circuit layer with respect to the second integrated circuit layer of at least about 60:1.

Abstract: A method for controlling the plasma etch bias of a patterned layer formed through plasma etching of a blanket layer formed beneath a patterned photoresist layer. There is first formed upon a semiconductor substrate a blanket layer. Formed upon the blanket layer is a patterned photoresist layer. The patterned photoresist layer is then treated through a pre-treatment method to form with a controlled degradation and a controlled flow a hardened patterned photoresist layer from the patterned photoresist layer. The hardened patterned photoresist layer is hardened against a further flow in a subsequent plasma etch method which is employed in etching the patterned layer from the blanket layer while employing the hardened patterned photoresist layer as an etch mask. Finally, the blanket layer is etched through the subsequent plasma etch method to form the patterned layer while employing the hardened patterned photoresist layer as the etch mask.

Abstract: A method for forming, without dishing, a planarized aperture fill layer within an aperture within a substrate. There is first provided a substrate having an aperture formed therein. There is then formed upon the substrate and within the aperture a conformal aperture fill layer, where the conformal aperture fill layer is thicker than the depth of the aperture. There is then formed upon the conformal aperture fill layer a conformal polish stop layer having a lower planar region of the conformal polish stop layer where the conformal aperture fill layer is formed within the aperture. The conformal polish stop layer and the conformal aperture fill layer are then planarized through a first chemical mechanical polish (CMP) planarizing method until there is reached the lower planar region of the conformal polish stop layer, while simultaneously forming a patterned polish stop layer and a partially chemical mechanical polish (CMP) planarized aperture fill layer.

Abstract: A low fringe-field and narrow write-track magnetic read-write head. The low fringe-field and narrow write-track magnetic read-write head includes a first pole layer formed adjoining an insulator layer over a substrate. The first pole layer has a first air bearing surface which has a first edge adjoining and parallel with a first surface of the insulator layer. The low fringe-field and narrow write-track magnetic read-write head also includes a second pole layer separated from the first pole layer by the insulator layer. The second pole layer has a width no greater than about 20 microns and a width no greater than about 100 percent of the width of the first pole layer where the width of the second pole layer is contained within the width of the first pole layer. The second pole layer also has a second air bearing surface coplanar with the first air bearing surface.

Abstract: A method for forming a diode for use within an integrated circuit, and a diode formed through the method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a dielectric layer. There is then formed upon the dielectric layer a first polysilicon layer, where the first polysilicon layer has a first dopant polarity and a first dopant concentration. There is then formed at least in part overlapping and at least in part in contact with the first polysilicon layer a second polysilicon layer. The second polysilicon layer has a second dopant polarity and a second dopant concentration, where the second dopant polarity is opposite to the first dopant polarity. A first portion of the second polysilicon layer overlapping and in contact within a first portion of the first polysilicon layer forms a junction diode.

Abstract: A method for forming a tungsten silicide polycide gate electrode within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the tungsten silicide polycide gate electrode which is formed through the method. Formed upon a semiconductor substrate is a gate oxide layer. Formed upon the gate oxide layer is a first polysilicon layer which is formed through annealing a first amorphous silicon layer. Formed upon the first polysilicon layer is a second polysilicon layer which is formed through annealing a second amorphous silicon layer. Formed upon the second polysilicon layer is a tungsten silicide layer formed through a Chemical Vapor Deposition (CVD) method. The first polysilicon layer and the second polysilicon layer have a crystallite size no greater than about 0.3 microns, and the first polysilicon layer and the second polysilicon layer have a dopant concentration larger than about 1E16 atoms per cubic centimeter.

Abstract: A method for cleaning a semiconductor substrate. Introduced into a semiconductor substrate processing chamber is a semiconductor substrate. The semiconductor substrate and the semiconductor substrate processing chamber are maintained at a temperature not exceeding about 800 degrees centigrade. Introduced substantially simultaneously with the semiconductor substrate into the semiconductor substrate processing chamber is a low flow of a first oxidant gas. Introduced into the semiconductor substrate processing chamber immediately subsequent to the low flow of the first oxidant gas is a high flow of a second oxidant gas. Introduced into the semiconductor wafer processing chamber no earlier than the high flow of the second oxidant gas is a flow of a chlorine containing getter material.

Abstract: A method for determining through a test structure a longitudinal magnetic exchange field within a patterned exchange biased magnetoresistive (MR) sensor element. To practice the method, there is first provided a substrate. Formed upon the substrate is a patterned magnetoresistive (MR) layer which has a projected length upon the substrate and a projected width upon the substrate. There is formed at a pair of separated locations over the patterned magnetoresistive (MR) layer a pair of patterned conductor lead layers. The pair of patterned conductor lead layers is separated by a track width of the patterned magnetoresistive (MR) layer, where the track width is smaller than the projected width.

Abstract: A method for forming within a trench within a substrate within an integrated circuit a planarized trench fill layer. There is first provided a substrate having a trench formed therein. There is formed upon the substrate at regions other than those within the trench a first integrated circuit layer which has a composition which inhibits formation upon the first integrated circuit layer of a trench fill layer which is subsequently formed upon the substrate and within the trench. There is also formed within the trench but not upon the substrate at regions other than those within the trench a second integrated circuit layer which has a composition which promotes formation within the trench of the trench fill layer which is subsequently formed upon the substrate and within the trench. Finally, there is formed upon the substrate and within the trench the trench fill layer.

Abstract: A method for optically inspecting a semiconductor substrate for defects such as oxidation induced stacking faults, and a template mask which assists in practicing the optical inspection method. There is first provided a semiconductor substrate which has a surface to be inspected for defects such as oxidation induced stacking faults. Aligned then upon the surface of the semiconductor substrate to be inspected for defects such as oxidation induced stacking faults is a template mask. The template mask has a minimum of one aperture which leaves exposed a portion of the surface of the semiconductor substrate to be inspected for defects such as oxidation induced stacking faults. Finally, there is inspected optically the portion of the surface of the semiconductor substrate exposed through the aperture.

Abstract: A method for limiting contaminant particle deposition upon integrated circuit layers within plasma assisted process reactor chambers. First, there is undertaken a plasma assisted process upon an integrated circuit layer within a plasma assisted process reactor chamber. The plasma assisted process employs a reactant gas composition, a first radio frequency power and a first reactor chamber pressure appropriate to the plasma assisted process and the integrated circuit layer. There is then undertaken a first plasma purge step for a first purge time immediately following the plasma assisted process. The first plasma purge step employs a first purge gas composition, a second radio frequency power and a second reactor chamber pressure. The second radio frequency power is lower than the first radio frequency power and the second reactor chamber pressure is higher than the first reactor chamber pressure.

Abstract: A method for forming patterned conductor metallization layers adjoining patterned barrier metallization layers upon semiconductor substrates. A semiconductor substrate is provided which has formed upon its surface a patterned second masking layer upon a blanket first masking layer. The patterned second masking layer is formed from a photoresist material and the blanket first masking layer is formed from a silicon oxide material, a silicon nitride material or a silicon oxynitride material. Beneath the blanket first masking layer resides a blanket multi-layer metallization stack which includes a blanket conductor metallization layer adjoining a blanket barrier metallization layer. The blanket first masking layer and the upper lying blanket metallization layer of the blanket conductor metallization layer and the blanket barrier metallization layer are successively patterned through a Reactive Ion Etch (RIE) process using as the etch mask the patterned second masking layer.

Abstract: A method for forming a double layer planar polysilicon capacitor for use within integrated circuits is presented. Formed within a semiconductor substrate is a deep trench which is filled with a dielectric material. Formed within the dielectric material within the deep trench is a shallow trench which has a first polysilicon capacitor plate formed therein. The upper surface of the first polysilicon capacitor plate is substantially planar with the semiconductor substrate. Formed upon the first polysilicon capacitor plate is a polysilicon capacitor dielectric layer. Formed upon the polysilicon capacitor dielectric layer is a second polysilicon capacitor plate.

Abstract: A low capacitance input/output integrated circuit and a method by which the low capacitance input/output integrated circuit is formed. Formed upon a semiconductor substrate is an input/output integrated circuit which contains a minimum of one integrated circuit device. The integrated circuit device, in turn, possesses at minimum a source electrode and a drain electrode of the same polarity. Coincident with the source electrode and the drain electrode are normally at least one ion implant of polarity opposite to the source electrode and the drain electrode. At least a portion of the drain electrode is masked when the ion implant(s) of polarity opposite to the source electrode and the drain electrode are provided into the source electrode region and the drain electrode region of the integrated circuit device(s).

Abstract: A method for plasma hardening a patterned photoresist layer. There is first provided a semiconductor substrate which has formed upon its surface a patterned photoresist layer. The patterned photoresist layer is then exposed to a hydrogen containing plasma for a time sufficient to harden the patterned photoresist layer against a Reactive Ion Etch (RIE) etch plasma to which the patterned photoresist layer is later exposed. A blanket layer residing beneath the plasma hardened photoresist layer may then be patterned through the Reactive Ion Etch (RIE) etch plasma without softening, erosion and/or consumption of the plasma hardened patterned photoresist layer.