Abstract: A method for forming a narrow cross-sectional diameter via through an insulator layer for use within an integrated circuit. Formed upon a semiconductor substrate is a metal layer. At least the top surface of the metal layer is formed from a titanium nitride layer. Formed upon the titanium nitride layer is an insulator layer. The insulator layer exhibits a first incubation time with respect to forming an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator coating upon the insulator layer. The first incubation time is less than a second incubation time for forming the same ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator coating upon the titanium nitride layer. A conventional via is then formed completely through the insulator layer. The bottom of the conventional via exposes a portion of the titanium nitride layer.

Abstract: A polysilicon resistor structure and a method by which the polysilicon resistor structure may be formed. A polysilicon resistor is formed upon the surface of a semiconductor substrate. A pair of dummy polysilicon layers is formed along opposite edges and separated from the polysilicon resistor. A pair of metal sidewalls is then formed upon the upper surfaces of the pair of dummy polysilicon layers, and a top metal layer is formed bridging the upper surfaces of the pair of metal sidewalls. The pair of dummy polysilicon layers, the pair of metal sidewalls and the top metal layer form an open ended cavity upon the semiconductor substrate within which structure the polysilicon resistor resides. The polysilicon resistor is separated from the structure by an insulating material which is not susceptible to outgassing of hydrogen.

Abstract: A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer.