Abstract: A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) exhibiting enhanced immunity to Hot Carrier Effects (HCEs), and a method by which the MOSFET may be formed. To form the MOSFET there is first provided a semiconductor substrate having a gate dielectric layer formed thereupon. The gate dielectric layer has a gate electrode formed thereupon, where the gate dielectric layer extends beyond a pair of opposite edges of the gate electrode. Formed into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode is a pair of low dose ion implants. Formed upon the gate dielectric layer and contacting the pair of opposite edges of the gate electrode is a pair of conductive spacers. The pair of conductive spacers partially overlaps the pair of low dose ion implants. Finally, there is formed into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode and further removed from the pair of conductive spacers a pair of source/drain electrodes.

Abstract: A method for forming a dual stripe magnetoresistive (DSMR) sensor element, and the dual stripe magnetoresistive (DSMR) sensor element formed through the method. To practice the method, there is formed upon a substrate a first magnetoresistive (MR) layer, where the first magnetoresistive (MR) layer has a first sensor region longitudinally magnetically biased in a first longitudinal bias direction through a patterned first longitudinal magnetic biasing layer. There is then formed a second magnetoresistive (MR) layer parallel with and separated from the first magnetoresistive (MR) layer by an insulator layer. The second magnetoresistive (MR) layer has a second sensor region longitudinally magnetically biased in a second longitudinal bias direction through a patterned second longitudinal magnetic biasing layer. The first longitudinal bias direction and the second longitudinal bias direction are substantially parallel. In addition, the first sensor region and the second sensor region are physically offset.

Abstract: A method for forming an insulator layer with enhanced uniformity when planarized through a Chemical-Mechanical Polish (CMP) planarizing process. There is first provided a semiconductor substrate having formed thereupon a patterned layer. The patterned layer has a volume density greater than the volume density of an insulator layer to be formed upon the patterned layer. The patterned layer also has a first region having a high areal density of the patterned layer and a second region having a low areal density of the patterned layer. The second region of the patterned layer is then masked. The first region of the patterned layer is then exposed to a first plasma which is capable of modifying the first region of the patterned layer such that the insulator layer will form less rapidly upon the first region of the patterned layer than upon the second region of the patterned layer. The second region of the semiconductor substrate is then unmasked and the insulator layer is formed upon the patterned layer.

Abstract: A method for removing particulate residues from semiconductor substrates. A semiconductor substrate is provided which has upon its surface a particulate residue. At minimum, either the semiconductor substrate or the particulate residue is susceptible to oxidation upon exposure to an oxygen containing plasma. The semiconductor substrate and the particulate residue are exposed to an oxygen plasma. The particulates are then rinsed from the surface of the semiconductor substrate with deionized water.

Abstract: A method for planarizing a high step-height integrated circuit structure within an integrated circuit. There is first formed upon a semiconductor substrate a high step-height integrated circuit structure. Formed then adjoining the high step-height integrated circuit structure is a patterned Global Planarization Dielectric (GPD) layer. There is then formed upon the exposed surfaces of the semiconductor substrate, the high step-height integrated circuit structure and the patterned Global Planarization Dielectric (GPD) layer a reflowable dielectric layer. Finally, the reflowable dielectric layer is reflowed.

Abstract: An attenuated Phase Shift Mask (PSM) blank and an attenuated Phase Shift Mask (PSM), and a method by which the attenuated Phase Shift Mask (PSM) blank and the attenuated Phase Shift Mask (PSM) may be formed. To form the attenuated Phase Shift Mask (PSM) blank there is first provided a transparent substrate. Formed upon the transparent substrate is a tantalum-silicon oxide blanket semi-transparent shifter layer which has the formula,Ta.sub.x Si.sub.y O.sub.1-x-ywherein 0.1<x<0.3 and 0.03<y<0.1. To form the attenuated Phase Shift Mask (PSM) from the attenuated Phase Shift Mask (PSM) blank, the tantalum-silicon oxide blanket semi-transparent shifter layer is patterned to form a tantalum-silicon oxide patterned semi-transparent shifter layer.

Abstract: A method for forming metal patterns through use of a multi-step magnetically assisted reactive ion etch plasma process. A metal layer is formed upon a semiconductor substrate. The metal layer is patterned with a photoresist composition which leaves exposed those regions of metal to be removed. The exposed metal is removed through a multi-step magnetically assisted reactive ion etch process. The first etch step is a primary metal etch at elevated levels of radio frequency power and magnetic field strength. The last etch step is a secondary metal over-etch step at lower levels of radio frequency power and magnetic field strength. Intermediate to the first etch step and last etch step are a multiplicity of etch process steps where the radio frequency power and magnetic field strength are independently and sequentially reduced.

Abstract: A method for forming a low contact leakage and low contact resistance integrated circuit device electrode within an integrated circuit, and the low contact leakage and low contact resistance integrated circuit device electrode formed through the method. There is first formed within a semiconductor substrate an integrated circuit device electrode. The integrated circuit device electrode has a width upon the semiconductor substrate of less than the width of a conductor element desired to be formed upon the integrated circuit device electrode plus two times the registration tolerance of a fabrication tool employed in defining the location of the conductor element desired to be formed upon the integrated circuit device electrode. Formed then upon the semiconductor substrate including the integrated circuit device electrode is a blanket metal silicide forming metal layer.

Abstract: A method for limiting contaminant particle deposition upon integrated circuit layers within plasma assisted process reactor chambers. First, a plasma assisted process is undertaken upon an integrated circuit layer within a plasma assisted process reactor chamber. The plasma assisted process employs a first reactant gas composition, a first radio frequency power and a first reactor chamber pressure appropriate to the plasma assisted process and the integrated circuit layer. Immediately following the plasma assisted process is undertaken a first plasma purge step. The first plasma purge step employs a first concentration of an oxidizing reactant gas, a first concentration of a non-oxidizing reactant gas, a second radio frequency power and a second reactor chamber pressure. The second radio frequency power is lower than the first radio frequency power and the second reactor chamber pressure is higher than the first reactor chamber pressure.

Abstract: A method for forming a low-energy electron excited fluorescent screen. First, there is dissolved in a non-aqueous solvent a charging material. The charging material when dissolved forms a cation which is susceptible to forming an oxide, which oxide is a first essential component of a low-energy electron excited fluorescent phosphor composition. In addition to the charging material, there is suspended in the non-aqueous solvent a phosphor which naturally adopts a positive charge in the non-aqueous solvent. The phosphor is a second essential component of the low-energy electron excited fluorescent phosphor composition. There is then electrophoretically deposited from the non-aqueous solvent the cation and the phosphor to form a low-energy electron excited fluorescent phosphor precursor composition. The electrophoretic deposition occurs upon a fluorescent screen substrate which serves as a cathode.

Abstract: A method for forming damage free patterned layers adjoining the edges of high step height apertures within integrated circuits. There is first provided a semiconductor substrate which has a first aperture formed therein. Formed upon the semiconductor substrate and into the first aperture is a blanket layer. The blanket layer has a second aperture formed therein where the blanket layer is formed into the first aperture. Formed then into the second aperture is a buffer layer. The buffer layer substantially planarizes the blanket layer. Formed then upon the semiconductor substrate is a blanket photoresist layer. The blanket photoresist layer and the blanket layer are then sequentially patterned to form a patterned photoresist layer and a damage free patterned layer.

Abstract: A method for forming a low voltage coefficient capacitor within an integrated circuit. Formed upon a semiconductor substrate is a first polysilicon layer. Formed directly upon the first polysilicon layer is an Inter Polysilicon Dielectric (IPD) layer. Formed directly upon the Inter Polysilicon Dielectric (IPD) layer is a second polysilicon layer. The first polysilicon layer and the second polysilicon layer each have a resistivity no greater than about 40 ohms per square. Formed directly upon the second polysilicon layer is an amorphous silicon layer. Formed directly upon the amorphous silicon layer is a metal layer which is capable of forming a metal silicide with the amorphous silicon layer. The thickness of the metal layer and the thickness of the amorphous silicon layer are chosen to form a stoichiometric metal silicide with minimal consumption of the polysilicon layer. Finally, the semiconductor substrate is annealed to form a metal silicide layer from the amorphous silicon layer and the metal layer.

Abstract: A method for photo-exposing a blanket conformal photosensitive layer upon a high step height topography substrate layer. There is first provided a high step height topography substrate layer having a blanket conformal photosensitive layer formed thereupon. The high step height topography substrate layer has a first region having a first step height separated from a third region having a third step height by a second region having a second step height. The second step height is intermediate to the first step height and the third step height. The blanket conformal photosensitive layer is photo-exposed to form a first pattern upon the first region and the second region through use of a first reticle and a first photo-exposure condition. The first photo-exposure condition provides a first depth of focus suitable for at least the first region.

Abstract: A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer.

Abstract: A method for forming a residue free patterned conductor layer upon a high step height integrated circuit substrate. First, there is provided a semiconductor substrate having formed thereon a high step height patterned integrated circuit layer. Formed upon the high step height patterned integrated circuit layer is a blanket conductor layer, and formed upon the blanket conductor layer is a patterned photoresist layer. The portions of the blanket conductor layer exposed through the patterned photoresist layer are etched through an anisotropic etch process to leave remaining a patterned conductor layer upon the surface of the high step height patterned integrated circuit layer and conductor layer residues at a lower step level of the high step height patterned integrated circuit layer. The patterned photoresist layer is then reflowed to cover exposed edges of the patterned conductor layer.

Abstract: A polysilicon resistor structure for use within integrated circuits and a method by which the polysilicon resistor structure may be formed. A first insulating layer which is formed from a glasseous material is formed directly upon the surface of a semiconductor substrate. A polysilicon resistor is formed in contact with the first insulating layer. A second insulating layer is formed directly upon the first insulating layer and over the polysilicon resistor. The second insulating layer is formed from a silicon oxide material deposited through a Plasma Enhanced Chemical Vapor Deposition process employing silane as the silicon source material.

Abstract: A method for forming a gap-filling and self-planarizing silicon oxide insulator spacer layer within a patterned integrated circuit layer. Formed upon a semiconductor substrate is a patterned integrated circuit layer which is structured with a titanium nitride upper-most layer. The patterned integrated circuit layer also has at least one lower-lying layer formed of a material having a growth rate with respect to ozone assisted Chemical Vapor Deposited (CVD) silicon oxide layers greater than the growth rate of ozone assisted Chemical Vapor Deposited (CVD) silicon oxide layers upon titanium nitride. Formed within and upon the patterned integrated circuit layer is a silicon oxide insulator spacer layer deposited through an ozone assisted Chemical Vapor Deposition (CVD) process. The silicon oxide insulator spacer layer is formed until the surface of the titanium nitride upper-most layer is passivated with the silicon oxide insulator spacer layer.

Abstract: A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with limited susceptibility to Hot Carrier Effects (HCEs), and a method by which that MOSFET is formed. There is first provided a semiconductor substrate which has a first portion, a second portion adjoining a side of the first portion and a third portion adjoining an opposite side of the first portion. Formed upon the first portion of the semiconductor substrate is a gate oxide layer which has a gate electrode formed and aligned thereupon. The gate electrode has a first sidewall adjoining the second portion of the semiconductor substrate and a second sidewall adjoining the third portion of the semiconductor substrate. Formed upon the first sidewall of the gate electrode and upon the surface of the second portion of the semiconductor substrate adjoining the first sidewall is a conformal oxide layer. The conformal oxide layer has a dose of fluorine atoms incorporated therein.

Abstract: A multi-layer polysilicon resistor and a method by which the multi-layer polysilicon resistor is formed. A minimum of two polysilicon layers is formed upon an insulating layer, the insulating layer in turn being formed upon a semiconductor substrate. The first polysilicon layer is formed to a first thickness at a first deposition temperature. The second polysilicon layer is formed directly upon the first polysilicon layer. The second polysilicon layer is formed to a second thickness at a second deposition temperature. The two deposition temperatures are in the range of about 450 degrees centigrade to about 620 degrees centigrade, and the difference in temperature between the first deposition temperature and the second deposition temperature is a minimum of 10 degrees centigrade.

Abstract: A Reactive Ion Etch (RIE) plasma method for removing from semiconductor substrates oxidized organic residues such as oxidized photoresist residues, and the Reactive Ion Etch (RIE) plasma which is employed within the Reactive Ion Etch (RIE) plasma method. A semiconductor substrate upon whose surface resides an oxidized organic residue such as an oxidized photoresist residue is provided into a Reactive Ion Etch (RIE) plasma chamber. Also provided into the chamber is a concentration of oxygen and a concentration of moisture. Finally, a radio frequency excitation of sufficient magnitude is provided to the concentration of oxygen and the concentration of moisture to form a plasma. The oxidized organic residue which resides upon the semiconductor substrate is then removed through etching in the Reactive Ion Etch (RIE) plasma.