Abstract: Improved accumulation apparatus for generating phantom raster in skewed Cartesian coordinates uses two, rather than four, accumulators. Arrangements for accommodating non-square pixels are described; as well as arrangements for accommodating the display image being compressed, expanded, or changed in aspect ratio.

Abstract: The storage locations of a memory system map a field of sample points. Apparatus affording parallel access to a plurality of storage locations describing an array of the sample points in an access window, which window can be shifted to any selected region of field of sample points responsive to orthogonal address coordinates of one of the sample points in the array, is described.

Abstract: The process of linearly interpolating between data taken from adjacent storage locations in a memory non-integrally addressed has the initial subtraction and final addition steps eliminated from it, and the partial products to be summed in the intervening multiplication process are modified to compensate for the elimination of these steps. This modification is done with a relatively fast select-one-of-four process, reducing the time for linear interpolation to that required for a simple multiplication--or, in the case of a single-bit multiplier, to the time for selection of the modified multiplicand to be used as linear interpolation result.

Abstract: Phantom raster scanning of an image memory, in which the image is stored in compacted form, is made possible by introducing offsets in strictly spatial coordinates, rather than in time coordinates parallelling a particular spatial coordinate system.

Abstract: Oscillators phase locked to transitions in the envelope of a bandwidth-limited complex waveform are used, for example, in detecting MPSK signals. The magnitude of the envelope is approximated by linearly combining the real and imaginary components of the complex waveform, or by selecting the larger of the two components, or by using both these techniques in combination.

Abstract: Graphics for television display which emphasize circles, ellipses, circular or elliptical arcs, and the radii of circles or ellipses are conveniently stored in image memories addressable in polar coordinates. Television images which are to be rotated are conveniently stored in such memories, so the angular coordinate of the image memory addresses can be incremented or decremented to rotate the image with hardware as simple as a single adder. To read image memories addressed in polar coordinates, the Cartesian coordinates descriptive of television raster display are scan-converted to polar coordinates. This scan conversion takes place in real time at video sampling rates. The generation of the angular coordinate of the polar coordinates is facilitated by dividing one Cartesian coordinate by another by differentially combining their logarithms as found from read-only-memory table look-up, then finding an arc tangent from the logarithm of their difference as found from further read-only-memory table look-up.

Abstract: Orthogonal Cartesian coordinates descriptive of the raster scanning of a television display screen are generated at a programmable skew angle to the Cartesian coordinates of an image stored in memory. Each of these generated coordinates has a number of more significant bits used to generate the column and row addresses for that memory, four spatially adjacent storage location of which are read from for developing each sample of video signal describing a rotated television image. Each of these generated coordinates has a number of less significant bits affording resolution higher than that with which the memory can be addressed, which are used for calculation of each video sample by two-dimensional interpolation between the read-outs from the four locations in memory. To avoid aliasing as the image is rotated, the digital video to be stored in memory is processed using two-dimensional spatial-frequency low-pass filters to reduce resolution in directions other than horizontal and vertical.

Abstract: A switching voltage regulator in which the input voltage to a switching dc-to-dc converter is boosted and the output voltage of the converter is indirectly regulated responsive to direct regulation of the boosted voltage.

Abstract: DC-to-dc switching converters that deliver non-pulsating output current use a conventional transformer and a flyback transformer with primary windings recurrently connected in series to the primary d-c energy source and with secondary windings alternately connected to the output load.

Abstract: Color signal samples generated by CCD imagers used with a color stripe filter normally exhibit hue errors associated with misalignment of the color striped imager on the imager elements, which errors are obtrusive to the viewer of a TV display based on those color signal samples. These hue errors are converted to less-obtrusive color saturation and luminance errors in accordance with the invention, by re-sampling the color signals.

Abstract: A memory with a plurality of memory planes parallelly addressed by row and by column is used to store digitally generated graphic information for constructing a video display--e.g., on the screen of a kinescope or other cathode ray tube. Angular scanning of the memory addresses is provided by accumulating in tangent or cotangent of the scanning angle and using its integer part as one of the row and column addresses and by counting the cycles of accumulation to provide the other of the row and column addresses.

Abstract: A push-pull switching dc-to-dc converter using controlled rectifiers as switch elements delivers uninterrupted output current to its load, owing to the inclusion of plural-winding inductors.

Abstract: A gradient in the impurity concentration of the semiconductor material in a CCD imager, normal to the surface in which the charge-accumulation wells are induced, speeds the collection of charge carriers formed further from the surface by photon interaction with the semiconductor lattice. This reduces the chance for crosstalk between charge-accumulation wells owing to sideways diffusion.

Abstract: A current mirror amplifier comprising a master mirroring transistor with collector-to-base connection for adjusting its emitter-to-base potential to condition it to conduct input current applied to its collector-emitter path, a plurality of slave mirroring transistors arranged to respond to an emitter-to-base potential equal to that of the master mirroring transistor for conducting an output current through its emitter-collector path proportional to the input current, a further transistor with its collector-emitter path arranged to sense the collector current of one of the slave mirroring transistors, and a component current mirror amplifier responding to the base current of the further transistor flowing through its input connection to supply a substantial share of the base current needs of said mirroring transistors at its output connection.

Abstract: A common-collector-amplifier transistor is followed in direct-coupled cascade connection by a common-emitter amplifier transistor. A multiple-V.sub.BE supply biases the base of the common-collector-amplifier transistor respective to the emitter of the common-emitter amplifier, so the quiescent collector current of the common-emitter-amplifier transistor can be accurately defined. To improve the high-frequency response of the common-collector amplifier transistor, while preserving the capability of accurately defining the quiescent collector current of the common-emitter-amplifier transistor, the emitter of the common-collector amplifier transistor is supplied bias current from the collector of a constant-current-generator transistor having its emitter-to-base voltage related to that of one of the transistors in the multiple-V.sub.BE supply.

Abstract: The performance of a frequency-tracking filter comprising a phase-locked loop synchronized by square-wave output signal from a limiter amplifier is improved during interruptions in that signal by interposing a level discriminator between the limiter amplifier and the phase comparator element of the phase-locked loop.

Abstract: The difference between the source-to-gate voltages of two MOSFET's with different dopings of the regions in which their respective conduction channels are induced is applied to a resistor to determine the level to which current is regulated in current regulating circuitry embodying the invention.

Abstract: A current divider apportions current applied to the interconnected emitters of a pair of current-dividing transistors as their respective emitter currents in a ratio dependent upon the voltage applied between their bases. A first diode means and a resistor are connected in a series connection, which series connection is in parallel connection with a second diode means. Current is applied to this parallel connection in a poling to forward-bias the first and second diode means which exhibit a difference in offset potentials across said resistor. A voltage directly related to this difference is applied between the bases of the pair of current-dividing transistors to determine the ratio of their emitter currents.

Abstract: Emitter-coupled differential amplifier transistors have their collector currents differentially combined for application to a series regulator transistor in series with a potential divider network having first and second taps to the base electrodes of the emitter-coupled differential amplifier transistors, for completing a feedback loop which develops positive-temperature-coefficient voltages across resistor portions of the potential divider network. These positive-temperature-coefficient voltages augment negative-temperature-coefficient voltages developed across semiconductor diode means included in the potential divider network to provide for zero-temperature-coefficient voltages being developed across the potential divider network or a portion thereof.

Abstract: A composite transistor device is described which comprises a field effect transistor having its transconductance multiplied by the current gain of a current mirror amplifier. The transconductances of such devices can be matched with an accuracy approaching that with which simple field effect transistors can be matched. The higher transconductances of the composite devices make possible a variety of new circuits with distinct performance advantages.