Abstract: An image sensor and a method of manufacturing the same are disclosed. The image sensor includes a plurality of photodiodes on a substrate, an dielectric layer on the plurality of the photodiodes, a metal line layer in the dielectric layer corresponding to a border region between neighboring photodiodes, the metal line layer having a curved backside, a color filter layer on the dielectric layer, and a microlens on the color filter layer.

Abstract: Provided is a method in which a photodiode layer is formed on a metal interconnection layer, and a hard mask layer is formed on the photodiode layer. Then, a photoresist pattern is formed on the hard mask layer to define a contact hole region, and a first hole is formed in the hard mask layer through an etching process. Next, an ion implantation etching layer is formed in the photodiode layer using the photoresist pattern as an ion implantation mask, and a second hole is formed by etching the ion implantation etching layer. A third hole is formed to expose the metal interconnection by etching a region of the metal interconnection layer corresponding to the second hole.

Abstract: Disclosed is a method for placing dummy patterns in a semiconductor device layout. More specifically, the method places the dummy patterns densely between main patterns in accordance with a sequence and configuration. The method includes placing vertical dummies having a greater length than width in a region other than main patterns to form a first layout, removing the vertical dummies within a first distance from the main patterns to form a second layout, placing horizontal dummies having a greater length than width in a vacant space of the second layout to form a third layout, and removing the horizontal dummies within a second distance from the main patterns in the third layout. The method prevents and/or inhibits pattern deformation.

Abstract: A novel concentrator system is described, which increases the efficiency of collecting and concentrating sunlight energy onto a target. This method uses an array of small movable reflective or refractive concentrator components that can move via a feedback mechanism which tracks the sun and concentrates the suns energy on to a second array of energy converting elements. In order to improve the effective collected energy, the array of concentrator elements is placed on a moving or tiltable flat slab (or dish, substrate, plane, plate, holder, tablet, or similar flat or non-flat surface) that tracks the sun. An alternative method uses an array of target elements or linear elements and a second array of concentrator elements in harmony such that the suns energy is efficiently redistributed by the reflective or refractive array on to the energy converting array as the sun's position in the sky (elevation and azimuth) changes.

Abstract: Provided is a method for modeling an ESD breakdown current. According to one variation, a first proportional constant is based on a circumference of the ESD protection device and a second proportional constant based on an area of the ESD protection device. A dual first order equation is derived by sampling circumferences and areas of two ESD protection devices. According to another variation, an equation is defined in which a third value (an ESD breakdown current) is a sum of a first value and a second value, the first value being obtained by multiplying a circumference of an ESD protection device by a first proportional constant, the second value being obtained by multiplying an area of the ESD protection device by a second proportional constant. Then, circumferences and areas of first and second ESD protection samples are calculated. Next, first and second equations are derived by reflecting the first and second circumferences and areas to the equation.

Abstract: Disclosed is an image sensor. The image sensor includes a semiconductor substrate including a lower interconnection, a plurality of upper interconnection sections protruding upward from the semiconductor substrate, a first trench disposed between the upper interconnection sections such that the upper interconnection sections are spaced apart from each other, a bottom electrode disposed on an outer peripheral surfaces of the upper interconnection sections, a first conductive layer disposed on an outer peripheral surface of the bottom electrode, an intrinsic layer disposed on the semiconductor substrate including the first conductive layer and the first trench, and having a second trench on the first trench, a second conductive layer disposed on the intrinsic layer and having a third trench on the second trench, a light blocking part disposed in the third trench, and a top electrode disposed on the light blocking part and the second conductive layer.

Abstract: A LDMOS transistor and a method for manufacturing the same are disclosed. A lateral double diffused metal oxide semiconductor (LDMOS) transistor includes a first dielectric layer formed on a top surface of a substrate; a plurality of second dielectric layers on a top surface of the first dielectric layer; a plurality of contact plugs spaced apart by a predetermined distance in an active region of the substrate, passing through the first and second dielectric layers; and a bridge metal line formed in the second dielectric layers, inter-connecting the contact plugs in a horizontal direction. The bridge metal line formed to inter-connect the contact plugs allows for more current to flow in the presently disclosed LDMOS transistor than in a conventional LDMOS transistor of identical size.

Abstract: An image sensor may comprise circuitry, a first lower electrode, a photodiode, an upper electrode, a second lower electrode, and an upper interconnection. The circuitry may comprise a first lower interconnection and a second lower interconnection over a dielectric of a substrate. The first lower electrode, the photodiode, and the upper electrode may be sequentially formed over the first lower interconnection. The second lower electrode may comprise a passivation layer over the second lower interconnection. The upper interconnection may be formed over the second lower electrode and electrically connected to the upper electrode.

Abstract: Semiconductor devices and/or structures, and methods for fabricating the same are disclosed. Embodiments of the present invention allow for production of customized products, while also minimizing production steps, avoiding some or all photolithography steps, and reducing overall production costs. Using selective deposition and patterning methods such as printing, to form metal and/or dielectric layer(s) on substrates where one or more device circuit components are pre-made in a factory, but which require further processing to obtain an electrically functional circuit, results in the ability for a user/consumer to make custom, specific and/or unique electrically functional circuits without incurring the cost and complexity of a full fabrication to form and pattern all of the layers.

Abstract: Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae SinH2n and SinH2n+2 as well as alkyl- and arylsilanes, to produce soluble silicon polymers as a precursor to silicon films having low carbon content.

Abstract: The present disclosure provides an exposure method for a semiconductor device, in which whether a specific pattern corresponds to a sparse area or a dense area is decided to employ a specific phase-shift mask and by which critical dimension uniformity and resolution of the pattern are enhanced. One example method includes defining a hole area for a plurality of holes into a dense area and a sparse area, coating a photoresist layer on a substrate having a plurality of elements formed thereon, carrying out a first exposure on the photoresist layer using a first photomask having patterns corresponding to the dense and sparse areas, respectively, and carrying out a second exposure on the photoresist layer using a second photomask having at least two halftone layers provided to portions corresponding to the dense and sparse areas, respectively wherein the at least two halftone layers differ from each other in transmitivity, respectively.

Abstract: A bipolar junction transistor and a method of manufacturing a bipolar junction transistor are disclosed. An exemplary bipolar junction transistor includes a second conductivity type base region in a first conductivity type substrate, step-shaped recesses in the base region, a polysilicon layer doped with a first conductivity type impurity in the step-shaped recesses, and a step-shaped emitter region between the polysilicon layer and the base region.

Abstract: Frequency divider circuits and architectures, and methods of implementing and using the same, are disclosed. In one embodiment, the frequency divider circuit includes a dynamic section that receives an input signal and outputs an intermediate signal that has a frequency lower than that of the input signal; and a static section that receives the intermediate signal and outputs a signal having a frequency that is lower than that of the intermediate signal. Stages in the dynamic and/or static section can be implemented using thin film transistors (TFTs). Embodiments of the present invention advantageously provide an approach that takes overcomes problems associated with the leakage and speed characteristics of TFTs.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate having a device isolation region, a first drain spacer on one side of the gate electrode, a second drain spacer next to the first drain spacer, a first source spacer on an opposite side of the gate electrode and a portion of the semiconductor substrate where a source region is to be formed, a second source spacer on side and top surfaces of the first source spacer, and LDDs adjacent to the first drain spacer and below the first source spacers, wherein the LDD below the first source spacer is thinner than the LDD adjacent to the first drain spacer.

Abstract: A stackable container and blanks for forming a stackable container are disclosed. In one embodiment, a stackable container has (a) a base having two pairs of opposed base edges, (b) two first sidewall structures foldably attached to the first base edges at an angle of from about 90 degrees to about 100 degrees, and (c) two second sidewall structures. The second sidewall structures generally each include (i) a wall flap foldably attached to one of the base edges at an angle of from about 90 degrees to about 100 degrees, (ii) an index fold-down flap foldably attached to the wall flap at an angle of about 180 degrees, and (iii) a plurality of inner fold-down flaps foldably attached to the wall flap at an angle of about 180 degrees.

Abstract: An image sensor having greatly improved physical and electrical bonding forces between a photodiode and a substrate, and a manufacturing method thereof. The image sensor includes a semiconductor substrate and readout circuitry, a dielectric layer on the semiconductor substrate, a metal line in the dielectric layer, electrically connected with the readout circuitry, an image sensing device including first and second impurity regions on the dielectric layer, a via hole through the dielectric layer and the image sensing device, a hard mask in the via hole, and a lower electrode in the via hole to connect the first impurity region with the metal line.

Abstract: A semiconductor device and a method of manufacturing the same. The method includes preparing a semiconductor substrate having high-voltage and low-voltage device regions, forming a field insulating layer in the high-voltage device region, forming a first gate oxide layer on the semiconductor substrate, exposing the semiconductor substrate in the low-voltage device region by etching part of the first gate oxide layer and also etching part of the field insulating layer to form a stepped field insulating layer, forming a second gate oxide layer on the first gate oxide layer in the high-voltage device region and on the exposed semiconductor substrate in the low-voltage device region, and forming a gate over the stepped field insulating layer and part of the second gate oxide layer in the high-voltage device region adjoining the field insulating layer.

Abstract: Printable metal formulations, methods of making the formulations, and methods of coating or printing thin films from metal ink precursors are disclosed. The metal formulation generally includes one or more Group 4, 5, 6, 7, 8, 9, 10, 11, or 12 metal salts or metal complexes, one or more solvents adapted to facilitate coating and/or printing of the formulation, and one or more optional additives that form (only) gaseous or volatile byproducts upon reduction of the metal salt or metal complex to an elemental metal and/or alloy thereof. The formulation may be made by combining the metal salt(s) or metal complex(es) and the solvent(s), and dissolving the metal salt(s) or metal complex(es) in the solvent(s) to form the formulation. Thin films may be made by coating or printing the metal formulation on a substrate; removing the solvents to form a metal-containing precursor film; and reducing the metal-containing precursor film.

Abstract: An organizer/storage system that mounts on top of a computer workstation for storage of office supplies, devices, or files that makes efficient use of the available space above, or on one or both sides of the computer workstation. The organizer/storage system includes a top platform and side panels, and may include back and bottom panels with interlocking closure systems, and slide-in shelves with optional drawers. Optional cutouts in the side panels allow airflow to cool the computer, and optional cutouts in the back panels permit connection of conduit or electrical wires. When adaptive fasteners are used for attachment to the computer workstation, the height of the organizer/storage system may be adjusted. Exterior side shelves may be attached to one or both of the side panels to permit storage of a greater variety of objects. The organizer/storage system may be made from a single sheet of suitable material.

Abstract: An electrically erasable programmable read only memory (EEPROM) is disclosed. The EEPROM includes a tunneling region in a semiconductor substrate, a control gate region in the semiconductor substrate and separated from the tunneling region by a device isolating layer, a tunnel oxide layer in a trench in the semiconductor substrate between the tunneling region and the control gate region, and a polysilicon layer on the tunnel oxide layer.