Patents Represented by Attorney Andrew D. Fortney
  • Patent number: 8057865
    Abstract: Polysilanes, inks containing the same, and methods for their preparation are disclosed. The polysilane generally has the formula H—[(AHR)n(c—AmHpm?2)q]—H, where each instance of A is independently Si or Ge; R is H, —AaHa+1Ra, Halogen, aryl or substituted aryl; (n+a)?10 if q=0, q?3 if n=0, and (n+q)?6 if both n and q?0; p is 1 or 2; and m is from 3 to 12. In one aspect, the method generally includes the steps of combining a silane compound of the formula AHaR14?a, the formula AkHgR1?h and/or the formula c—AmHpmR1rm with a catalyst of the formula R4xR5yMXz (or an immobilized derivative thereof) to form a poly(aryl)silane; then washing the poly(aryl)silane with an aqueous washing composition and contacting the poly(aryl)silane with an adsorbent to remove the metal M. In another aspect, the method includes the steps of halogenating a polyarylsilane to form a halopolysilane; and reducing the halopolysilane with a metal hydride to form the polysilane.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: November 15, 2011
    Assignee: Kovio, Inc.
    Inventors: Wenzhuo Guo, Vladimir K. Dioumaev, Joerg Rockenberger, Brent Ridley
  • Patent number: 8059478
    Abstract: Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second non-volatile memory. An integrated circuit is independently functional upon separation from the cluster if the codes in the first and second non-volatile memories match. Upon separation, integrated circuits are queried to determine which respond. Each integrated circuit includes logic adapted to determine whether the codes in the first and second non-volatile memories match. If the codes do not match, the logic permanently disables the integrated circuit upon separation from the cluster.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: November 15, 2011
    Assignee: Kovio, Inc.
    Inventor: Roger G. Stewart
  • Patent number: 8048307
    Abstract: The present invention generally relates to a filtration system having one or more apparatuses for filtering gases, liquids, or fluids (e.g., water) to remove particulate matter, and methods of making and using the apparatus. More particularly, embodiments relate to apparatuses and methods for applying centrifugal force(s) to push a fluid or gas to be filtered through a porous membrane or filter within the apparatus to separate particulate matter therefrom. The present invention takes advantage of the Coriolis effect within a cylindrical filter radiating out from a rotating central body. The filtration apparatus provides an energy efficient system for microfiltration (or other filtration process) to remove contaminants from gases and fluids, such as waste water.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: November 1, 2011
    Inventor: Brent Lee
  • Patent number: 8049265
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device comprises: a floating gate pattern formed in a cell area of a semiconductor substrate; a dummy floating gate pattern extending from the floating gate pattern into an interface area around the cell area; and a control gate pattern intersecting the floating gate pattern at the cell area of the semiconductor substrate.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: November 1, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Ji Ho Hong
  • Patent number: 8049257
    Abstract: Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging. The CMOS image sensor may include: a semiconductor substrate; at least one photodiode on or in the semiconductor substrate; a first insulating layer on the substrate including the photodiode(s); a plurality of metal lines on and/or in the first insulating layer; a second insulating layer on the first insulating layer including at least some of the metal lines; a patterned light shielding layer on the second insulating layer; and microlenses in a remaining space on the second insulating layer.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: November 1, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang Gi Lee
  • Patent number: 8048744
    Abstract: A semiconductor device and fabricating method thereof are disclosed. The method includes forming a polysilicon layer on a semiconductor substrate including a high-voltage area and a low-voltage area, partially etching the polysilicon layer in the low-voltage area, forming an anti-reflective layer on the polysilicon layer to reduce a step difference between the high-voltage and low-voltage areas, forming a photoresist pattern in the high-voltage and low-voltage areas, and forming a high-voltage gate and a low-voltage gate by etching the polysilicon layer using the photoresist pattern as an etch mask.
    Type: Grant
    Filed: November 27, 2009
    Date of Patent: November 1, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Dong Woo Kang
  • Patent number: 8049289
    Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a semiconductor substrate including a unit pixel, first to third color filters provided on the semiconductor substrate, a first micro-lens provided on each of the first and third color filters, and a second micro-lens provided on the second color filter, in which an outer periphery of the first micro-lens has a square shape, and an upper portion of the first micro-lens has a semi-spherical or convex shape.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: November 1, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Seung Ryong Park
  • Patent number: 8050329
    Abstract: A generic spatially-scalable shape encoding apparatus and method for handling different mask decomposition methods, while maximizing coding efficiency of the encoder, is disclosed. The present generic spatially-scalable shape encoding applies three encoding steps to maximize the coding efficiency of the encoder, i.e., mask mode encoding, base mask layer coding and enhancement mask layer coding.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: November 1, 2011
    Assignee: MediaTek Inc.
    Inventor: Shipeng Li
  • Patent number: 8030116
    Abstract: A CMOS image sensor and a method for fabricating the same are disclosed. The method includes forming a plurality of color filters on a substrate, each color filter having a curvature, and forming microlenses on the color filters that each has a radius of curvature that varies with the wavelength of the color filter on which it is formed.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: October 4, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Sung Ho Jun
  • Patent number: 8030117
    Abstract: A method for manufacturing an image sensor includes forming first to third photodiodes and first to third color filters corresponding thereto; forming a photoresist film including photosensitive materials on the upper surfaces of the first to third color filters; forming a first exposed part by exposing the photoresist film with a first exposure energy using a first pattern mask with a first light transmitting part having a first width at boundaries between the individual color filters; forming a second exposed part overlapping a portion of the first exposed part by exposing the photoresist film with a second exposure energy smaller than the first exposure energy using a second pattern mask with a second light transmitting part having a second width wider than the first width; and forming microlenses by developing the photoresist film.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: October 4, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Young Je Yun
  • Patent number: 8021946
    Abstract: A nonvolatile (e.g., flash) memory device includes a substrate having a plurality of isolation areas and active areas; a trench formed on the isolation area; a first electrode layer formed on an inner wall of the trench; a first gate oxide layer formed between the inner wall of the trench and the first electrode layer; a junction area formed on the active area; a second gate oxide layer formed on the entire surface of the substrate including the first electrode layer, the first gate oxide layer, the trench and the junction area; a tunnel oxide layer formed on a part of the second gate oxide layer corresponding to the active area; and a second electrode layer formed on the active area and in the trench.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: September 20, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Heong Jin Kim
  • Patent number: 8022483
    Abstract: A semiconductor device and a manufacturing method for the same are disclosed. The semiconductor device includes a gate pattern formed at an upper part of the semiconductor substrate to overlap one side of a drift region, and a shallow oxide region disposed adjacent to the gate pattern, having a shallower depth than a plurality of device isolation layers.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: September 20, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Kwang Young Ko
  • Patent number: 8022480
    Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes at least two of first and second conductive-type high-voltage transistors and first and second conductive-type low-voltage transistors. The first conductive-type high-voltage transistor include a first conductive-type well in a semiconductor substrate, a device isolation film in the first conductive-type well, a gate pattern on the first conductive-type well, second conductive-type drift regions in the semiconductor substrate at opposite sides of the gate pattern, second conductive-type source and drain regions in the second conductive-type drift region, a pick-up region to receive a bias voltage, and a first latch-up inhibiting region under the pick-up region. Accordingly, it is possible to reduce and prevent latchup without using a double guard ring and to eliminate an additional process to form first and second latch-up inhibiting regions.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: September 20, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: San Hong Kim, Jong Min Kim
  • Patent number: 8015533
    Abstract: A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: September 6, 2011
    Assignee: Golden Gate Technology, Inc.
    Inventors: Michael Burstein, Boris Ginzburg, Andrew Nikishin
  • Patent number: 8000583
    Abstract: Methods, software, apparatus, and systems for reading a recordable optical disc. The method generally comprises the steps of (a) determining whether a lead-in area on the disc contains valid lead-in data and, when the lead-in area does not contain valid lead-in data, and (b) searching an area on the disc (e.g., searching for directory data, such as RSAT or VAT data). The present invention advantageously allows a disc playback device (e.g., a DVD player) to locate disc type information even on discs that are unfinalized (e.g., where no lead-in data has been recorded in the lead-in area of the disc).
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: August 16, 2011
    Assignee: MediaTek Inc.
    Inventors: Shui-Hsiang Ho, Yuan-Ching Lin
  • Patent number: 7994018
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a first oxide film, a nitride film, and a second oxide film on a semiconductor substrate in succession, etching the second oxide film and the nitride film to form a second oxide film pattern and a nitride film pattern, exposing a portion of the first oxide film, performing at least one nitrogen implantation into the semiconductor substrate to form a nitrogen injection region under the exposed portion of the first oxide film, forming a third oxide film over the second oxide film pattern, the nitride film pattern, and the semiconductor substrate, forming a trench that is deeper than the nitrogen ion injection region by etching the semiconductor substrate using the second oxide film pattern as a mask, and filling the trench with an oxide film to form a device isolating film.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: August 9, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Doo Sung Lee
  • Patent number: 7994013
    Abstract: A semiconductor device comprises a gate electrode on a semiconductor substrate, drift regions at opposite sides of the gate electrode, source and drain regions in the respective drift regions, and shallow trench isolation (STI) regions in the respective drift regions between the gate electrode and the source or drain region, wherein the drift regions comprise first and second conductivity-type impurities.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: August 9, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Jae Hyun Yoo, Jong Min Kim
  • Patent number: 7994591
    Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a gate structure which includes a silicon oxynitride (SiON) layer formed on a semiconductor substrate, a hafnium silicon oxynitride (HfSiON) layer formed on the silicon oxynitride (SiON) layer, a polysilicon layer formed on the hafnium silicon oxynitride (HfSiON) layer, and a silicide layer formed on the polysilicon layer, spacers at sidewalls of the gate structure, and source and drain regions at opposite sides of the gate structure.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: August 9, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eun Jong Shin
  • Patent number: 7994554
    Abstract: Disclosed are a CMOS image sensor and a manufacturing method thereof.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 9, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chang Hun Han
  • Patent number: 7989908
    Abstract: Provided is an image sensor. The image sensor includes a semiconductor substrate, photodiode structures, color filters, and microlenses. The semiconductor substrate includes a first region having pixel regions and a second region around the first region. The pixel regions are arranged in a matrix configuration. Each of the photodiode structures has a photodiode in each of the pixel regions. The color filters are disposed on or over the photodiode structures, the color filters correspond to the pixel regions, respectively, and have different areas corresponding to incident angles of light.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: August 2, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Seoung Hyun Kim