Abstract: Compositions, inks and methods for forming a patterned silicon-containing film and patterned structures including such a film. The composition generally includes (a) passivated semiconductor nanoparticles and (b) first and second cyclic Group IVA compounds in which the cyclic species predominantly contains Si and/or Ge atoms. The ink generally includes the composition and a solvent in which the composition is soluble. The method generally includes the steps of (1) printing the composition or ink on a substrate to form a pattern, and (2) curing the patterned composition or ink. In an alternative embodiment, the method includes the steps of (i) curing either a semiconductor nanoparticle composition or at least one cyclic Group IVA compound to form a thin film, (ii) coating the thin film with the other, and (iii) curing the coated thin film to form a semiconducting thin film.

Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

Abstract: A semiconductor device and fabrication method thereof are disclosed. An example semiconductor device includes a semiconductor substrate having a device isolation area defining an active area; a gate oxide layer formed on the active area of the substrate; a gate on the gate oxide layer; a spacer provided to a sidewall of the gate; and a well region provided within the active area. The well region includes a threshold voltage adjustment doped region, a halo region, a source region, a drain region, an additional doped region, and a channel stop region, the additional doped region provided between the well region and each of the source and drain regions.

Abstract: A method for fabricating a semiconductor device, including forming a gate insulating layer and a gate electrode on a substrate; forming insulating layer sidewalls at sides of the gate electrode; forming source/drain regions in surface portions of the substrate that are located, respectively, at sides of the gate electrode; forming a conductive silicide layer on the entire surface of the substrate; and selectively removing the silicide layer from areas other than the gate electrode and the source/drain regions of the substrate. The conductive silicide layer may be made by forming a silicon layer on an entire surface of the substrate; forming a conductive layer on the silicon layer; and thermal-processing the substrate such that the conductive layer reacts with the silicon layer.

Abstract: A voltage level shifter circuit is provided. A high power voltage is input to a first power voltage terminal, an enable signal is input to an enable terminal, and an intermediate voltage level between the first power voltage and a high enable signal voltage is input to a second power voltage terminal. First and second inverters are connected to the enable terminal. A first transistor has a source connected to the second inverter. A second transistor has a drain connected to a drain of the first transistor, a source connected to the second power voltage terminal, and a gate connected to an output terminal of the first inverter. Third and fourth transistors have gates connected to the outputs of the first and second transistors, the fourth transistor having a source connected to the first power voltage terminal.

Abstract: Methods of fabricating semiconductor devices are disclosed. An illustrated example method protects spacers and active areas by performing impurity ion implantation on an oxide layer prior to etching the oxide layer. The illustrated method includes forming a gate on a semiconductor substrate, forming a spacer on a sidewall of the gate, forming an oxide layer over the substrate, forming a mask on the oxide layer to cover a non-salicide area, implanting impurity ions into a portion of the oxide layer which is not covered by the mask, removing the portion of the oxide layer which is implanted with impurity ions, performing salicidation on the substrate, and removing the mask.

Abstract: A method for manufacturing an inductor according to the embodiment comprises the steps of: forming a first photoresist pattern; forming an impurity region forming the inductor by implanting an impurity ion to the substrate by means of the first photoresist pattern and a pad region applying current across the impurity region; forming a second photoresist pattern so that a position spaced by a predetermined interval from the impurity region is opened; and forming a guard impurity region in the position spaced from the impurity region by implanting the same impurity ion as the impurity ion by means of the second photoresist pattern.

Abstract: Multi-mode (e.g., EAS and RFID) tags and methods for making and using the same are disclosed. The tag generally includes an antenna, an electronic article surveillance (EAS) function block coupled to the antenna, and one or more identification function blocks coupled to the antenna in parallel with the EAS function block. The method of reading the tag generally includes the steps of applying an electric field to the tag, detecting the tag when the electric field has a relatively low power, and detecting an identification signal from the tag when the electric field has a relatively high power. The present invention advantageously enables a single tag to be used for both inventory and anti-theft purposes, thereby improving inventory management and control at reduced system and/or “per-article” costs.

Abstract: In order to diversify a current control method of a semiconductor device, improve performance (including a current drive performance) of the semiconductor device, and reduce a size of the semiconductor device, a second gate may be formed inside a substrate that forms a channel upon applying a bias voltage thereto. In one aspect, the semiconductor device includes: a well region of a first conductivity; source and drain regions of a second conductivity in the well region; a first gate on an oxide layer above the well region, controlling a first channel region of a second conductivity between the source region and the drain region; and a second gate under the first channel region.

Abstract: A method of manufacturing a semiconductor device employs a PEALD method including using an organometallic Ta precursor to form a TaN thin film. As a result, a conformal TaN diffusion barrier may be formed at a temperature of 250° C. or higher, so that impurities are reduced and density is increased in the TaN thin film.

Abstract: Disclosed is a capacitor and method for forming a capacitor in a semiconductor. The method includes the steps of: (a) forming a lower electrode pattern on a silicon semiconductor substrate; (b) etching a portion of the lower electrode pattern to a predetermined depth to form a step in the lower electrode pattern; (c) forming a dielectric layer and a upper electrode layer on an entire surface of the substrate including the lower electrode pattern; and (e) patterning the upper electrode layer and the dielectric layer to form a upper electrode pattern and a dielectric pattern.

Abstract: A calibration circuit including a plurality of first resistance components, a plurality of second resistance components, and a first feedback system is provided. The first feedback system selects M1 first resistance components and N1 second resistance components so that a first combination of the M1 first resistance components and the N1 second resistance components has a first predetermined relationship with the impedance of a first resistor. The first feedback system selects M2 first resistance components and N2 second resistance components so that a second combination of the M2 first resistance components and the N2 second resistance components has a second predetermined relationship with the impedance of the first resistor. Based on the values of M1, N1, M2, N2, and a target impedance, the first feedback system generates a first set of calibration signals for a plurality of third resistance components and generates a second set of calibration signals for a plurality of fourth resistance components.

Abstract: A method of forming a metal line pattern for a semiconductor device is provided. The method includes forming a preliminary structure on a semiconductor substrate, having a lower barrier metal layer, a metal layer, and an upper barrier and/or passivation layer having a first thickness; removing a top surface of the passivation layer so that the passivation layer has a second thickness; forming a sub-passivation layer on the passivation layer; forming an adhesion promoter and a photoresist pattern on the sub-passivation layer; and forming a metal line pattern by etching the preliminary structure using the photoresist pattern as an etching mask.

Abstract: A method of fabricating a vertical CMOS image sensor is disclosed, to improve the integration with the decrease in size of pixel by minimizing the lateral diffusion, in which phosphorous and arsenic ions are implanted while controlling the dose and energy, the method including forming a first photodiode in a semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a first plug by sequentially implanting first and second ions in the first epitaxial layer; forming a second photodiode in the first epitaxial layer; forming a second epitaxial layer in the first epitaxial layer; forming an isolation area in the second epitaxial layer; and forming a third photodiode and a second plug in the second epitaxial layer.

Abstract: Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, and a silicon carbide layer is deposited thereon. A photolithography process is performed, and the silicon carbide layer is etched except for predetermined portions corresponding to source-drain regions and the gate electrode. Then, a metal layer is formed on the resulting structure after performing a source-drain ion implantation process. The metal layer is heated to form a salicide layer on the gate electrode and the source-drain diffusion regions. Then, the unreacted metal layer is removed, thereby forming the MOS transistor.

Abstract: A method of forming a compressive channel layer in a PMOS device and a PMOS device having a compressive channel layer are provided. The method includes (a) forming a buffer oxide layer on a silicon semiconductor substrate having a gate oxide layer and a gate electrode thereon, (b) forming a silicon nitride layer on the buffer oxide layer, (c) implanting impurities into the silicon nitride layer, and (d) etching or patterning the silicon nitride layer and the buffer oxide layer into which impurities are implanted to form gate spacers on sidewalls of the gate electrode.

Abstract: Polysilanes, inks containing the same, and methods for their preparation are disclosed. The polysilane generally has the formula H-[(AHR)n(c-AmHpm-2)q]—H, where each instance of A is independently Si or Ge; R is H, -AaHa+1Ra, halogen, aryl or substituted aryl; (n+a)?10 if q=0, q?3 if n=0, and (n+q)?6 if both n and q?0; p is 1 or 2; and m is from 3 to 12. In one aspect, the method generally includes the steps of combining a silane compound of the formula AHaR14-a, the formula AkHgR1?h and/or the formula c-AmHpmR1fm with a catalyst of the formula R4xR5yMXz (or an immobilized derivative thereof) to form a poly(aryl)silane; then washing the poly(aryl)silane with an aqueous washing composition and contacting the poly(aryl)silane with an adsorbent to remove the metal M. In another aspect, the method includes the steps of halogenating a polyarylsilane to form a halopolysilane; and reducing the halopolysilane with a metal hydride to form the polysilane.

Abstract: An image sensor may comprise photodiodes on a semiconductor; color filters on the photodiodes; a planarization layer covering the color filters; and microlenses on the planarization layer, including alternate hydrophilic microlenses and hydrophobic microlenses contacting the edges of the hydrophilic microlenses, corresponding to respective color filters.

Abstract: There is provided a semiconductor device. The semiconductor device includes a lower electrode, a contact connected to the lower electrode to have a double trench structure, a phase change material layer accommodated in the double trench to cause a phase change between a crystalline state and an amorphous state in accordance with a change in heat transmitted by the contact, and an upper electrode connected to the phase change material layer.

Abstract: Provided is a method for manufacturing an image sensor. The method includes the following. A color filter layer is formed on a semiconductor substrate having a photodiode and a transistor formed thereon. A planarization layer is formed on the color filter layer. An LTO (Low Temperature Oxide) layer is formed on the planarization layer. A photoresist pattern is formed to correspond to the color filter layer on the LTO layer, and a reflow process is performed. A microlens array is formed by reactive ion etching the photoresist pattern and the LTO layer. A second reflow process may be performed on the photoresist pattern and/or the LTO layer during the reactive ion etching process.