Abstract: A data processor having an execution unit and which includes a control means having a first and a second control store. The control means has an input for receiving a control store address. In response to the received control store address, the first control store provides sequencing information at a first output for selecting the next control store address. Also, in response to the received control store address, the second control store supplies control information at a second output for controlling the execution unit. The data processor also includes means for receiving a macroinstruction and selection means responsive to the macroinstruction and to the sequencing information for generating the control store address. In a preferred embodiment, the control store address is received by both the input of the first control store and the input of the second control store. Each control word in the first control store has a unique control store address.

Abstract: A sampled data system having improved (sin X)/X correction is provided. A modified switched capacitor filter is used as a receive filter. The switched capacitor filter is modified in a manner to provide a charge gain thereby avoiding the increase in thermal noise normally associated with voltage gain amplification. The modified switched capacitor filter does not impair the dynamic range of the system and can be made duty cycle independent by providing additional controllable switches to the filter.

Abstract: A read-only-memory circuit is disclosed which includes a plurality of column conductors and circuitry for selecting one of the plurality of column conductors in response to an input address. The selection circuitry couples each of the column conductors to a common node which is coupled to a precharge circuit such that only the selected column conductor is precharged. The precharged circuit includes first and second diode-connected IGFET devices coupled in series such that the first IGFET device is a standard enhancement mode transistor which includes an implanted channel while the second IGFET device is a natural transistor which does not include an implanted channel.

Abstract: An N-channel MOS high voltage detection circuit generates an output when an input voltage (Vin) exceeds a supply voltage (V.sub.DD) by a desired offset voltage. The crossover detection is delayed by pumping more current into an output producing node via a lower resistance field effect transistor having a gate coupled to the input voltage. The output is finally produced when the effect of this transistor is overcome by a second field effect transistor. Switching characteristics may be sharpened by placing a voltage limiting field effect transistor between Vin and the gate of the low resistance field effect transistor.

Abstract: In a high speed synchronizing circuit, the rising edge of an asynchronous input signal is used to set an input RS flip-flop. First and second latch registers monitor the input RS flip-flop. Each latch register generates a reset signal before a change in the logic level of the system clock for resetting the input RS flip-flop. The reset pulses are very narrow which enables the RS flip-flop to be quickly conditioned to receive the next asynchronous signal.

Abstract: A memory array having improved isolation between the bit sense common lines is provided by using diode connected transistors. The diode connected transistors substantially eliminate any current flow between bit sense common lines when a certain portion of the column select circuitry has not been selected. Since the blocking transistors prevent current flow there is no noise generated to be coupled to one of the control lines. This results in a memory array which can operate at higher speeds since better differential signals are established to be sensed by the sense amplifier.

Abstract: A companded stacked DAC is provided which can be used in an A-law or .mu.-law conversion merely by selection. The companded DAC is inherently monotonic and can be integrated with field effect transistors. The current sources of the DAC are switched to only one of two buses. The stacked DAC includes a chord DAC and a step DAC. The two buses which the chord DAC is connected to are maintained at approximately equal voltages by the use of a reference amplifier. The companded DAC uses successive approximation when converting.

Abstract: A data processor which is adapted for microprogrammed operation has a control store includes an ALU and condition code control unit for controlling operations performed by an arithmetic-logic unit within the execution unit of the data processor and for controlling the setting of the condition code bits in a status register. The ALU and condition code control unit is arranged in a row and column format. A decoder coupled to a macroinstruction register selects a row which is selected over an entire period that is required to execute macroinstruction. The row corresponds to a set of operations and condition code settings associated with a particular macroinstruction. The control store output provides information for selecting the proper column during each microcycle used to execute the macroinstruction. ALU function control signals and the condition code control signals are selected simultaneously according to the selected row and column.

Abstract: A microprogrammed control structure for an integrated circuit data processor which employs a two-level control store designated as a micro control store and nano control store. An instruction decoder decodes each macro instruction to be executed by the data processor and causes a series of micro word addresses to be input to the micro control store. In response to such input, the micro control store outputs a corresponding number of nano address words for addressing the nano control store. The nano control store when addressed by the nano address words, outputs a control word to an execution unit for executing the macro instruction.

Abstract: There is provided a reverse battery protection circuit which does not have current limiting resistors to limit current in all portions of the circuit. The protection is obtained by connecting the substrate tubs of N-channel drivers through another N-channel transistor to VSS. The another N-channel transistor has its gate electrode connected to voltage terminal VDD. Accordingly, when reverse voltage is applied to the circuit, VDD will be negative and therefore the another N-channel transistor will not be conductive. This prevents the output driver transistor from becoming a conductive parasitic bipolar transistor.

Abstract: An MOS low voltage detector circuit includes a comparator which compares an internally generated reference voltage with an internally generated non-linear voltage. Both the reference voltage and the non-linear voltage are derived from a supply voltage, and the comparator generates an output whenever the divided down non-linear voltage falls below the reference voltage. This output is supplied to a series of regularly biased MOS inverter stages which not only amplify the comparator output but also amplify the inherent offset error in the comparator itself. Voltage compensating means may also be included in the comparator.

Abstract: A CMOS microprocessor is provided having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static registers. In most cases the registers are connected to two buses. A 5 bit temporary register and an 8 bit program counter are each connected to three buses. An incrementer can provide an increment or decrement function but cannot be used to store functions. A bit code generator is connected to a data bus thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter is capable of directly transferring its contents to the 5 bit temporary register. An 8 bit low order incrementer is capable of incrementing three different registers which are an address storage register, a program counter, and a stack pointer. A 5 bit high order incrementer is also capable of incrementing three registers which are an address storage register, a program counter, and a temporary register.

Abstract: A compensated Schmitt trigger includes first and second balanced current paths between V.sub.DD and ground for establishing the Schmitt trigger's low and high output respectively. The first path includes a first small enhancement device, a second depletion device and a third enhancement device. The second path includes a fourth enchancement device and said second and third devices. Thus, each path includes two enhancement devices and one depletion device. Process variations in each path will tend to track stabilizing the difference between the low and high switching voltages.

Abstract: A data processor having an execution unit employs a segmented bus structure and a dual port register cell in order to increase circuit density and in order to allow address and data computations to occur simultaneously. The circuit is designed to interface with an external 16-bit bidirectional data bus and an external address bus having as many as 32 address bits. Serial bus switches on each of two parallel buses allow concatenation with a second pair of buses. Each bus, while 16 bits wide, actually utilizes two conductors per bit to carry data and the complement thereof.

Abstract: An NMOS power on/low voltage reset circuit provides a substantially instantaneous reset enabling signal when a predetermined fraction of the power supply voltage falls below a predetermined reference voltage. In addition, an external capacitor is discharged. A second reset enabling signal is extended until the capacitor is again charged to a predetermined voltage thus allowing the clock oscillators of a microcomputer sufficient time to stabilize. Self test means are also provided. The reset circuit is implemented on the microcomputer chip.

Abstract: A balanced differential circuit is provided which is useful as an address buffer in digital memories. The circuit is illustrated as a single ended input circuit having complementary outputs. Capacitors are used to couple imbalancing signals into the circuit. Through selective timing of load devices within the circuit power dissipation is kept to a minimum.

Abstract: A bandgap voltage reference source is provided which is temperature stable or temperature controlled and can be made by standard CMOS process. The reference has two substrate bipolar transistors with the emitter current density of one of the transistors being larger than the emitter current density of the other transistor. The transistors are used as emitter followers having resistors in their emitter circuits from which an error voltage is obtained. The error voltage is amplified through a differential or operational amplifier. Through the amplifier or through a resistor network, an output voltage higher or lower, respectively, than the bandgap voltage can be obtained. The output voltage can be made to have a positive, negative, or zero temperature coefficient.

Abstract: There is provided a microprocessor interface circuitry which allows single peripheral and memory devices to be used with at least two different types of microprocessors. The interface includes a latch which latches the state of a control signal provided to the peripheral/memory device by the microprocessor. The control signal that is latched serves a somewhat different function when eminating from each of the at least two different microprocessors, and as such has different logic states. Logic circuitry is controlled by the latch to take at least one other control signal and generate the internal control signals used by the peripheral/memory device.

Abstract: An MOS logic circuit is provided which generates and latches an output signal at a given logic level upon detection of a given transition in an input signal coinciding with a given state of a clock signal. The circuit utilizes the capacitance inherent in an MOS structure. The circuit requires a minimum of MOS components and is therefore useful in high density MOS integrated circuits where it is desired to detect and latch a transition in a signal.The edge sense latch comprises an MOS inverter (Q1, Q2) responsive to an input signal S, a transmission gate (Q3) controlled by a clock signal, a transmission gate (Q4) controlled in part by an inherent capacitance (29), a latch comprising a pair of cross-coupled MOS transistors (Q5, Q8) for generating an output signal Q, and an MOS transistor (Q6) responsive to a reset signal R.

Abstract: A microprocessor comprises an internal address bus having a first portion (2,4) having a plurality of conductors carrying the low order address byte and a second portion (10) having a plurality of conductors for carrying the high order address byte. The microprocessor further comprises a plurality of registers, including an incrementor (12,13), a program counter (14,15), a temporary register (16,17), a stack pointer (18,19), an index register (20,21), and an accumulator (22,24), each comprising a pair of 8-bit registers for temporarily storing information. An arithmetic logic unit (28) performs computational operations on digital information within the microprocessor. The microprocessor includes a pair of internal data buses (6,8) each having a plurality of conductors for conducting digital information within the microprocessor. Means are provided for coupling selected ones of the registers, or the high or low order portions thereof, to the first and second data buses.