Abstract: An interface device to provide a data and address path between a data processor, a memory and peripheral devices. The interface device includes an internal arithmetic and logic unit to provide a means for generating and/or modifying addresses for the memory or peripheral devices. The device further includes a plurality of registers for temporarily storing data or addresses as well as information associated with addressing functions, for example, program counter, index register, stack pointer and page addresses. The interface device may be used singly or in combination with like devices as in a slice processing system.

Abstract: An instruction set modifier register, comprising one or more bistable latches which are loadable under program control, is provided for use in a processor in conjunction with an instruction register. An instruction decoding circuit and an instruction execution control logic circuit, responsive to both the instruction register and the instruction set modifier register, generate a first set of control signal combinations corresponding to a first instruction set when the instruction set modifier register is in a first state and generate a second set of control signal combinations corresponding to a second instruction set when the instruction set modifier register is in a second state. The processor is thus able to execute more than one set of instructions, utilizing the same instruction decoding circuitry and instruction execution control logic circuitry.

Abstract: A method and an apparatus are disclosed for converting an analog input signal having either a positive or negative polarity into a digital output signal indicating the magnitude and polarity of the input signal. Amplifier offset voltages and dynamic hysteresis in the comparator are compensated automatically and a zero reference is established automatically to provide a corrected output. A compensation capacitor and an integrating capacitor are selectively charged. A reference signal is integrated to measure the magnitude of the difference between the integrator offset voltage and the comparator threshold. A digital representation of the time required to measure the difference between the integrator offset voltage and the comparator threshold is stored. The compensation capacitor and the integrating capacitor are again selectively charged. The analog input signal is then integrated for a fixed time. The reference signal is integrated for a time equivalent to the digitally stored time.

Abstract: A data processing system in which a central processor polls one or more peripheral devices to initiate a data transfer or to enable a data transfer. The system includes logic associated with a peripheral device or with an interface device for sensing the occurrence of data handling errors such as parity errors, carrier loss, clear to send loss, data overrun or underflow, and for interrupting the central processor upon such occurrence to avoid polling that peripheral device unnecessarily. A status signal is also generated to inform the processor of the nature of the interrupt, so as to distinguish from, for example, the interrupt of another device which is operative to communicate by means of such interrupt rather than by polling.

Abstract: An adder provides either binary or binary coded decimal operation under the selection of a control input. The data inputs are a pair of four bit operands and a carry in for providing an additional capability of greater than four bits. Outputs, in addition to the four bit result, include carry propagate and carry generate signals for the four bit group. Binary operation is conventional. For binary coded decimal operation, the adder corrects an initial binary result to the binary coded decimal format by adding six when there is a group carry generate signal present thus forming an intermediate result. This intermediate result is formed before the occurrence of the carry in from a preceding stage. In the final stage of the adder, the intermediate result is incremented to form the final four bit result if there is a carry in.

Abstract: A carrier correction circuit accepts a serial digital data input stream having an underlying carrier frequency associated with it and generates a corrected carrier signal synchronized with the underlying carrier frequency. The input stream may, for example, be a serial output of an analog-to-digital converter having a differential phase shift keyed analog signal applied to its analog input, the underlying carrier frequency being the carrier frequency of the DPSK signal. The carrier correction circuit includes a phase detector which receives the serial digital data input stream and two representations of the recovered carrier which are shifted in phase from each other by 90.degree.. Each of these representations of the recovered carrier is mixed with the serial digital data input stream by means of first and second mixer circuits, and the results are loaded into first and second serial accumulators, which accumulate, respectively, the average products of the two mixer circuits over a certain time period.

Abstract: A programmable timer module (PTM) is provided as a component of a microprocessor system in order to generate and measure varying time intervals under program control. The programmable timer module includes, in one embodiment, three independent 16-bit timers. Each timer includes a 16-bit counter and a 16-bit latch. The programmable timer module also includes an 8-bit status register and an 8-bit control register each of which may be coupled to an 8-bit bidirectional data bus of a microprocessor system. Selection circuitry is provided which permits the microprocessor to select either the control register or the status register. Information can be written into the control register; the operation is effected by means of read/write circuitry and a read/write input. Any one of the three timers can also be selected by means of the selection circuitry, and a 16-bit number can be written into the selected 16-bit latch.

Abstract: A control memory address generation device, for use as a single device or in a slice environment, performs logical and/or data path selection functions with respect to control information from an arithmetic and logic unit or a control word field, or both, to generate the next control memory address. A flexible register organization and extender bus logic allows subroutining control, instruction or subroutine repetition, masking, branching (conditional or unconditional), and other address-related operations.

Abstract: A dual port memory cell suitable for use in emitter coupled logic applications is accessible from two different address ports. The dual port storage cell includes first and second cross coupled cells, each including a selection conductor and a pair of diodes coupled to the cross coupled transistors to effect selection of that storage cell. The base of each of the cross coupled transistors of the first storage cell is coupled to the base of a coupling transistor, the emitter of which is connected to the base of a corresponding transistor of the other storage cell. Each dual port memory cell has two pairs of bit lines, one pair being coupled to the first storage cell and the other being coupled to the second storage cell. If one of the storage cells is selected, and the other remains unselected, the information in the selected cell is automatically written into the unselected storage cell.

Abstract: A high-speed voltage subtractor circuit suitable for use in a serial-parallel A/D converter uses differential current switches to select a predetermined reference voltage value as one input to a precision current matching circuit whose other input is an applied analog input signal. An output buffer circuit coupled to the current matching circuit produces an output signal equal to the difference between the analog input signal and the reference voltage value.

Abstract: An analog to digital converter for converting an analog input voltage into a four most significant bit group and a four least significant bit group of digital outputs at a first and a second group of output terminals. The complete analog to digital converter includes a first analog to digital converter for converting the analog input voltage into a four most significant bit group of digital outputs at the first group of output terminals. A digital to analog converter which is coupled to the first group of output terminals converts the four most significant bit group of digital outputs into a first analog current which is proportional to the magnitude of the four most significant bit group of digital outputs and into a second analog current such that the sum of the first and the second analog currents is a constant.

Abstract: A sense-write circuit for use with a emitter coupled logic memory array is provided. A first differential stage includes a pair of emitter-coupled transistors connected to a current source controlled by a chip select voltage. A first one of the emitter-coupled transistors has its base connected to a first reference voltage and the second one of said transistors has its base coupled to a write enable input. The collector of a first one of the emitter-coupled transistors serves as a current source for a second differential stage including a second pair of emitter-coupled transistors, a first one having its base connected to a second reference voltage and the second having its base coupled to a data input conductor. The two respective outputs of the second differential stage are coupled to emitter follower drivers, and are also independently coupled through a pair of respective diode-connected transistors to the collector of the first transistor of the first emitter coupled pair.

Abstract: An N-channel field effect transistor microprocessor includes an arithmetic logic unit, a plurality of working registers and address generating circuitry coupled to an internal bus. Control circuitry is coupled to the arithmetic logic unit, the working registers, and the address generating circuitry for producing control signals for controlling operation of the arithmetic logic unit, the working registers, and the address generating circuitry. The microprocessor requires only a single external power supply, and includes means connected to the external power supply for providing electrical energy to the working registers, the arithmetic logic unit, the control circuitry, and the address generating circuitry in order to effect operation thereof.

Abstract: A first-in-first-out memory system is described in which the storage array is made up of single rank storage elements. Control logic means provide for sequencing the transfer of data within the storage array such that transfer can occur only between adjacent groups of storage elements for which a status record shows an empty data word preceded by a full data word.

Abstract: A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

Abstract: An MOS analog to digital converter circuit is provided in which an MOS enhanced capacitor is interposed between a buffer circuit responsive to an analog input and a digital output. The capacitance value present between the first terminal and the second terminal of the MOS enchanced capacitor is determined by the particular value of analog input voltage applied via the input buffer circuit. An oscillator pulse coupled to a second terminal of the enhanced capacitor produces a resultant pulse on the first terminal of the enhanced capacitor which in turn is coupled to an input of digital comparator circuits which are part of the digital output means. A series of reference voltages coupled to the other inputs of the digital comparator circuits allow the generation of a series of digital output signals whose value is indicative of the value of analog input signal present, thus accomplishing the analog to digital conversion function.

Abstract: A digital noise blanking circuit for use in generating a single output pulse in response to a noisy signal which may include clusters of noise-induced pulses, the circuit utilizing a digital counter which is operated for a preset period of time longer than the time during which noise-induced transitional pulses may occur.

Abstract: A digital logic circuit synchronizing data transfers between asynchronously clocked data systems. Synchronization is accomplished by three logically interlocked storage elements which respectively record and control (1) the time when data is available for transfer, (2) time when data transfer begins and (3) the time when data transfer is complete. Transfer is accomplished without a loss of data independent of the clock pulse width and frequency relationship of the asynchronously clocked systems.

Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, the data direction register and a data register. Data from the peripheral data bus the data direction register and the control register are transferred via the output bus to the data bus buffers.

Abstract: A digital tone decoder includes means for generating a timing signal, zero crossing counter means for generating a decode signal after a predetermined number of zero crossings in response to an incoming time domain signal and for generating a reset signal at a predetermined time after the decode signal is sent to reset said zero crossing counter means to zero, and decoder means coupled to said zero crossing counter and to said timing means for generating an output signal at one of a plurality of output terminals corresponding to the frequency of the incoming signal upon receipt of the decode signal from said zero crossing counter means, said decoder means being reset to an initial state upon receipt of the reset signal.