Abstract: A data and clock recovery system for capturing and processing serial data of a type wherein data bits of an unknown format are interleaved with clock bits utilizes a phase lock loop capable of being operated in a capture mode or a tracking mode. The data stream is compared with an internally generated reference signal, and error pulses having widths proportional to the phase error are generated. In the capture mode, these error pulses are differentially processed to produce a control voltage which varies the frequency of a VCO which in turn alters the reference frequency. In the tracking mode, phase error pulses of fixed widths are processed only if the data bits occur in fixed windows. Differential amplifying means provide adjustable gain control of the error pulses. Means are provided for digitally controlling the loop's dynamic response when switching between the capture and tracking modes.

Abstract: A single-chip microcomputer includes a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic includes a control and status register (46), one bit (WU) of which may be utilized, when the microcomputer is connected in a distributed processing system having a shared serial communication line, to indicate that the CPU wishes to ignore a message not of interest to it. When the serial communication line again becomes free, the WU control bit is reset, enabling the CPU to intercept a new message of interest.

Abstract: A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely SDLC, HDLC, and ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Abstract: A substrate bias regulator useful for controlling a variable output oscillator and/or a substrate bias voltage generator is provided to control the substrate voltage on a semiconductor chip. A series of field effect transistors are arranged in a manner to sense the substrate voltage and to provide an output to regulate the substrate voltage. One of the series field effect transistors has its gate electrode connected to reference potential ground which tends to make the regulator independent of transistor thresholds.

Abstract: A temperature stable bandgap voltage reference source utilizing bipolar transistors biased at different emitter current densities is provided. Switched capacitors are used to input the V.sub.be and the .DELTA.V.sub.be of the transistors (PTC and NTC voltages, respectively,) into an operational amplifier to provide a reference voltage proportional to the sum of the PTC and NTC voltages. Proper selection of the ratio of the switched capacitors renders the reference voltage substantially independent of temperature. In a modified form of the reference, the reference amplifier is implemented by an auto-zeroed operational amplifier which uses switched capacitor techniques and an integrated capacitor to achieve the auto-zeroing function.

Abstract: A CMOS static ALU is capable of selecting one operand from a plurality of inputs and can perform various arithmetic and logic operations in addition to shift left and shift right operations. The ALU uses exclusive OR gates having a minimum number of transistors. In addition, more N-channel transistors are used than P-channel transistors which results in overall smaller size and faster operation. In addition, the ALU has a RAM cell for use as a temporary storage means which is capable of driving the ALU data bus.

Abstract: An integrated circuit data processor receives interrupt level signals from external circuitry which represent a priority level associated with the external circuitry. These signals are compared with signals representing the current operating level of the processor, and an interrupt pending output is generated if (1) the priority level is higher than the operating level; or (2) a maximum priority level is received. Upon the occurrence of the interrupt pending output, the current instruction program is interrupted, and an instruction program associated with the external circuitry is executed. The processor transmits a signal back to the external circuitry indicating that the interrupt request has been granted and receives a vector number from the external circuitry. A first acknowledgment signal from the external circuitry causes the vector number to be latched in the processor. A second acknowledgment signal from the external circuitry causes a vector to be internally generated.

Abstract: A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and various power supply, clock, and control inputs. One of the I/O ports (13) is user programmable by application of specific signals to mode selection pins (P20-22) for configuration in several possible ways. The programmable port comprises a plurality of lines which each may be individually programmed as input or output lines to peripheral equipment associated with the microcomputer. Alternatively, the port lines can be programmed to serve as a bidirectional data bus to external memory. Alternatively, the port lines can be programmed to be multiplexed data and address lines to external memory. Bus arbitration logic is provided to route data to the CPU from either on-chip memory or external memory.

Abstract: Each channel of a priority encoder register is equipped with a latch for storing one bit of a binary data word. The channel of highest priority generates an output which is applied to encoding means which in turn generates a unique code. The channel output is also fed back to reset its associated latch to permit the channel of next highest priority to generate an output.

Abstract: An integrated circuit microprocessor includes storage means coupled to a control unit for receiving from the control unit information regarding how the next bus cycle is to be run. Upon receipt of a bus error signal from a peripheral device, the storage means is reset. If, however, a halt signal accompanies the bus error signal, the storage means is not reset and the bus cycle is rerun when the halt signal terminates.

Abstract: In a successive-approximation charge-redistribution analog-to-digital converter which includes a binary weighted capacitive ladder network, an unknown analog input voltage is sampled only on the largest capacitor representing half the capacitance. The conversion phase proceeds utilizing all the capacitance and only half the reference voltage. This not only reduces circuit complexity, but also reduces problems associated with disruption of the charge stored on the capacitor.

Abstract: A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely SDLC, HDLC, and ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Abstract: An MOS voltage boost circuit includes a first field-effect-transistor coupled between ground and an output node and a second, depletion type, field effect transistor coupled between the output node and a source of supply voltage (V.sub.DD). The first transistor is turned off by a disabling signal, and the second transistor is turned on by an enabling signal derived, in part, from the disabling signal. This produces a first voltage at the output node. A third field-effect-transistor is capacitively coupled between the output node and the enabling signal to boost the output voltage when the enabling signal terminates.

Abstract: A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic is capable of handling serial communications in either the NRZ or Manchester (biphase) format. The result is more versatile and more reliable serial communications.

Abstract: A single slope analog to digital converter uses a DAC to trim the discharge current of a capacitor during calibration thereof. A method of calibrating the analog to digital converter is provided which iterates required steps to obtain a correct current setting within a short period of time. The analog to digital converter discharges a capacitor through a high impedance to obtain a linear discharge. The time to discharge the capacitor appears in a counter and is indicative of the voltage across the capacitor at the beginning of the discharge period once the analog to digital converter has been calibrated.

Abstract: A bias current reference circuit is disclosed having a diode-connected bipolar device connected in series with an MOS device to develop a reference voltage which is proportional to a bias current. The reference voltage is used by an MOS device connected in series with a resistor to develop a reference current which is proportional to the reference voltage. The reference current is used by a diode-connected MOS device to develop a bias voltage which is proportional to the reference current. The bias voltage in turn is used by another MOS device to develop the bias current in proportion to the bias voltage. The bias voltage is also used by other MOS devices to provide similar bias currents. In the disclosed embodiment, such a bias current is used by a complementary diode-connected MOS device to develop a complementary bias voltage. The complementary bias voltage may be used to develop start-up bias current in the event the bias current reference circuit fails to provide a suitable bias voltage.

Abstract: A data processor which includes an instruction register for storing a macroinstruction to be executed, a decoder responsive to the stored macroinstruction for generating two or more starting addresses, and a selector which receives the starting addresses generated by the decoder and which selects one of the starting addresses as a next address in response to one or more selection signals. The data processor also includes a control structure which receives the next address chosen by the selector and which selects one of the starting addresses as a next address in response to one or more selection signals. The data processor also icludes a control structure which receives the next address chosen by the selector and which, in response to the next address, derives the selection signals to which the selector will respond in order to select a subsequent next address.

Abstract: A data processor having a microprogrammed control store and including a conditional branch control unit for receiving selection bits output by the control store, selection bits from an instruction register, and conditional signals for generating a two-bit result which, when added to a base address, can specify one of two, three, or four branch destinations in the control store. The selection bits output by the control store determine whether the combination of conditional signals upon which the branch is dependent is selected by the control store or is selected directly by a bit field in the macroinstruction. Also, one of the selection bits output by the control store is used to select one of two possible output codes for the two-bit result associated with a particular branch destination.

Abstract: A driver circuit suitable for use in an operational amplifier, includes a bipolar pull-up transistor which sources current to an output terminal in proportion to an applied drive current, and an MOS pull-down transistor which sinks current from the output terminal in proportion to an applied control voltage. An MOS drive transistor provides a constant drive current for the pull-up transistor, and an MOS shunt transistor shunts the drive current away from the bipolar transistor in proportion to the control voltage. A cross-over compensation circuit develops a predetermined bias voltage on the base of the bipolar transistor relative to the voltage on the output terminal, to assure a minimum level of operation of the bipolar transistor when the output terminal is near the analog ground voltage.

Abstract: A single-chip microcomputer comprises a central processor unit (100), a random access memory (110), a read only memory (120), internal timing circuitry including a timer counter (131), and three I/O data ports (140, 150, and 160). Included within the instruction set of the microcomputer are a branch on bit set instruction and a branch on bit clear instruction. The branch on bit set instruction is a three-byte instruction in which the first byte represents the op code including a designation of a particular bit to be examined, the second byte represents the address of a memory location in which the designated bit is to be examined, and the third byte represents an offset which when combined with the contents of the program counter designates a memory location to which a branch is to be taken if the designated bit is in fact set. For the branch on bit clear instruction, a branch is performed when the particular bit examined is determined not to be set.