Abstract: In one aspect of the present invention, a method for controlling the operation of a phase locked loop circuit is provided. The method is comprised of monitoring a frequency of a system clock, and a first signal is delivered in response to the detected frequency of the system clock being greater than a preselected setpoint. A second signal is delivered in response to the detected frequency of the system clock being less than a preselected setpoint. A first operating mode of the phase locked loop circuit is selected in response to receiving the first signal. The first mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a first preselected range of frequencies. A second operating mode of the phase locked loop circuit is selected in response to receiving the second signal. The second mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a second preselected range of frequencies.

Abstract: A power sub-system controls a supply of power to a field replaceable unit for electronic equipment. The power sub-system includes a power controller that is arranged, in response to the detection of a fault, to switch off the supply of power to a field replaceable unit. The power controller is then responsive to a sequence of two events to switch on the supply of power to the field replaceable unit. The first event is a first change in state of an interlock signal indicative of the field replaceable unit being released. The second event is a change of state of the interlock signal indicative of a field replaceable unit being secured in position. Automatic power management can thus provided with requiring a maintenance engineer to restore power manually, this being achievable simply by the removal and replacement of the field replaceable unit. The field replaceable unit includes an interlock mechanism for locking the field replaceable unit in the electronic equipment.

Abstract: A memory module comprising a printed circuit board having mounting locations for a plurality of memory chips. A line driver having a plurality of outputs for each input is used to drive address and control signals to the chips, with each set of outputs coupled to a subset of the chips. Memory access time is improved by limiting subset size and thereby limiting driver loading. Subsets may correlate to banks of memory chips. Access time is substantially the same for a module with a plurality of banks of memory chips as it is for a module with only one bank of chips. Computer memory may be efficiently exchanged by using only such memory modules, allowing higher clock speed since the range of memory access times is reduced and requiring no change to system memory configuration or settings. Memory modules having differing capacities can be easily interchanged in the system.

Abstract: A microprocessor including an instruction translation unit and a storage control unit is provided. The instruction translation unit scans the instructions to be executed by the microprocessor. The instructions are coded in the instruction set of a CPU core included within the microprocessor. The instruction translation unit detects code sequences which may be more efficiently executed in a DSP core included within the microprocessor, and translates detected code sequences into one or more DSP instructions. The instruction translation unit conveys the translated code sequences to a storage control unit. The storage control unit stores the code sequences along with the address of the original code sequences. As instructions are fetched, the storage control unit is searched. If a translated code sequence is stored for the instructions being fetched, the translated code sequence is substituted for the code sequence.

Abstract: A method and related system for transferring data between systems having different clock domains. A skip signal generation circuit calculates substantially simultaneously with the transfer of data which signals of the faster clock domain should be skipped to ensure proper operation. The skip signal generation circuit makes this determination using values representing the faster and slower frequencies of each clock domain. These values are obtained either from preset values integrated in some form onto the microprocessor substrate, or may be written to the microprocessor by external circuitry and software. The skip signal generation circuit is capable of calculating skip patterns for any ratio of faster to slower frequency and is not constrained to have integer or half-integer ratios of the faster and slower clock domains.

Abstract: Several methods for providing an estimate of the current time are described for use in a computer system including a local time source (e.g., a real time clock or RTC). The local time source is capable of holding one of multiple levels of trust with regard to timekeeping, where the levels of trust are ranked with respect to one another. The level of trust of the local time source is dependent upon a timekeeping accuracy of the local time source. The level of trust of the local time source may also be dependent upon a timekeeping stability, a timekeeping reliability, and/or a timekeeping security (e.g., a tamper resistance) of the local time source.

Abstract: A method is provided, the method comprising testing at least one hot-pluggable peripheral hardware device and a computer system by simulating hot-plugging the at least one hot-pluggable peripheral hardware device using a test fixture inserted between the computer system and the at least one hot-pluggable peripheral hardware device. The method also comprises monitoring at least one effect of testing the at least one hot-pluggable peripheral hardware device and the computer system.

Abstract: A computer system comprising mass storage, a system bus connected to the mass storage, and a processor unit connected to the system bus. A library of standard functions is stored in the mass storage. Each library function is stored in at least one of two versions. The first version is obtained from compilation of firmware code, as is conventional. The second version is obtained from compilation of firmware code and comprises a set of configuration data for loading into a field programmable gate array (FPGA). The computer system is provided with a FPGA connected to the system bus which can be configured by the second versions of the library functions so that these can be performed in the FPGA, instead of in the processor. The apparatus and method are well suited to libraries of database search engine functions. Performance advantages can be obtained by executing function calls in the FPGA.

Abstract: A phase locked loop circuit is provided. The phase locked loop circuit is comprised of a first and second divide-by-N counter, a phase comparator, a voltage controlled oscillator, a clock tree, and a feedback path. The first divide-by-N counter is adapted to receive a first clock signal and provide a second clock signal. The phase comparator has a first and second input terminal and an output terminal. The phase comparator is adapted to compare the phase of signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals. The first input terminal is coupled to receive the second clock signal. The voltage controlled oscillator is coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto. The second divide-by-N counter is coupled to receive the third clock signal and deliver a fourth clock signal.

Abstract: System and method for caching JavaServer Page™ (JSP) component responses. The JSP components may be components that execute on an application server that supports networked applications, such as web applications or other Internet-based applications. One or more client computers, e.g., web servers, may perform requests referencing the JSP components on the application server. The execution of JSP components may be managed by a JSP engine process running on the application server. When a request referencing a JSP is received from a client computer, the JSP engine may first check a JSP response cache to determine whether a valid JSP response satisfying the request is present. If a matching cached response is found, then the response may be retrieved and immediately streamed back to the client. Otherwise, the referenced JSP may be executed. Each JSP file may comprise various SetCacheCriteria( ) method calls.

Abstract: Several methods are described for building and using a network device database. The network includes multiple enclosures, and each enclosure houses at least one device (e.g., a data storage device). The network may be, for example, a storage area network. One embodiment of a method for deriving the addresses of all devices of the network includes repeating the following steps for each enclosure of the network. A command is issued to the enclosure requesting information comprising device identifications (IDs) of all devices within the enclosure. A portion of an address of the enclosure is concatenated with each device ID to form the addresses of all devices within the enclosure. The network may include one or more Fibre Channel Arbitrated Loops (FC-ALs). In this case, the addresses of the enclosures and the devices coupled FC-ALs are fabric addresses. Each enclosure may include a small computer system interface (SCSI) enclosure services (SES) unit.

Abstract: A computer system, for example a network server, comprises a service processor for providing system management functions for the system, and at least one peripheral component that communicates with, and/or is controlled by, the service processor via a communication or control line. The system includes a timer that is initialised by the service processor at a predetermined rate. If the timer is not initialised within a certain time period, it will reset the peripheral device to a different state, e.g. a quiescent state or one that is independent of the service processor. The timer is separate from the service processor and the service processor sends initialisation signals to the timer along the communication or control line.

Abstract: An I/O node for a computer system including an integrated I/O interface. An input/output node for a computer system that is implemented upon an integrated circuit includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may receive and transmit packet transactions on a second link of the packet bus. The packet tunnel may convey selected packet transactions between the first and second transceiver units. The bridge unit may receive particular packet transactions from the first transceiver may transmit transactions corresponding to the particular packet transactions upon a peripheral bus. The I/O interface unit may receive additional packet transactions from the first transceiver unit and may transmit transactions corresponding to the additional packet transactions upon an I/O link.

Abstract: A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

Abstract: A system and method of a forward and/or inverse discrete cosine transform in a video system. In one embodiment, an array of DCT transform coefficients are converted to a two dimensional array of spatial data. The array of DCT transform coefficients are first operated upon by a pre-scale computation unit (implemented in either hardware or software) which multiplies a set of predetermined pre-scale constants with the input coefficients. The pre-scale constants multiplied by the input DCT coefficient matrix form a symmetric pre-scale array. Upon pre-scaling using the symmetric pre-scale factor array, an intermediary array is composed by performing intermediary calculations upon each column vector of the pre-scaled array. The output of this intermediary calculation is composed to form an intermediary array. Subsequently, a set of calculations are performed row-wise upon each row vector of the intermediary array to thereby form the output array of spatial data.

Abstract: The present invention discloses improved heatsink designs and methods for cooling a heat source. One embodiment is a heatsink assembly for removing heat from an electronic component, the heatsink assembly comprising a copper-based core section having a first surface generally adapted to conform to an exposed mating surface of an electronic device and a second surface having a generally convex curvature having a greater surface area than the first surface. An aluminum-based outer section has a first surface comprising a concave curvature that is generally adapted to conform to the convex curvature of the core and a second surface. A plurality of fin elements protrude outwardly from the second surface of the outer section. At least one cooling fan can be positioned to direct airflow onto the fin elements. The core section can comprise a semi-spherical shape and can be joined by a finger-joint type connection to the outer section.

Abstract: A circuit board mount is provided for mounting a circuit board in an electronic equipment housing. The mount is mountable on a surface within the housing and includes a slot for receiving and supporting the circuit board at a first height with respect to the housing surface. The mount further comprises at least one upstand of a second height higher than that of the circuit board, whereby a component can be supported on the upstand without contacting the circuit board. The mount is thus able to support the circuit board and to protect the circuit board during handling of other components within the housing.

Abstract: A memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.

Abstract: The present invention provides management of one or more domains in a processor-based system over a network connection. An apparatus is provided that comprises a first plane adapted to receive a first voltage level and a second plane adapted to receive a second voltage level. The apparatus further comprises a path asymmetrically positioned between the first plane and the second plane, wherein the path is capable of providing the network connection to one or more devices within the processor-based system.