Patents Represented by Attorney, Agent or Law Firm Beall Law Offices
  • Patent number: 6103053
    Abstract: A method for manufacturing a decorative slip-resistant cover system includes the step of impacting a softened polymer film with a plurality of beads such that a section of each bead protrudes from the softened polymer film. The softened polymer film is hardened. The sections of the beads are embedded into an upper layer of the cover system.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: August 15, 2000
    Inventor: Edward T. Saylor, Jr.
  • Patent number: 6099706
    Abstract: A magnetic film forming apparatus includes a film forming source to emit film-forming particles, a substrate holder for holding a substrate on which a magnetic film is formed with the film-forming particles, and a magnetic field generating circuit for applying the magnetic field to the substrate. The magnetic field generating circuit includes two pairs of magnets. Each pair of magnets is composed of two bar-shaped magnets combined in a line apart from each other by a gap of distance d. The pair of magnets have respective pairs of magnetic poles, with the direction of each pair of the magnetic poles being perpendicular to the longitudinal direction of the pair of magnets and having the same orientation. The two pairs of magnets are arranged apart from each other by the distance L in the horizontal x-y plane, substantially symmetrically to the vertical central y-axis of the substrate.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: August 8, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Fumihito Hirabayashi, Satoshi Umehara, Kazuo Sekine
  • Patent number: 6101506
    Abstract: A rack 110 is displayed on a display unit 100. A plurality of file cases 112A to 112D are disposed within the rack 110 in an array. A series of files which have a common file name and different versions are all accommodated in one of the file cases 112A to 112D. Files 116A to 116D of the latest version are shown on the file cases 112A, 112B, 112C and 112D with the other files for the older versions being housed within the file cases 112A, 112B, 112C and 112D, respectively.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: August 8, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hiromi Ukai, Yuichi Yagawa
  • Patent number: 6097404
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: August 1, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 6097663
    Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: August 1, 2000
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corporation
    Inventors: Takao Watanabe, Kazushige Ayukawa, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka
  • Patent number: 6098136
    Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controlling connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: August 1, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
  • Patent number: 6094451
    Abstract: A radio receiver apparatus for receiving a spread spectrum signal in which a signal derived through a level detection of a signal demodulated by a correlative demodulator and a signal obtained by extracting a signal component of a synchronous frequency from a reception synchronizing clock are combined to thereby generate a reference signal having a level which changes in accordance with change of the detected signal, and by comparing the detected signal with the reference signal, the received signal is discriminated.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: July 25, 2000
    Assignees: Hitachi, Ltd., Hitachi Media Electronics Co., Ltd.
    Inventors: Minoru Moteki, Daini Okajima, Kazuhide Tamizu, Kenji Tamaru
  • Patent number: 6093370
    Abstract: Different probes each having a specific base sequence are immobilized to each of independent areas formed on the surface of a substrate, complementary polynucleotides in a sample solution are hybridized to the probes, and each of the independent areas on the substrate is heated and then cooled in sequence, and hence the solution is recovered to extract different polynucleotides separately corresponding to individual probes.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: July 25, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Yasuda, Kazunori Okano, Hirokazu Kato
  • Patent number: 6092362
    Abstract: A gas-turbine combustor (1) provided with a plurality of premix burners (2-a, 2-b) and a diffusion burner (8) and capable of varying the number of the operating premix burners according to the variation of load thereon comprises fuel pipes (3-a, 3-b, 9) connected to the burners, flow control valves (4-a, 4-b, 10) placed respectively in the fuel pipes, a pressure control valves (6, 12) placed in fuel pipes (5, 11), a fuel distribution setting device (14) for controlling the respective openings of the flow control valves according to load, and a pressure ratio setting device (15) for controlling the respective openings of the pressure control valves when the condition of the flow control valves is changed.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: July 25, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Naoyuki Nagafuchi, Kazuyuki Ito, Yotaro Kimura
  • Patent number: 6092232
    Abstract: A disk data reproducing apparatus and a disk data reproducing method for carrying out error correction at fixed intervals independent of demodulation rate fluctuations caused by variable disk revolutions during access, whereby the reliability of error correction is improved. Data are demodulated by use of a regenerative clock signal acquired in keeping with the input data rate, whereas error correction is conducted at a fixed frequency clock signal. Two counters are provided, one being incremented by a signal generated upon detection of a block top, the other counter being incremented by a signal generated when a block of erroneous data is corrected. The two computers are compared in contents so that depending on the result of the comparison, an error correction start signal is generated. Error correction is performed always at fixed intervals regardless of the velocity of reproduction being standard, doubled, quadrupled, or multiplied by a factor of j (j: natural number).
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: July 18, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Nagai, Tomoaki Kudo, Masayuki Hirabayashi, Toshifumi Takeuchi, Hiroyuki Gunji
  • Patent number: 6090630
    Abstract: When an operator touches a reagent interruption key during a continuous analyzing operation of samples in an operation state, the succeeding sampling operation is temporarily suspended and a reagent interruption screen is displayed on a screen of a CRT. A reagent delivery operation as to pipetted samples and a light-measurement operation as to the reaction solution are continued. A waiting time period until an operation for exchanging a reagent bottle can be started is displayed on the screen. When the waiting time period becomes zero minutes, an operator touches an execution key. Then, a screen representing readiness for exchanging a reagent bottle is displayed and an analyzing apparatus is placed in a reagent exchange waiting state for waiting for exchanging the reagent bottle. When an operator touches the execution key after exchanging the reagent bottle, the analysis apparatus reads bar codes o the reagent bottles on the reagent disks and registers the reagent information.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: July 18, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Koakutsu, Atsushi Takahashi
  • Patent number: 6091305
    Abstract: It is an object of the present invention to reduce the amount of spurious noise generated by an emission line spectrum of a signal propagating around the PLL of a PLL frequency synthesizer carrying out digital-signal processing.In order to achieve the object described above, the present invention provides a PLL frequency synthesizer with the following configuration.In a PLL frequency synthesizer having a charge-pump circuit, a waveform converter is provided at a stage behind the charge-pump circuit. The waveform converter converts the voltage waveform on a time axis of a rectangular wave output by the charge-pump circuit into a waveform which: is symmetrical with respect to a predetermined point of time; oscillates so as to have no direct-current component; and has a maximum value of the absolute values of maximums of wave heights thereof located at the center wherein the absolute value decreases uniformly as the wave height is separated farther away from the center.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: July 18, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Nagoya, Yuji Ishida, Ken Takei
  • Patent number: 6090684
    Abstract: A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: July 18, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Yasuko Yoshida, Norio Suzuki, Masayuki Kojima, Kota Funayama
  • Patent number: 6092203
    Abstract: An information accessing method permits the user data belonging to a client-server system to be accessed by a user belonging to another client-server system under proper security and controls the permission for accessing the user data according to the security ranks of the user whose data is to be accessed and the user who wants to access the data. When a client unit issues a request for accessing the user data of the user belonging to the other client-server system, the request for access is sent to an ID conversion unit through a user ID management unit. The ID conversion unit operates to convert a user ID into a guest ID by referring to an ID conversion table, and then sends the request for access to a user ID management unit. The user ID management unit makes sure that the guest ID is registered by referring to the user ID table.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: July 18, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Masayoshi Ooki, Kouji Nishimoto, Nobuyuki Hama
  • Patent number: 6088743
    Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: July 11, 2000
    Assignee: Hitachi, Ltd.
    Inventor: Hiroshi Takeda
  • Patent number: 6087945
    Abstract: A pump failure alarm system which is provided in a hydraulic working machine comprising hydraulic pumps driven by a prime mover, delivery lines joining with one another into one common delivery line on the downstream side, check valves provided in the delivery lines upstream of a point where the delivery lines join with one another, a hydraulic cylinder driven by a hydraulic fluid introduced through the common delivery line, and a hydraulic reservoir. The pump failure alarm system comprises pressure sensors for detecting respective delivery pressures of the hydraulic pumps, bypass lines having one ends connected to the delivery lines at points upstream of the check valves and the other ends connected to the hydraulic reservoir, solenoid switching valves for opening and closing the associated bypass lines, an alarm display unit for giving an alarm in correspondence to each of the hydraulic pumps, and a controller.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: July 11, 2000
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventor: Gen Yasuda
  • Patent number: 6088770
    Abstract: A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is "0", a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: July 11, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Tarui, Koichi Okazawa, Yasuyuki Okada, Toru Shonai, Toshio Okochi, Hideya Akashi
  • Patent number: 6087027
    Abstract: A magnetic head of storage/read separation type in which both a reproducing head of magnetoresistive type and a write head of magnetic induction type are formed through a magnetic shield. The magnetic head includes a ferromagnetic material and an antiferromagnetic material in intimate contact with said ferromagnetic material. At least a part of the antiferromagnetic material acts to bring about unidirectional anisotropy in the ferromagnetic material, and is made of Cr--Mn-based alloy, and at least a part of the ferromagnetic material in intimate contact with the antiferromagnetic material is made of Co or Co-based alloy.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: July 11, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Hoshiya, Yoshihiro Hamakawa, Susumu Soeya, Shigeru Tadokoro
  • Patent number: D428174
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: July 11, 2000
    Assignee: John Manufacturing Ltd.
    Inventor: John Se-Kit Yuen
  • Patent number: D428660
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: July 25, 2000
    Assignee: John Se-Kit Yuen
    Inventor: John Se-Kit Yuen